1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mmc/nvidia,tegra20-sdhci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Secure Digital Host Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 This controller on Tegra family SoCs provides an interface for MMC, SD, and
15 SDIO types of memory cards.
17 This file documents differences between the core properties described by
18 mmc-controller.yaml and the properties for the Tegra SDHCI controller.
24 - nvidia,tegra20-sdhci
25 - nvidia,tegra30-sdhci
26 - nvidia,tegra114-sdhci
27 - nvidia,tegra124-sdhci
28 - nvidia,tegra210-sdhci
29 - nvidia,tegra186-sdhci
30 - nvidia,tegra194-sdhci
33 - const: nvidia,tegra132-sdhci
34 - const: nvidia,tegra124-sdhci
38 - nvidia,tegra194-sdhci
39 - nvidia,tegra234-sdhci
40 - const: nvidia,tegra186-sdhci
49 assigned-clock-parents: true
50 assigned-clock-rates: true
62 - description: module reset
69 description: specify GPIOs for power control
74 - description: memory read client
75 - description: memory write client
79 - const: dma-mem # read
86 $ref: "/schemas/types.yaml#/definitions/phandle"
90 - description: phandle to the core power domain
93 description: Specify the default inbound sampling clock trimmer value for
96 The values are used for compensating trace length differences by
97 adjusting the sampling point. The values are programmed to the Vendor
98 Clock Control Register. Please refer to the reference manual of the SoC
101 The DQS trim values are only used on controllers which support HS400
102 timing. Only SDMMC4 on Tegra210 and Tegra186 supports HS400.
103 $ref: "/schemas/types.yaml#/definitions/uint32"
106 description: Specify the default outbound clock trimmer value.
107 $ref: "/schemas/types.yaml#/definitions/uint32"
110 description: Specify DQS trim value for HS400 timing.
111 $ref: "/schemas/types.yaml#/definitions/uint32"
113 nvidia,pad-autocal-pull-down-offset-1v8:
114 description: Specify drive strength calibration offsets for 1.8 V
116 $ref: "/schemas/types.yaml#/definitions/uint32"
118 nvidia,pad-autocal-pull-down-offset-1v8-timeout:
119 description: Specify drive strength used as a fallback in case the
120 automatic calibration times out on a 1.8 V signaling mode.
121 $ref: "/schemas/types.yaml#/definitions/uint32"
123 nvidia,pad-autocal-pull-down-offset-3v3:
124 description: Specify drive strength calibration offsets for 3.3 V
126 $ref: "/schemas/types.yaml#/definitions/uint32"
128 nvidia,pad-autocal-pull-down-offset-3v3-timeout:
129 description: Specify drive strength used as a fallback in case the
130 automatic calibration times out on a 3.3 V signaling mode.
131 $ref: "/schemas/types.yaml#/definitions/uint32"
133 nvidia,pad-autocal-pull-down-offset-sdr104:
134 description: Specify drive strength calibration offsets for SDR104 mode.
135 $ref: "/schemas/types.yaml#/definitions/uint32"
137 nvidia,pad-autocal-pull-down-offset-hs400:
138 description: Specify drive strength calibration offsets for HS400 mode.
139 $ref: "/schemas/types.yaml#/definitions/uint32"
141 nvidia,pad-autocal-pull-up-offset-1v8:
142 description: Specify drive strength calibration offsets for 1.8 V
144 $ref: "/schemas/types.yaml#/definitions/uint32"
146 nvidia,pad-autocal-pull-up-offset-1v8-timeout:
147 description: Specify drive strength used as a fallback in case the
148 automatic calibration times out on a 1.8 V signaling mode.
149 $ref: "/schemas/types.yaml#/definitions/uint32"
151 nvidia,pad-autocal-pull-up-offset-3v3:
152 description: Specify drive strength calibration offsets for 3.3 V
155 The property values are drive codes which are programmed into the
156 PD_OFFSET and PU_OFFSET sections of the SDHCI_TEGRA_AUTO_CAL_CONFIG
157 register. A higher value corresponds to higher drive strength. Please
158 refer to the reference manual of the SoC for correct values. The SDR104
159 and HS400 timing specific values are used in corresponding modes if
161 $ref: "/schemas/types.yaml#/definitions/uint32"
163 nvidia,pad-autocal-pull-up-offset-3v3-timeout:
164 description: Specify drive strength used as a fallback in case the
165 automatic calibration times out on a 3.3 V signaling mode.
166 $ref: "/schemas/types.yaml#/definitions/uint32"
168 nvidia,pad-autocal-pull-up-offset-sdr104:
169 description: Specify drive strength calibration offsets for SDR104 mode.
170 $ref: "/schemas/types.yaml#/definitions/uint32"
172 nvidia,pad-autocal-pull-up-offset-hs400:
173 description: Specify drive strength calibration offsets for HS400 mode.
174 $ref: "/schemas/types.yaml#/definitions/uint32"
177 description: The presence of this property indicates that the controller
178 operates at a 1.8 V fixed I/O voltage.
179 $ref: "/schemas/types.yaml#/definitions/flag"
190 - $ref: "mmc-controller.yaml"
196 - nvidia,tegra20-sdhci
197 - nvidia,tegra30-sdhci
198 - nvidia,tegra114-sdhci
199 - nvidia,tegra124-sdhci
204 - description: module clock
211 - description: module clock
212 - description: timeout clock
228 const: nvidia,tegra210-sdhci
235 description: pad configuration for 3.3 V
237 description: pad configuration for 1.8 V
238 - const: sdmmc-3v3-drv
239 description: pull-up/down configuration for 3.3 V
240 - const: sdmmc-1v8-drv
241 description: pull-up/down configuration for 1.8 V
243 - const: sdmmc-3v3-drv
244 description: pull-up/down configuration for 3.3 V
245 - const: sdmmc-1v8-drv
246 description: pull-up/down configuration for 1.8 V
248 - const: sdmmc-1v8-drv
249 description: pull-up/down configuration for 1.8 V
257 - nvidia,tegra186-sdhci
258 - nvidia,tegra194-sdhci
264 description: pad configuration for 3.3 V
266 description: pad configuration for 1.8 V
270 unevaluatedProperties: false
274 #include <dt-bindings/interrupt-controller/arm-gic.h>
277 compatible = "nvidia,tegra20-sdhci";
278 reg = <0xc8000200 0x200>;
280 clocks = <&tegra_car 14>;
281 resets = <&tegra_car 14>;
282 reset-names = "sdhci";
283 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
284 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
285 power-gpios = <&gpio 155 0>; /* gpio PT3 */
290 #include <dt-bindings/clock/tegra210-car.h>
291 #include <dt-bindings/interrupt-controller/arm-gic.h>
294 compatible = "nvidia,tegra210-sdhci";
295 reg = <0x700b0000 0x200>;
296 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
298 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
299 clock-names = "sdhci", "tmclk";
300 resets = <&tegra_car 14>;
301 reset-names = "sdhci";
302 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
303 "sdmmc-3v3-drv", "sdmmc-1v8-drv";
304 pinctrl-0 = <&sdmmc1_3v3>;
305 pinctrl-1 = <&sdmmc1_1v8>;
306 pinctrl-2 = <&sdmmc1_3v3_drv>;
307 pinctrl-3 = <&sdmmc1_1v8_drv>;
308 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
309 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
310 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
311 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>;
312 nvidia,default-tap = <0x2>;
313 nvidia,default-trim = <0x4>;
314 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
315 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
316 <&tegra_car TEGRA210_CLK_PLL_C4>;
317 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
318 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>;