1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/mmc/fsl-imx-esdhc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale Enhanced Secure Digital Host Controller (eSDHC) for i.MX
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: sdhci-common.yaml#
16 The Enhanced Secure Digital Host Controller on Freescale i.MX family
17 provides an interface for MMC, SD, and SDIO types of memory cards.
19 This file documents differences between the core properties described
20 by mmc.txt and the properties used by the sdhci-esdhc-imx driver.
39 - const: fsl,imx50-esdhc
40 - const: fsl,imx53-esdhc
46 - const: fsl,imx6sx-usdhc
48 - const: fsl,imx7d-usdhc
49 - const: fsl,imx6sl-usdhc
53 - const: fsl,imx7d-usdhc
61 - const: fsl,imx8mm-usdhc
66 - const: fsl,imx8qxp-usdhc
74 - const: fsl,imx7d-usdhc
80 - const: fsl,imx8mm-usdhc
81 - const: fsl,imx7d-usdhc
87 - const: fsl,imx8qxp-usdhc
88 - const: fsl,imx7d-usdhc
93 - const: fsl,imxrt1050-usdhc
103 boolean, if present, indicate to use controller internal write protection.
107 $ref: /schemas/types.yaml#/definitions/uint32
109 Specify the number of delay cells for override mode.
110 This is used to set the clock delay for DLL(Delay Line) on override mode
111 to select a proper data sampling window in case the clock quality is not good
112 because the signal path is too long on the board. Please refer to eSDHC/uSDHC
113 chapter, DLL (Delay Line) section in RM for details.
117 $ref: /schemas/types.yaml#/definitions/uint32-matrix
119 Specify the voltage range in case there are software transparent level
120 shifters on the outputs of the controller. Two cells are required, first
121 cell specifies minimum slot voltage (mV), second cell specifies maximum
125 - description: value for minimum slot voltage
126 - description: value for maximum slot voltage
129 fsl,tuning-start-tap:
130 $ref: /schemas/types.yaml#/definitions/uint32
132 Specify the start delay cell point when send first CMD19 in tuning procedure.
136 $ref: /schemas/types.yaml#/definitions/uint32
138 Specify the increasing delay cell steps in tuning procedure.
139 The uSDHC use one delay cell as default increasing step to do tuning process.
140 This property allows user to change the tuning step to more than one delay
141 cell which is useful for some special boards or cards when the default
142 tuning step can't find the proper delay window within limited tuning retries.
145 fsl,strobe-dll-delay-target:
146 $ref: /schemas/types.yaml#/definitions/uint32
148 Specify the strobe dll control slave delay target.
149 This delay target programming host controller loopback read clock, and this
150 property allows user to change the delay target for the strobe input read clock.
151 If not use this property, driver default set the delay target to value 7.
152 Only eMMC HS400 mode need to take care of this property.
158 Handle clocks for the sdhc controller.
177 - const: state_100mhz
178 - const: state_200mhz
183 - const: state_100mhz
195 unevaluatedProperties: false
200 compatible = "fsl,imx51-esdhc";
201 reg = <0x70004000 0x4000>;
207 compatible = "fsl,imx51-esdhc";
208 reg = <0x70008000 0x4000>;
210 cd-gpios = <&gpio1 6 0>; /* GPIO1_6 */
211 wp-gpios = <&gpio1 5 0>; /* GPIO1_5 */