Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra124 SoC External Memory Controller
   8
   9 maintainers:
  10   - Thierry Reding <thierry.reding@gmail.com>
  11   - Jon Hunter <jonathanh@nvidia.com>
  12
  13 description: |
  14   The EMC interfaces with the off-chip SDRAM to service the request stream
  15   sent from the memory controller.
  16
  17 properties:
  18   compatible:
  19     const: nvidia,tegra124-emc
  20
  21   reg:
  22     maxItems: 1
  23
  24   clocks:
  25     items:
  26       - description: external memory clock
  27
  28   clock-names:
  29     items:
  30       - const: emc
  31
  32   "#interconnect-cells":
  33     const: 0
  34
  35   nvidia,memory-controller:
  36     $ref: /schemas/types.yaml#/definitions/phandle
  37     description:
  38       phandle of the memory controller node
  39
  40 patternProperties:
  41   "^emc-timings-[0-9]+$":
  42     type: object
  43     properties:
  44       nvidia,ram-code:
  45         $ref: /schemas/types.yaml#/definitions/uint32
  46         description:
  47           value of the RAM_CODE field in the PMC_STRAPPING_OPT_A register that
  48           this timing set is used for
  49
  50     patternProperties:
  51       "^timing-[0-9]+$":
  52         type: object
  53         properties:
  54           clock-frequency:
  55             description:
  56               external memory clock rate in Hz
  57             minimum: 1000000
  58             maximum: 1000000000
  59
  60           nvidia,emc-auto-cal-config:
  61             $ref: /schemas/types.yaml#/definitions/uint32
  62             description:
  63               value of the EMC_AUTO_CAL_CONFIG register for this set of
  64               timings
  65
  66           nvidia,emc-auto-cal-config2:
  67             $ref: /schemas/types.yaml#/definitions/uint32
  68             description:
  69               value of the EMC_AUTO_CAL_CONFIG2 register for this set of
  70               timings
  71
  72           nvidia,emc-auto-cal-config3:
  73             $ref: /schemas/types.yaml#/definitions/uint32
  74             description:
  75               value of the EMC_AUTO_CAL_CONFIG3 register for this set of
  76               timings
  77
  78           nvidia,emc-auto-cal-interval:
  79             description:
  80               pad calibration interval in microseconds
  81             $ref: /schemas/types.yaml#/definitions/uint32
  82             minimum: 0
  83             maximum: 2097151
  84
  85           nvidia,emc-bgbias-ctl0:
  86             $ref: /schemas/types.yaml#/definitions/uint32
  87             description:
  88               value of the EMC_BGBIAS_CTL0 register for this set of timings
  89
  90           nvidia,emc-cfg:
  91             $ref: /schemas/types.yaml#/definitions/uint32
  92             description:
  93               value of the EMC_CFG register for this set of timings
  94
  95           nvidia,emc-cfg-2:
  96             $ref: /schemas/types.yaml#/definitions/uint32
  97             description:
  98               value of the EMC_CFG_2 register for this set of timings
  99
 100           nvidia,emc-ctt-term-ctrl:
 101             $ref: /schemas/types.yaml#/definitions/uint32
 102             description:
 103               value of the EMC_CTT_TERM_CTRL register for this set of timings
 104
 105           nvidia,emc-mode-1:
 106             $ref: /schemas/types.yaml#/definitions/uint32
 107             description:
 108               value of the EMC_MRW register for this set of timings
 109
 110           nvidia,emc-mode-2:
 111             $ref: /schemas/types.yaml#/definitions/uint32
 112             description:
 113               value of the EMC_MRW2 register for this set of timings
 114
 115           nvidia,emc-mode-4:
 116             $ref: /schemas/types.yaml#/definitions/uint32
 117             description:
 118               value of the EMC_MRW4 register for this set of timings
 119
 120           nvidia,emc-mode-reset:
 121             $ref: /schemas/types.yaml#/definitions/uint32
 122             description:
 123               reset value of the EMC_MRS register for this set of timings
 124
 125           nvidia,emc-mrs-wait-cnt:
 126             $ref: /schemas/types.yaml#/definitions/uint32
 127             description:
 128               value of the EMR_MRS_WAIT_CNT register for this set of timings
 129
 130           nvidia,emc-sel-dpd-ctrl:
 131             $ref: /schemas/types.yaml#/definitions/uint32
 132             description:
 133               value of the EMC_SEL_DPD_CTRL register for this set of timings
 134
 135           nvidia,emc-xm2dqspadctrl2:
 136             $ref: /schemas/types.yaml#/definitions/uint32
 137             description:
 138               value of the EMC_XM2DQSPADCTRL2 register for this set of timings
 139
 140           nvidia,emc-zcal-cnt-long:
 141             description:
 142               number of EMC clocks to wait before issuing any commands after
 143               clock change
 144             $ref: /schemas/types.yaml#/definitions/uint32
 145             minimum: 0
 146             maximum: 1023
 147
 148           nvidia,emc-zcal-interval:
 149             $ref: /schemas/types.yaml#/definitions/uint32
 150             description:
 151               value of the EMC_ZCAL_INTERVAL register for this set of timings
 152
 153           nvidia,emc-configuration:
 154             description:
 155               EMC timing characterization data. These are the registers (see
 156               section "15.6.2 EMC Registers" in the TRM) whose values need to
 157               be specified, according to the board documentation.
 158             $ref: /schemas/types.yaml#/definitions/uint32-array
 159             items:
 160               - description: EMC_RC
 161               - description: EMC_RFC
 162               - description: EMC_RFC_SLR
 163               - description: EMC_RAS
 164               - description: EMC_RP
 165               - description: EMC_R2W
 166               - description: EMC_W2R
 167               - description: EMC_R2P
 168               - description: EMC_W2P
 169               - description: EMC_RD_RCD
 170               - description: EMC_WR_RCD
 171               - description: EMC_RRD
 172               - description: EMC_REXT
 173               - description: EMC_WEXT
 174               - description: EMC_WDV
 175               - description: EMC_WDV_MASK
 176               - description: EMC_QUSE
 177               - description: EMC_QUSE_WIDTH
 178               - description: EMC_IBDLY
 179               - description: EMC_EINPUT
 180               - description: EMC_EINPUT_DURATION
 181               - description: EMC_PUTERM_EXTRA
 182               - description: EMC_PUTERM_WIDTH
 183               - description: EMC_PUTERM_ADJ
 184               - description: EMC_CDB_CNTL_1
 185               - description: EMC_CDB_CNTL_2
 186               - description: EMC_CDB_CNTL_3
 187               - description: EMC_QRST
 188               - description: EMC_QSAFE
 189               - description: EMC_RDV
 190               - description: EMC_RDV_MASK
 191               - description: EMC_REFRESH
 192               - description: EMC_BURST_REFRESH_NUM
 193               - description: EMC_PRE_REFRESH_REQ_CNT
 194               - description: EMC_PDEX2WR
 195               - description: EMC_PDEX2RD
 196               - description: EMC_PCHG2PDEN
 197               - description: EMC_ACT2PDEN
 198               - description: EMC_AR2PDEN
 199               - description: EMC_RW2PDEN
 200               - description: EMC_TXSR
 201               - description: EMC_TXSRDLL
 202               - description: EMC_TCKE
 203               - description: EMC_TCKESR
 204               - description: EMC_TPD
 205               - description: EMC_TFAW
 206               - description: EMC_TRPAB
 207               - description: EMC_TCLKSTABLE
 208               - description: EMC_TCLKSTOP
 209               - description: EMC_TREFBW
 210               - description: EMC_FBIO_CFG6
 211               - description: EMC_ODT_WRITE
 212               - description: EMC_ODT_READ
 213               - description: EMC_FBIO_CFG5
 214               - description: EMC_CFG_DIG_DLL
 215               - description: EMC_CFG_DIG_DLL_PERIOD
 216               - description: EMC_DLL_XFORM_DQS0
 217               - description: EMC_DLL_XFORM_DQS1
 218               - description: EMC_DLL_XFORM_DQS2
 219               - description: EMC_DLL_XFORM_DQS3
 220               - description: EMC_DLL_XFORM_DQS4
 221               - description: EMC_DLL_XFORM_DQS5
 222               - description: EMC_DLL_XFORM_DQS6
 223               - description: EMC_DLL_XFORM_DQS7
 224               - description: EMC_DLL_XFORM_DQS8
 225               - description: EMC_DLL_XFORM_DQS9
 226               - description: EMC_DLL_XFORM_DQS10
 227               - description: EMC_DLL_XFORM_DQS11
 228               - description: EMC_DLL_XFORM_DQS12
 229               - description: EMC_DLL_XFORM_DQS13
 230               - description: EMC_DLL_XFORM_DQS14
 231               - description: EMC_DLL_XFORM_DQS15
 232               - description: EMC_DLL_XFORM_QUSE0
 233               - description: EMC_DLL_XFORM_QUSE1
 234               - description: EMC_DLL_XFORM_QUSE2
 235               - description: EMC_DLL_XFORM_QUSE3
 236               - description: EMC_DLL_XFORM_QUSE4
 237               - description: EMC_DLL_XFORM_QUSE5
 238               - description: EMC_DLL_XFORM_QUSE6
 239               - description: EMC_DLL_XFORM_QUSE7
 240               - description: EMC_DLL_XFORM_ADDR0
 241               - description: EMC_DLL_XFORM_ADDR1
 242               - description: EMC_DLL_XFORM_ADDR2
 243               - description: EMC_DLL_XFORM_ADDR3
 244               - description: EMC_DLL_XFORM_ADDR4
 245               - description: EMC_DLL_XFORM_ADDR5
 246               - description: EMC_DLL_XFORM_QUSE8
 247               - description: EMC_DLL_XFORM_QUSE9
 248               - description: EMC_DLL_XFORM_QUSE10
 249               - description: EMC_DLL_XFORM_QUSE11
 250               - description: EMC_DLL_XFORM_QUSE12
 251               - description: EMC_DLL_XFORM_QUSE13
 252               - description: EMC_DLL_XFORM_QUSE14
 253               - description: EMC_DLL_XFORM_QUSE15
 254               - description: EMC_DLI_TRIM_TXDQS0
 255               - description: EMC_DLI_TRIM_TXDQS1
 256               - description: EMC_DLI_TRIM_TXDQS2
 257               - description: EMC_DLI_TRIM_TXDQS3
 258               - description: EMC_DLI_TRIM_TXDQS4
 259               - description: EMC_DLI_TRIM_TXDQS5
 260               - description: EMC_DLI_TRIM_TXDQS6
 261               - description: EMC_DLI_TRIM_TXDQS7
 262               - description: EMC_DLI_TRIM_TXDQS8
 263               - description: EMC_DLI_TRIM_TXDQS9
 264               - description: EMC_DLI_TRIM_TXDQS10
 265               - description: EMC_DLI_TRIM_TXDQS11
 266               - description: EMC_DLI_TRIM_TXDQS12
 267               - description: EMC_DLI_TRIM_TXDQS13
 268               - description: EMC_DLI_TRIM_TXDQS14
 269               - description: EMC_DLI_TRIM_TXDQS15
 270               - description: EMC_DLL_XFORM_DQ0
 271               - description: EMC_DLL_XFORM_DQ1
 272               - description: EMC_DLL_XFORM_DQ2
 273               - description: EMC_DLL_XFORM_DQ3
 274               - description: EMC_DLL_XFORM_DQ4
 275               - description: EMC_DLL_XFORM_DQ5
 276               - description: EMC_DLL_XFORM_DQ6
 277               - description: EMC_DLL_XFORM_DQ7
 278               - description: EMC_XM2CMDPADCTRL
 279               - description: EMC_XM2CMDPADCTRL4
 280               - description: EMC_XM2CMDPADCTRL5
 281               - description: EMC_XM2DQPADCTRL2
 282               - description: EMC_XM2DQPADCTRL3
 283               - description: EMC_XM2CLKPADCTRL
 284               - description: EMC_XM2CLKPADCTRL2
 285               - description: EMC_XM2COMPPADCTRL
 286               - description: EMC_XM2VTTGENPADCTRL
 287               - description: EMC_XM2VTTGENPADCTRL2
 288               - description: EMC_XM2VTTGENPADCTRL3
 289               - description: EMC_XM2DQSPADCTRL3
 290               - description: EMC_XM2DQSPADCTRL4
 291               - description: EMC_XM2DQSPADCTRL5
 292               - description: EMC_XM2DQSPADCTRL6
 293               - description: EMC_DSR_VTTGEN_DRV
 294               - description: EMC_TXDSRVTTGEN
 295               - description: EMC_FBIO_SPARE
 296               - description: EMC_ZCAL_WAIT_CNT
 297               - description: EMC_MRS_WAIT_CNT2
 298               - description: EMC_CTT
 299               - description: EMC_CTT_DURATION
 300               - description: EMC_CFG_PIPE
 301               - description: EMC_DYN_SELF_REF_CONTROL
 302               - description: EMC_QPOP
 303
 304         required:
 305           - clock-frequency
 306           - nvidia,emc-auto-cal-config
 307           - nvidia,emc-auto-cal-config2
 308           - nvidia,emc-auto-cal-config3
 309           - nvidia,emc-auto-cal-interval
 310           - nvidia,emc-bgbias-ctl0
 311           - nvidia,emc-cfg
 312           - nvidia,emc-cfg-2
 313           - nvidia,emc-ctt-term-ctrl
 314           - nvidia,emc-mode-1
 315           - nvidia,emc-mode-2
 316           - nvidia,emc-mode-4
 317           - nvidia,emc-mode-reset
 318           - nvidia,emc-mrs-wait-cnt
 319           - nvidia,emc-sel-dpd-ctrl
 320           - nvidia,emc-xm2dqspadctrl2
 321           - nvidia,emc-zcal-cnt-long
 322           - nvidia,emc-zcal-interval
 323           - nvidia,emc-configuration
 324
 325         additionalProperties: false
 326
 327 required:
 328   - compatible
 329   - reg
 330   - clocks
 331   - clock-names
 332   - nvidia,memory-controller
 333   - "#interconnect-cells"
 334
 335 additionalProperties: false
 336
 337 examples:
 338   - |
 339     #include <dt-bindings/clock/tegra124-car.h>
 340     #include <dt-bindings/interrupt-controller/arm-gic.h>
 341
 342     mc: memory-controller@70019000 {
 343         compatible = "nvidia,tegra124-mc";
 344         reg = <0x70019000 0x1000>;
 345         clocks = <&tegra_car TEGRA124_CLK_MC>;
 346         clock-names = "mc";
 347
 348         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 349
 350         #iommu-cells = <1>;
 351         #reset-cells = <1>;
 352         #interconnect-cells = <1>;
 353     };
 354
 355     external-memory-controller@7001b000 {
 356         compatible = "nvidia,tegra124-emc";
 357         reg = <0x7001b000 0x1000>;
 358         clocks = <&car TEGRA124_CLK_EMC>;
 359         clock-names = "emc";
 360
 361         nvidia,memory-controller = <&mc>;
 362
 363         #interconnect-cells = <0>;
 364
 365         emc-timings-0 {
 366             nvidia,ram-code = <3>;
 367
 368             timing-0 {
 369                 clock-frequency = <12750000>;
 370
 371                 nvidia,emc-auto-cal-config = <0xa1430000>;
 372                 nvidia,emc-auto-cal-config2 = <0x00000000>;
 373                 nvidia,emc-auto-cal-config3 = <0x00000000>;
 374                 nvidia,emc-auto-cal-interval = <0x001fffff>;
 375                 nvidia,emc-bgbias-ctl0 = <0x00000008>;
 376                 nvidia,emc-cfg = <0x73240000>;
 377                 nvidia,emc-cfg-2 = <0x000008c5>;
 378                 nvidia,emc-ctt-term-ctrl = <0x00000802>;
 379                 nvidia,emc-mode-1 = <0x80100003>;
 380                 nvidia,emc-mode-2 = <0x80200008>;
 381                 nvidia,emc-mode-4 = <0x00000000>;
 382                 nvidia,emc-mode-reset = <0x80001221>;
 383                 nvidia,emc-mrs-wait-cnt = <0x000e000e>;
 384                 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
 385                 nvidia,emc-xm2dqspadctrl2 = <0x0130b118>;
 386                 nvidia,emc-zcal-cnt-long = <0x00000042>;
 387                 nvidia,emc-zcal-interval = <0x00000000>;
 388
 389                 nvidia,emc-configuration = <
 390                     0x00000000 /* EMC_RC */
 391                     0x00000003 /* EMC_RFC */
 392                     0x00000000 /* EMC_RFC_SLR */
 393                     0x00000000 /* EMC_RAS */
 394                     0x00000000 /* EMC_RP */
 395                     0x00000004 /* EMC_R2W */
 396                     0x0000000a /* EMC_W2R */
 397                     0x00000003 /* EMC_R2P */
 398                     0x0000000b /* EMC_W2P */
 399                     0x00000000 /* EMC_RD_RCD */
 400                     0x00000000 /* EMC_WR_RCD */
 401                     0x00000003 /* EMC_RRD */
 402                     0x00000003 /* EMC_REXT */
 403                     0x00000000 /* EMC_WEXT */
 404                     0x00000006 /* EMC_WDV */
 405                     0x00000006 /* EMC_WDV_MASK */
 406                     0x00000006 /* EMC_QUSE */
 407                     0x00000002 /* EMC_QUSE_WIDTH */
 408                     0x00000000 /* EMC_IBDLY */
 409                     0x00000005 /* EMC_EINPUT */
 410                     0x00000005 /* EMC_EINPUT_DURATION */
 411                     0x00010000 /* EMC_PUTERM_EXTRA */
 412                     0x00000003 /* EMC_PUTERM_WIDTH */
 413                     0x00000000 /* EMC_PUTERM_ADJ */
 414                     0x00000000 /* EMC_CDB_CNTL_1 */
 415                     0x00000000 /* EMC_CDB_CNTL_2 */
 416                     0x00000000 /* EMC_CDB_CNTL_3 */
 417                     0x00000004 /* EMC_QRST */
 418                     0x0000000c /* EMC_QSAFE */
 419                     0x0000000d /* EMC_RDV */
 420                     0x0000000f /* EMC_RDV_MASK */
 421                     0x00000060 /* EMC_REFRESH */
 422                     0x00000000 /* EMC_BURST_REFRESH_NUM */
 423                     0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
 424                     0x00000002 /* EMC_PDEX2WR */
 425                     0x00000002 /* EMC_PDEX2RD */
 426                     0x00000001 /* EMC_PCHG2PDEN */
 427                     0x00000000 /* EMC_ACT2PDEN */
 428                     0x00000007 /* EMC_AR2PDEN */
 429                     0x0000000f /* EMC_RW2PDEN */
 430                     0x00000005 /* EMC_TXSR */
 431                     0x00000005 /* EMC_TXSRDLL */
 432                     0x00000004 /* EMC_TCKE */
 433                     0x00000005 /* EMC_TCKESR */
 434                     0x00000004 /* EMC_TPD */
 435                     0x00000000 /* EMC_TFAW */
 436                     0x00000000 /* EMC_TRPAB */
 437                     0x00000005 /* EMC_TCLKSTABLE */
 438                     0x00000005 /* EMC_TCLKSTOP */
 439                     0x00000064 /* EMC_TREFBW */
 440                     0x00000000 /* EMC_FBIO_CFG6 */
 441                     0x00000000 /* EMC_ODT_WRITE */
 442                     0x00000000 /* EMC_ODT_READ */
 443                     0x106aa298 /* EMC_FBIO_CFG5 */
 444                     0x002c00a0 /* EMC_CFG_DIG_DLL */
 445                     0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
 446                     0x00064000 /* EMC_DLL_XFORM_DQS0 */
 447                     0x00064000 /* EMC_DLL_XFORM_DQS1 */
 448                     0x00064000 /* EMC_DLL_XFORM_DQS2 */
 449                     0x00064000 /* EMC_DLL_XFORM_DQS3 */
 450                     0x00064000 /* EMC_DLL_XFORM_DQS4 */
 451                     0x00064000 /* EMC_DLL_XFORM_DQS5 */
 452                     0x00064000 /* EMC_DLL_XFORM_DQS6 */
 453                     0x00064000 /* EMC_DLL_XFORM_DQS7 */
 454                     0x00064000 /* EMC_DLL_XFORM_DQS8 */
 455                     0x00064000 /* EMC_DLL_XFORM_DQS9 */
 456                     0x00064000 /* EMC_DLL_XFORM_DQS10 */
 457                     0x00064000 /* EMC_DLL_XFORM_DQS11 */
 458                     0x00064000 /* EMC_DLL_XFORM_DQS12 */
 459                     0x00064000 /* EMC_DLL_XFORM_DQS13 */
 460                     0x00064000 /* EMC_DLL_XFORM_DQS14 */
 461                     0x00064000 /* EMC_DLL_XFORM_DQS15 */
 462                     0x00000000 /* EMC_DLL_XFORM_QUSE0 */
 463                     0x00000000 /* EMC_DLL_XFORM_QUSE1 */
 464                     0x00000000 /* EMC_DLL_XFORM_QUSE2 */
 465                     0x00000000 /* EMC_DLL_XFORM_QUSE3 */
 466                     0x00000000 /* EMC_DLL_XFORM_QUSE4 */
 467                     0x00000000 /* EMC_DLL_XFORM_QUSE5 */
 468                     0x00000000 /* EMC_DLL_XFORM_QUSE6 */
 469                     0x00000000 /* EMC_DLL_XFORM_QUSE7 */
 470                     0x00000000 /* EMC_DLL_XFORM_ADDR0 */
 471                     0x00000000 /* EMC_DLL_XFORM_ADDR1 */
 472                     0x00000000 /* EMC_DLL_XFORM_ADDR2 */
 473                     0x00000000 /* EMC_DLL_XFORM_ADDR3 */
 474                     0x00000000 /* EMC_DLL_XFORM_ADDR4 */
 475                     0x00000000 /* EMC_DLL_XFORM_ADDR5 */
 476                     0x00000000 /* EMC_DLL_XFORM_QUSE8 */
 477                     0x00000000 /* EMC_DLL_XFORM_QUSE9 */
 478                     0x00000000 /* EMC_DLL_XFORM_QUSE10 */
 479                     0x00000000 /* EMC_DLL_XFORM_QUSE11 */
 480                     0x00000000 /* EMC_DLL_XFORM_QUSE12 */
 481                     0x00000000 /* EMC_DLL_XFORM_QUSE13 */
 482                     0x00000000 /* EMC_DLL_XFORM_QUSE14 */
 483                     0x00000000 /* EMC_DLL_XFORM_QUSE15 */
 484                     0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
 485                     0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
 486                     0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
 487                     0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
 488                     0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
 489                     0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
 490                     0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
 491                     0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
 492                     0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
 493                     0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
 494                     0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
 495                     0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
 496                     0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
 497                     0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
 498                     0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
 499                     0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
 500                     0x000fc000 /* EMC_DLL_XFORM_DQ0 */
 501                     0x000fc000 /* EMC_DLL_XFORM_DQ1 */
 502                     0x000fc000 /* EMC_DLL_XFORM_DQ2 */
 503                     0x000fc000 /* EMC_DLL_XFORM_DQ3 */
 504                     0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
 505                     0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
 506                     0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
 507                     0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
 508                     0x10000280 /* EMC_XM2CMDPADCTRL */
 509                     0x00000000 /* EMC_XM2CMDPADCTRL4 */
 510                     0x00111111 /* EMC_XM2CMDPADCTRL5 */
 511                     0x00000000 /* EMC_XM2DQPADCTRL2 */
 512                     0x00000000 /* EMC_XM2DQPADCTRL3 */
 513                     0x77ffc081 /* EMC_XM2CLKPADCTRL */
 514                     0x00000e0e /* EMC_XM2CLKPADCTRL2 */
 515                     0x81f1f108 /* EMC_XM2COMPPADCTRL */
 516                     0x07070004 /* EMC_XM2VTTGENPADCTRL */
 517                     0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
 518                     0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
 519                     0x51451400 /* EMC_XM2DQSPADCTRL3 */
 520                     0x00514514 /* EMC_XM2DQSPADCTRL4 */
 521                     0x00514514 /* EMC_XM2DQSPADCTRL5 */
 522                     0x51451400 /* EMC_XM2DQSPADCTRL6 */
 523                     0x0000003f /* EMC_DSR_VTTGEN_DRV */
 524                     0x00000007 /* EMC_TXDSRVTTGEN */
 525                     0x00000000 /* EMC_FBIO_SPARE */
 526                     0x00000042 /* EMC_ZCAL_WAIT_CNT */
 527                     0x000e000e /* EMC_MRS_WAIT_CNT2 */
 528                     0x00000000 /* EMC_CTT */
 529                     0x00000003 /* EMC_CTT_DURATION */
 530                     0x0000f2f3 /* EMC_CFG_PIPE */
 531                     0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
 532                     0x0000000a /* EMC_QPOP */
 533                 >;
 534             };
 535         };
 536     };