1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: LPDDR3 SDRAM compliant to JEDEC JESD209-3
10 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
24 $ref: /schemas/types.yaml#/definitions/uint32
26 Density in megabits of SDRAM chip.
34 $ref: /schemas/types.yaml#/definitions/uint32
36 IO bus width in bits of SDRAM chip.
42 $ref: /schemas/types.yaml#/definitions/uint32
44 Manufacturer ID value read from Mode Register 5. The property is
45 deprecated, manufacturer should be derived from the compatible.
49 $ref: /schemas/types.yaml#/definitions/uint32-array
55 Revision value of SDRAM chip read from Mode Registers 6 and 7.
62 $ref: /schemas/types.yaml#/definitions/uint32
65 CKE minimum pulse width (HIGH and LOW pulse width) in terms of number
69 $ref: /schemas/types.yaml#/definitions/uint32
72 CKE minimum pulse width during SELF REFRESH (low pulse width during
73 SELF REFRESH) in terms of number of clock cycles.
76 $ref: /schemas/types.yaml#/definitions/uint32
79 DQS output data access time from CK_t/CK_c in terms of number of clock
83 $ref: /schemas/types.yaml#/definitions/uint32
86 Four-bank activate window in terms of number of clock cycles.
89 $ref: /schemas/types.yaml#/definitions/uint32
92 Mode register set command delay in terms of number of clock cycles.
95 $ref: /schemas/types.yaml#/definitions/uint32
98 Additional READ-to-READ delay in chip-to-chip cases in terms of number
102 $ref: /schemas/types.yaml#/definitions/uint32
105 Row active time in terms of number of clock cycles.
108 $ref: /schemas/types.yaml#/definitions/uint32
111 ACTIVATE-to-ACTIVATE command period in terms of number of clock cycles.
114 $ref: /schemas/types.yaml#/definitions/uint32
117 RAS-to-CAS delay in terms of number of clock cycles.
120 $ref: /schemas/types.yaml#/definitions/uint32
123 Refresh Cycle time in terms of number of clock cycles.
126 $ref: /schemas/types.yaml#/definitions/uint32
129 READ data latency in terms of number of clock cycles.
132 $ref: /schemas/types.yaml#/definitions/uint32
135 Row precharge time (all banks) in terms of number of clock cycles.
138 $ref: /schemas/types.yaml#/definitions/uint32
141 Row precharge time (single banks) in terms of number of clock cycles.
144 $ref: /schemas/types.yaml#/definitions/uint32
147 Active bank A to active bank B in terms of number of clock cycles.
150 $ref: /schemas/types.yaml#/definitions/uint32
153 Internal READ to PRECHARGE command delay in terms of number of clock
157 $ref: /schemas/types.yaml#/definitions/uint32
160 Additional WRITE-to-WRITE delay in chip-to-chip cases in terms of number
164 $ref: /schemas/types.yaml#/definitions/uint32
167 WRITE data latency in terms of number of clock cycles.
170 $ref: /schemas/types.yaml#/definitions/uint32
173 WRITE recovery time in terms of number of clock cycles.
176 $ref: /schemas/types.yaml#/definitions/uint32
179 Internal WRITE-to-READ command delay in terms of number of clock cycles.
182 $ref: /schemas/types.yaml#/definitions/uint32
185 Exit power-down to next valid command delay in terms of number of clock
189 $ref: /schemas/types.yaml#/definitions/uint32
192 SELF REFRESH exit to next valid command delay in terms of number of clock
196 "^timings((-[0-9])+|(@[0-9a-f]+))?$":
197 $ref: jedec,lpddr3-timings.yaml
199 The lpddr3 node may have one or more child nodes with timings.
200 Each timing node provides AC timing parameters of the device for a given
201 speed-bin. The user may provide the timings for as many speed-bins as is
209 additionalProperties: false
214 compatible = "samsung,K3QF2F20DB", "jedec,lpddr3";
219 tCKESR-min-tck = <2>;
220 tDQSCK-min-tck = <5>;
223 tR2R-C2C-min-tck = <0>;
233 tW2W-C2C-min-tck = <0>;
241 compatible = "jedec,lpddr3-timings";
242 max-freq = <800000000>;
243 min-freq = <100000000>;