1 # SPDX-License-Identifier: GPL-2.0-only
2 # Copyright (C) 2020 Renesas Electronics Corp.
5 $id: http://devicetree.org/schemas/media/renesas,vin.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Renesas R-Car Video Input (VIN)
11 - Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 The R-Car Video Input (VIN) device provides video input capabilities for the
15 Renesas R-Car family of devices.
17 Each VIN instance has a single parallel input that supports RGB and YUV video,
18 with both external synchronization and BT.656 synchronization for the latter.
19 Depending on the instance the VIN input is connected to external SoC pins, or
20 on Gen3 and RZ/G2 platforms to a CSI-2 receiver.
27 - renesas,vin-r8a7742 # RZ/G1H
28 - renesas,vin-r8a7743 # RZ/G1M
29 - renesas,vin-r8a7744 # RZ/G1N
30 - renesas,vin-r8a7745 # RZ/G1E
31 - renesas,vin-r8a77470 # RZ/G1C
32 - renesas,vin-r8a7790 # R-Car H2
33 - renesas,vin-r8a7791 # R-Car M2-W
34 - renesas,vin-r8a7792 # R-Car V2H
35 - renesas,vin-r8a7793 # R-Car M2-N
36 - renesas,vin-r8a7794 # R-Car E2
37 - const: renesas,rcar-gen2-vin # Generic R-Car Gen2 or RZ/G1
41 - renesas,vin-r8a774a1 # RZ/G2M
42 - renesas,vin-r8a774b1 # RZ/G2N
43 - renesas,vin-r8a774c0 # RZ/G2E
44 - renesas,vin-r8a774e1 # RZ/G2H
45 - renesas,vin-r8a7778 # R-Car M1
46 - renesas,vin-r8a7779 # R-Car H1
47 - renesas,vin-r8a7795 # R-Car H3
48 - renesas,vin-r8a7796 # R-Car M3-W
49 - renesas,vin-r8a77965 # R-Car M3-N
50 - renesas,vin-r8a77970 # R-Car V3M
51 - renesas,vin-r8a77980 # R-Car V3H
52 - renesas,vin-r8a77990 # R-Car E3
53 - renesas,vin-r8a77995 # R-Car D3
70 #The per-board settings for Gen2 and RZ/G1 platforms:
72 $ref: /schemas/graph.yaml#/$defs/port-base
73 unevaluatedProperties: false
75 A node containing a parallel input
79 $ref: video-interfaces.yaml#
80 unevaluatedProperties: false
85 If both HSYNC and VSYNC polarities are not specified, embedded
86 synchronization is selected.
91 If both HSYNC and VSYNC polarities are not specified, embedded
92 synchronization is selected.
95 field-active-even: true
102 description: Polarity of CLKENB signal
109 #The per-board settings for Gen3 and RZ/G2 platforms:
111 description: VIN channel number
112 $ref: /schemas/types.yaml#/definitions/uint32
117 $ref: /schemas/graph.yaml#/properties/ports
121 $ref: /schemas/graph.yaml#/properties/port
123 Input port node, single endpoint describing a parallel input source.
127 $ref: video-interfaces.yaml#
128 unevaluatedProperties: false
133 If both HSYNC and VSYNC polarities are not specified, embedded
134 synchronization is selected.
139 If both HSYNC and VSYNC polarities are not specified, embedded
140 synchronization is selected.
143 field-active-even: true
150 description: Polarity of CLKENB signal
158 $ref: /schemas/graph.yaml#/properties/port
160 Input port node, multiple endpoints describing all the R-Car CSI-2
161 modules connected the VIN.
165 $ref: /schemas/graph.yaml#/properties/endpoint
166 description: Endpoint connected to CSI20.
169 $ref: /schemas/graph.yaml#/properties/endpoint
170 description: Endpoint connected to CSI21.
173 $ref: /schemas/graph.yaml#/properties/endpoint
174 description: Endpoint connected to CSI40.
177 $ref: /schemas/graph.yaml#/properties/endpoint
178 description: Endpoint connected to CSI41.
203 - renesas,vin-r8a7778
204 - renesas,vin-r8a7779
205 - renesas,rcar-gen2-vin
214 additionalProperties: false
217 # Device node example for Gen2 platform
219 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
220 #include <dt-bindings/interrupt-controller/arm-gic.h>
221 #include <dt-bindings/power/r8a7790-sysc.h>
224 compatible = "renesas,vin-r8a7790",
225 "renesas,rcar-gen2-vin";
226 reg = <0xe6ef1000 0x1000>;
227 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
228 clocks = <&cpg CPG_MOD 810>;
229 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
234 remote-endpoint = <&adv7180>;
240 # Device node example for Gen3 platform with only CSI-2
242 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
243 #include <dt-bindings/interrupt-controller/arm-gic.h>
244 #include <dt-bindings/power/r8a7795-sysc.h>
246 vin0: video@e6ef0000 {
247 compatible = "renesas,vin-r8a7795";
248 reg = <0xe6ef0000 0x1000>;
249 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cpg CPG_MOD 811>;
251 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
256 #address-cells = <1>;
260 #address-cells = <1>;
265 vin0csi20: endpoint@0 {
267 remote-endpoint= <&csi20vin0>;
269 vin0csi40: endpoint@2 {
271 remote-endpoint= <&csi40vin0>;
277 # Device node example for Gen3 platform with CSI-2 and parallel
279 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
280 #include <dt-bindings/interrupt-controller/arm-gic.h>
281 #include <dt-bindings/power/r8a77970-sysc.h>
283 vin2: video@e6ef2000 {
284 compatible = "renesas,vin-r8a77970";
285 reg = <0xe6ef2000 0x1000>;
286 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
287 clocks = <&cpg CPG_MOD 809>;
288 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>;
293 #address-cells = <1>;
300 remote-endpoint = <&adv7612_out>;
307 #address-cells = <1>;
312 vin2csi40: endpoint@2 {
314 remote-endpoint = <&csi40vin2>;