Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-decoder.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Mediatek Video Decode Accelerator
   9
  10 maintainers:
  11   - Yunfei Dong <yunfei.dong@mediatek.com>
  12
  13 description: |+
  14   Mediatek Video Decode is the video decode hardware present in Mediatek
  15   SoCs which supports high resolution decoding functionalities.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - mediatek,mt8173-vcodec-dec
  21       - mediatek,mt8183-vcodec-dec
  22
  23   reg:
  24     maxItems: 12
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   clocks:
  30     maxItems: 8
  31
  32   clock-names:
  33     items:
  34       - const: vcodecpll
  35       - const: univpll_d2
  36       - const: clk_cci400_sel
  37       - const: vdec_sel
  38       - const: vdecpll
  39       - const: vencpll
  40       - const: venc_lt_sel
  41       - const: vdec_bus_clk_src
  42
  43   assigned-clocks: true
  44
  45   assigned-clock-parents: true
  46
  47   assigned-clock-rates: true
  48
  49   power-domains:
  50     maxItems: 1
  51
  52   iommus:
  53     minItems: 1
  54     maxItems: 32
  55     description: |
  56       List of the hardware port in respective IOMMU block for current Socs.
  57       Refer to bindings/iommu/mediatek,iommu.yaml.
  58
  59   dma-ranges:
  60     maxItems: 1
  61     description: |
  62       Describes the physical address space of IOMMU maps to memory.
  63
  64   mediatek,vpu:
  65     $ref: /schemas/types.yaml#/definitions/phandle
  66     description:
  67       Describes point to vpu.
  68
  69   mediatek,scp:
  70     $ref: /schemas/types.yaml#/definitions/phandle
  71     description:
  72       Describes point to scp.
  73
  74 required:
  75   - compatible
  76   - reg
  77   - interrupts
  78   - clocks
  79   - clock-names
  80   - iommus
  81   - assigned-clocks
  82   - assigned-clock-parents
  83
  84 allOf:
  85   - if:
  86       properties:
  87         compatible:
  88           contains:
  89             enum:
  90               - mediatek,mt8183-vcodec-dec
  91
  92     then:
  93       required:
  94         - mediatek,scp
  95
  96   - if:
  97       properties:
  98         compatible:
  99           contains:
 100             enum:
 101               - mediatek,mt8173-vcodec-dec
 102
 103     then:
 104       required:
 105         - mediatek,vpu
 106
 107 additionalProperties: false
 108
 109 examples:
 110   - |
 111     #include <dt-bindings/interrupt-controller/arm-gic.h>
 112     #include <dt-bindings/clock/mt8173-clk.h>
 113     #include <dt-bindings/memory/mt8173-larb-port.h>
 114     #include <dt-bindings/interrupt-controller/irq.h>
 115     #include <dt-bindings/power/mt8173-power.h>
 116
 117     vcodec_dec: vcodec@16000000 {
 118       compatible = "mediatek,mt8173-vcodec-dec";
 119       reg = <0x16000000 0x100>,   /*VDEC_SYS*/
 120           <0x16020000 0x1000>,  /*VDEC_MISC*/
 121           <0x16021000 0x800>,   /*VDEC_LD*/
 122           <0x16021800 0x800>,   /*VDEC_TOP*/
 123           <0x16022000 0x1000>,  /*VDEC_CM*/
 124           <0x16023000 0x1000>,  /*VDEC_AD*/
 125           <0x16024000 0x1000>,  /*VDEC_AV*/
 126           <0x16025000 0x1000>,  /*VDEC_PP*/
 127           <0x16026800 0x800>,   /*VP8_VD*/
 128           <0x16027000 0x800>,   /*VP6_VD*/
 129           <0x16027800 0x800>,   /*VP8_VL*/
 130           <0x16028400 0x400>;   /*VP9_VD*/
 131       interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
 132       iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
 133              <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
 134              <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
 135              <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
 136              <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
 137              <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
 138              <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
 139              <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
 140       mediatek,vpu = <&vpu>;
 141       power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
 142       clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
 143              <&topckgen CLK_TOP_UNIVPLL_D2>,
 144              <&topckgen CLK_TOP_CCI400_SEL>,
 145              <&topckgen CLK_TOP_VDEC_SEL>,
 146              <&topckgen CLK_TOP_VCODECPLL>,
 147              <&apmixedsys CLK_APMIXED_VENCPLL>,
 148              <&topckgen CLK_TOP_VENC_LT_SEL>,
 149              <&topckgen CLK_TOP_VCODECPLL_370P5>;
 150       clock-names = "vcodecpll",
 151                   "univpll_d2",
 152                   "clk_cci400_sel",
 153                   "vdec_sel",
 154                   "vdecpll",
 155                   "vencpll",
 156                   "venc_lt_sel",
 157                   "vdec_bus_clk_src";
 158       assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
 159                       <&topckgen CLK_TOP_CCI400_SEL>,
 160                       <&topckgen CLK_TOP_VDEC_SEL>,
 161                       <&apmixedsys CLK_APMIXED_VCODECPLL>,
 162                       <&apmixedsys CLK_APMIXED_VENCPLL>;
 163       assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
 164                              <&topckgen CLK_TOP_UNIVPLL_D2>,
 165                              <&topckgen CLK_TOP_VCODECPLL>;
 166       assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
 167     };