1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
33 - description: Qcom SoCs implementing "arm,mmu-500"
36 - qcom,sc7180-smmu-500
37 - qcom,sdm845-smmu-500
38 - qcom,sm8150-smmu-500
39 - qcom,sm8250-smmu-500
41 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
46 - const: qcom,adreno-smmu
48 - description: Marvell SoCs implementing "arm,mmu-500"
50 - const: marvell,ap806-smmu-500
52 - description: NVIDIA SoCs that program two ARM MMU-500s identically
55 - nvidia,tegra194-smmu
56 - const: nvidia,smmu-500
78 description: The number of global interrupts exposed by the device.
79 $ref: /schemas/types.yaml#/definitions/uint32
81 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
86 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
87 value of 1, each IOMMU specifier represents a distinct stream ID emitted
88 by that device into the relevant SMMU.
90 SMMUs with stream matching support and complex masters may use a value of
91 2, where the second cell of the IOMMU specifier represents an SMR mask to
92 combine with the ID in the first cell. Care must be taken to ensure the
93 set of matched IDs does not result in conflicts.
97 maxItems: 388 # 260 plus 128 contexts
99 Interrupt list, with the first #global-interrupts entries corresponding to
100 the global interrupts and any following entries corresponding to context
101 interrupts, specified in order of their indexing by the SMMU.
103 For SMMUv2 implementations, there must be exactly one interrupt per
104 context bank. In the case of a single, combined interrupt, it must be
105 listed multiple times.
109 Present if page table walks made by the SMMU are cache coherent with the
112 NOTE: this only applies to the SMMU itself, not masters connected
113 upstream of the SMMU.
115 calxeda,smmu-secure-config-access:
118 Enable proper handling of buggy implementations that always use secure
119 access to SMMU configuration registers. In this case non-secure aliases of
120 secure registers have to be used during SMMU configuration.
123 $ref: /schemas/types.yaml#/definitions/uint32
125 For SMMUs supporting stream matching and using #iommu-cells = <1>,
126 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
127 be programmed into the SMRn.MASK field of every stream match register
128 used). For cases where it is desirable to ignore some portion of every
129 Stream ID (e.g. for certain MMU-500 configurations given globally unique
130 input IDs). This property is not valid for SMMUs using stream indexing, or
131 using stream matching with #iommu-cells = <2>, and may be ignored if
132 present in such cases.
141 - description: bus clock required for downstream bus access and for the
143 - description: interface clock required to access smmu's registers
144 through the TCU's programming interface.
152 - '#global-interrupts'
156 additionalProperties: false
164 - nvidia,tegra194-smmu
177 /* SMMU with stream matching or stream indexing */
178 smmu1: iommu@ba5e0000 {
179 compatible = "arm,smmu-v1";
180 reg = <0xba5e0000 0x10000>;
181 #global-interrupts = <2>;
182 interrupts = <0 32 4>,
184 <0 34 4>, /* This is the first context interrupt */
191 /* device with two stream IDs, 0 and 7 */
198 /* SMMU with stream matching */
199 smmu2: iommu@ba5f0000 {
200 compatible = "arm,smmu-v1";
201 reg = <0xba5f0000 0x10000>;
202 #global-interrupts = <2>;
203 interrupts = <0 38 4>,
205 <0 40 4>, /* This is the first context interrupt */
212 /* device with stream IDs 0 and 7 */
214 iommus = <&smmu2 0 0>,
218 /* device with stream IDs 1, 17, 33 and 49 */
220 iommus = <&smmu2 1 0x30>;
224 /* ARM MMU-500 with 10-bit stream ID input configuration */
225 smmu3: iommu@ba600000 {
226 compatible = "arm,mmu-500", "arm,smmu-v2";
227 reg = <0xba600000 0x10000>;
228 #global-interrupts = <2>;
229 interrupts = <0 44 4>,
231 <0 46 4>, /* This is the first context interrupt */
236 /* always ignore appended 5-bit TBU number */
237 stream-match-mask = <0x7c00>;
241 /* bus whose child devices emit one unique 10-bit stream
242 ID each, but may master through multiple SMMU TBUs */
243 iommu-map = <0 &smmu3 0 0x400>;
249 /* Qcom's arm,smmu-v2 implementation */
250 #include <dt-bindings/interrupt-controller/arm-gic.h>
251 #include <dt-bindings/interrupt-controller/irq.h>
252 smmu4: iommu@d00000 {
253 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
254 reg = <0xd00000 0x10000>;
256 #global-interrupts = <1>;
257 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
261 power-domains = <&mmcc 0>;
263 clocks = <&mmcc 123>,
265 clock-names = "bus", "iface";