1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
35 - description: Qcom SoCs implementing "arm,mmu-500"
38 - qcom,sc7180-smmu-500
39 - qcom,sdm845-smmu-500
40 - qcom,sm8150-smmu-500
41 - qcom,sm8250-smmu-500
43 - description: Marvell SoCs implementing "arm,mmu-500"
45 - const: marvell,ap806-smmu-500
47 - description: NVIDIA SoCs that program two ARM MMU-500s identically
50 - nvidia,tegra194-smmu
51 - const: nvidia,smmu-500
73 description: The number of global interrupts exposed by the device.
74 $ref: /schemas/types.yaml#/definitions/uint32
76 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
81 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
82 value of 1, each IOMMU specifier represents a distinct stream ID emitted
83 by that device into the relevant SMMU.
85 SMMUs with stream matching support and complex masters may use a value of
86 2, where the second cell of the IOMMU specifier represents an SMR mask to
87 combine with the ID in the first cell. Care must be taken to ensure the
88 set of matched IDs does not result in conflicts.
92 maxItems: 388 # 260 plus 128 contexts
94 Interrupt list, with the first #global-interrupts entries corresponding to
95 the global interrupts and any following entries corresponding to context
96 interrupts, specified in order of their indexing by the SMMU.
98 For SMMUv2 implementations, there must be exactly one interrupt per
99 context bank. In the case of a single, combined interrupt, it must be
100 listed multiple times.
104 Present if page table walks made by the SMMU are cache coherent with the
107 NOTE: this only applies to the SMMU itself, not masters connected
108 upstream of the SMMU.
110 calxeda,smmu-secure-config-access:
113 Enable proper handling of buggy implementations that always use secure
114 access to SMMU configuration registers. In this case non-secure aliases of
115 secure registers have to be used during SMMU configuration.
118 $ref: /schemas/types.yaml#/definitions/uint32
120 For SMMUs supporting stream matching and using #iommu-cells = <1>,
121 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
122 be programmed into the SMRn.MASK field of every stream match register
123 used). For cases where it is desirable to ignore some portion of every
124 Stream ID (e.g. for certain MMU-500 configurations given globally unique
125 input IDs). This property is not valid for SMMUs using stream indexing, or
126 using stream matching with #iommu-cells = <2>, and may be ignored if
127 present in such cases.
136 - description: bus clock required for downstream bus access and for the
138 - description: interface clock required to access smmu's registers
139 through the TCU's programming interface.
147 - '#global-interrupts'
151 additionalProperties: false
159 - nvidia,tegra194-smmu
172 /* SMMU with stream matching or stream indexing */
173 smmu1: iommu@ba5e0000 {
174 compatible = "arm,smmu-v1";
175 reg = <0xba5e0000 0x10000>;
176 #global-interrupts = <2>;
177 interrupts = <0 32 4>,
179 <0 34 4>, /* This is the first context interrupt */
186 /* device with two stream IDs, 0 and 7 */
193 /* SMMU with stream matching */
194 smmu2: iommu@ba5f0000 {
195 compatible = "arm,smmu-v1";
196 reg = <0xba5f0000 0x10000>;
197 #global-interrupts = <2>;
198 interrupts = <0 38 4>,
200 <0 40 4>, /* This is the first context interrupt */
207 /* device with stream IDs 0 and 7 */
209 iommus = <&smmu2 0 0>,
213 /* device with stream IDs 1, 17, 33 and 49 */
215 iommus = <&smmu2 1 0x30>;
219 /* ARM MMU-500 with 10-bit stream ID input configuration */
220 smmu3: iommu@ba600000 {
221 compatible = "arm,mmu-500", "arm,smmu-v2";
222 reg = <0xba600000 0x10000>;
223 #global-interrupts = <2>;
224 interrupts = <0 44 4>,
226 <0 46 4>, /* This is the first context interrupt */
231 /* always ignore appended 5-bit TBU number */
232 stream-match-mask = <0x7c00>;
236 /* bus whose child devices emit one unique 10-bit stream
237 ID each, but may master through multiple SMMU TBUs */
238 iommu-map = <0 &smmu3 0 0x400>;
244 /* Qcom's arm,smmu-v2 implementation */
245 #include <dt-bindings/interrupt-controller/arm-gic.h>
246 #include <dt-bindings/interrupt-controller/irq.h>
247 smmu4: iommu@d00000 {
248 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
249 reg = <0xd00000 0x10000>;
251 #global-interrupts = <1>;
252 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
253 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
254 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
256 power-domains = <&mmcc 0>;
258 clocks = <&mmcc 123>,
260 clock-names = "bus", "iface";