1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/iommu/arm,smmu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
14 ARM SoCs may contain an implementation of the ARM System Memory
15 Management Unit Architecture, which can be used to provide 1 or 2 stages
16 of address translation to bus masters external to the CPU.
18 The SMMU may also raise interrupts in response to various fault
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
29 - qcom,msm8996-smmu-v2
30 - qcom,msm8998-smmu-v2
33 - description: Qcom SoCs implementing "arm,mmu-500"
36 - qcom,sc7180-smmu-500
37 - qcom,sc7280-smmu-500
38 - qcom,sc8180x-smmu-500
39 - qcom,sdm845-smmu-500
40 - qcom,sm8150-smmu-500
41 - qcom,sm8250-smmu-500
42 - qcom,sm8350-smmu-500
44 - description: Qcom Adreno GPUs implementing "arm,smmu-v2"
49 - const: qcom,adreno-smmu
51 - description: Marvell SoCs implementing "arm,mmu-500"
53 - const: marvell,ap806-smmu-500
55 - description: NVIDIA SoCs that require memory controller interaction
56 and may program multiple ARM MMU-500s identically with the memory
57 controller interleaving translations between multiple instances
58 for improved performance.
61 - nvidia,tegra194-smmu
62 - nvidia,tegra186-smmu
63 - const: nvidia,smmu-500
85 description: The number of global interrupts exposed by the device.
86 $ref: /schemas/types.yaml#/definitions/uint32
88 maximum: 260 # 2 secure, 2 non-secure, and up to 256 perf counters
93 See Documentation/devicetree/bindings/iommu/iommu.txt for details. With a
94 value of 1, each IOMMU specifier represents a distinct stream ID emitted
95 by that device into the relevant SMMU.
97 SMMUs with stream matching support and complex masters may use a value of
98 2, where the second cell of the IOMMU specifier represents an SMR mask to
99 combine with the ID in the first cell. Care must be taken to ensure the
100 set of matched IDs does not result in conflicts.
104 maxItems: 388 # 260 plus 128 contexts
106 Interrupt list, with the first #global-interrupts entries corresponding to
107 the global interrupts and any following entries corresponding to context
108 interrupts, specified in order of their indexing by the SMMU.
110 For SMMUv2 implementations, there must be exactly one interrupt per
111 context bank. In the case of a single, combined interrupt, it must be
112 listed multiple times.
116 Present if page table walks made by the SMMU are cache coherent with the
119 NOTE: this only applies to the SMMU itself, not masters connected
120 upstream of the SMMU.
122 calxeda,smmu-secure-config-access:
125 Enable proper handling of buggy implementations that always use secure
126 access to SMMU configuration registers. In this case non-secure aliases of
127 secure registers have to be used during SMMU configuration.
130 $ref: /schemas/types.yaml#/definitions/uint32
132 For SMMUs supporting stream matching and using #iommu-cells = <1>,
133 specifies a mask of bits to ignore when matching stream IDs (e.g. this may
134 be programmed into the SMRn.MASK field of every stream match register
135 used). For cases where it is desirable to ignore some portion of every
136 Stream ID (e.g. for certain MMU-500 configurations given globally unique
137 input IDs). This property is not valid for SMMUs using stream indexing, or
138 using stream matching with #iommu-cells = <2>, and may be ignored if
139 present in such cases.
148 - description: bus clock required for downstream bus access and for the
150 - description: interface clock required to access smmu's registers
151 through the TCU's programming interface.
159 - '#global-interrupts'
163 additionalProperties: false
171 - nvidia,tegra194-smmu
172 - nvidia,tegra186-smmu
185 /* SMMU with stream matching or stream indexing */
186 smmu1: iommu@ba5e0000 {
187 compatible = "arm,smmu-v1";
188 reg = <0xba5e0000 0x10000>;
189 #global-interrupts = <2>;
190 interrupts = <0 32 4>,
192 <0 34 4>, /* This is the first context interrupt */
199 /* device with two stream IDs, 0 and 7 */
206 /* SMMU with stream matching */
207 smmu2: iommu@ba5f0000 {
208 compatible = "arm,smmu-v1";
209 reg = <0xba5f0000 0x10000>;
210 #global-interrupts = <2>;
211 interrupts = <0 38 4>,
213 <0 40 4>, /* This is the first context interrupt */
220 /* device with stream IDs 0 and 7 */
222 iommus = <&smmu2 0 0>,
226 /* device with stream IDs 1, 17, 33 and 49 */
228 iommus = <&smmu2 1 0x30>;
232 /* ARM MMU-500 with 10-bit stream ID input configuration */
233 smmu3: iommu@ba600000 {
234 compatible = "arm,mmu-500", "arm,smmu-v2";
235 reg = <0xba600000 0x10000>;
236 #global-interrupts = <2>;
237 interrupts = <0 44 4>,
239 <0 46 4>, /* This is the first context interrupt */
244 /* always ignore appended 5-bit TBU number */
245 stream-match-mask = <0x7c00>;
249 /* bus whose child devices emit one unique 10-bit stream
250 ID each, but may master through multiple SMMU TBUs */
251 iommu-map = <0 &smmu3 0 0x400>;
257 /* Qcom's arm,smmu-v2 implementation */
258 #include <dt-bindings/interrupt-controller/arm-gic.h>
259 #include <dt-bindings/interrupt-controller/irq.h>
260 smmu4: iommu@d00000 {
261 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
262 reg = <0xd00000 0x10000>;
264 #global-interrupts = <1>;
265 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
266 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>;
269 power-domains = <&mmcc 0>;
271 clocks = <&mmcc 123>,
273 clock-names = "bus", "iface";