1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/interrupt-controller/mti,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MIPS Global Interrupt Controller
10 - Paul Burton <paulburton@kernel.org>
11 - Thomas Bogendoerfer <tsbogend@alpha.franken.de>
14 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
15 It also supports local (per-processor) interrupts and software-generated
16 interrupts which can be used as IPIs. The GIC also includes a free-running
17 global timer, per-CPU count/compare timers, and a watchdog.
26 The 1st cell is the type of interrupt: local or shared defined in the
27 file 'dt-bindings/interrupt-controller/mips-gic.h'. The 2nd cell is the
28 GIC interrupt number. The 3d cell encodes the interrupt flags setting up
29 the IRQ trigger modes, which are defined in the file
30 'dt-bindings/interrupt-controller/irq.h'.
34 Base address and length of the GIC registers space. If not present,
35 the base address reported by the hardware GCR_GIC_BASE will be used.
38 interrupt-controller: true
40 mti,reserved-cpu-vectors:
42 Specifies the list of CPU interrupt vectors to which the GIC may not
43 route interrupts. This property is ignored if the CPU is started in EIC
46 - $ref: /schemas/types.yaml#definitions/uint32-array
54 mti,reserved-ipi-vectors:
56 Specifies the range of GIC interrupts that are reserved for IPIs.
57 It accepts two values: the 1st is the starting interrupt and the 2nd is
58 the size of the reserved range. If not specified, the driver will
59 allocate the last (2 * number of VPEs in the system).
61 - $ref: /schemas/types.yaml#definitions/uint32-array
71 MIPS GIC includes a free-running global timer, per-CPU count/compare
72 timers, and a watchdog. Currently only the GIC Timer is supported.
79 Interrupt for the GIC local timer, so normally it's suppose to be of
80 <GIC_LOCAL X IRQ_TYPE_NONE> format.
98 additionalProperties: false
100 unevaluatedProperties: false
105 - interrupt-controller
109 #include <dt-bindings/interrupt-controller/mips-gic.h>
110 #include <dt-bindings/interrupt-controller/irq.h>
112 interrupt-controller@1bdc0000 {
113 compatible = "mti,gic";
114 reg = <0x1bdc0000 0x20000>;
115 interrupt-controller;
116 #interrupt-cells = <3>;
117 mti,reserved-cpu-vectors = <7>;
118 mti,reserved-ipi-vectors = <40 8>;
121 compatible = "mti,gic-timer";
122 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
123 clock-frequency = <50000000>;
127 #include <dt-bindings/interrupt-controller/mips-gic.h>
128 #include <dt-bindings/interrupt-controller/irq.h>
130 interrupt-controller@1bdc0000 {
131 compatible = "mti,gic";
132 reg = <0x1bdc0000 0x20000>;
133 interrupt-controller;
134 #interrupt-cells = <3>;
137 compatible = "mti,gic-timer";
138 interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
143 interrupt-controller {
144 compatible = "mti,gic";
145 interrupt-controller;
146 #interrupt-cells = <3>;