Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
   8
   9 maintainers:
  10   - Alexandre Belloni <alexandre.belloni@bootlin.com>
  11
  12 allOf:
  13   - $ref: /schemas/interrupt-controller.yaml#
  14
  15 description: |
  16   the Microsemi Ocelot interrupt controller that is part of the
  17   ICPU. It is connected directly to the MIPS core interrupt
  18   controller.
  19
  20 properties:
  21   compatible:
  22     items:
  23       - enum:
  24           - mscc,ocelot-icpu-intr
  25
  26   '#interrupt-cells':
  27     const: 1
  28
  29   '#address-cells':
  30     const: 0
  31
  32   interrupt-controller: true
  33
  34   reg:
  35     maxItems: 1
  36
  37   interrupts:
  38     maxItems: 1
  39
  40 required:
  41   - compatible
  42   - '#interrupt-cells'
  43   - '#address-cells'
  44   - interrupt-controller
  45   - reg
  46
  47 additionalProperties: false
  48
  49 examples:
  50   - |
  51     intc: interrupt-controller@70000070 {
  52         compatible = "mscc,ocelot-icpu-intr";
  53         reg = <0x70000070 0x70>;
  54         #interrupt-cells = <1>;
  55         #address-cells = <0>;
  56         interrupt-controller;
  57         interrupt-parent = <&cpuintc>;
  58         interrupts = <2>;
  59     };
  60 ...