1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM Generic Interrupt Controller v1 and v2
10 - Marc Zyngier <marc.zyngier@arm.com>
13 ARM SMP cores are often associated with a GIC, providing per processor
14 interrupts (PPI), shared processor interrupts (SPI) and software
15 generated interrupts (SGI).
17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.
18 Secondary GICs are cascaded into the upward interrupt controller and do not
22 - $ref: /schemas/interrupt-controller.yaml#
38 - nvidia,tegra210-agic
49 - const: arm,arm1176jzf-devchip-gic
50 - const: arm,arm11mp-gic
53 - const: brcm,brahma-b15-gic
54 - const: arm,cortex-a15-gic
56 interrupt-controller: true
66 The 1st cell is the interrupt type; 0 for SPI interrupts, 1 for PPI
69 The 2nd cell contains the interrupt number for the interrupt type.
70 SPI interrupts are in the range [0-987]. PPI interrupts are in the
73 The 3rd cell is the flags, encoded as follows:
74 bits[3:0] trigger type and level flags.
75 1 = low-to-high edge triggered
76 2 = high-to-low edge triggered (invalid for SPIs)
77 4 = active high level-sensitive
78 8 = active low level-sensitive (invalid for SPIs).
79 bits[15:8] PPI interrupt cpu mask. Each bit corresponds to each of
80 the 8 possible cpus attached to the GIC. A bit set to '1' indicated
81 the interrupt is wired to that CPU. Only valid for PPI interrupts.
82 Also note that the configurability of PPI interrupts is IMPLEMENTATION
83 DEFINED and as such not guaranteed to be present (most SoC available
84 in 2014 seem to ignore the setting of this flag and use the hardware
89 Specifies base physical address(s) and size of the GIC registers. The
90 first region is the GIC distributor register base and size. The 2nd region
91 is the GIC cpu interface register base and size.
93 For GICv2 with virtualization extensions, additional regions are
94 required for specifying the base physical address and size of the VGIC
95 registers. The first additional region is the GIC virtual interface
96 control register base and size. The 2nd additional region is the GIC
97 virtual cpu interface register base and size.
104 description: Interrupt source of the parent interrupt controller on
105 secondary GICs, or VGIC maintenance interrupt on primary GIC (see
110 description: per-cpu offset within the distributor and cpu interface
111 regions, used when the GIC doesn't have banked registers. The offset
112 is cpu-offset * cpu-nr.
113 $ref: /schemas/types.yaml#/definitions/uint32
120 description: List of names for the GIC clock input(s). Valid clock names
121 depend on the GIC variant.
123 - const: ic_clk # for "arm,arm11mp-gic"
124 - const: PERIPHCLKEN # for "arm,cortex-a15-gic"
125 - items: # for "arm,cortex-a9-gic"
128 - const: clk # for "arm,gic-400" and "nvidia,tegra210"
129 - const: gclk #for "arm,pl390"
145 * GICv2m extension for MSI/MSI-x support (Optional)
147 Certain revisions of GIC-400 supports MSI/MSI-x via V2M register frame(s).
148 This is enabled by specifying v2m sub-node(s).
152 const: arm,gic-v2m-frame
158 description: GICv2m MSI interface register base and size
161 description: When the MSI_TYPER register contains an incorrect value,
162 this property should contain the SPI base of the MSI frame, overriding
164 $ref: /schemas/types.yaml#/definitions/uint32
167 description: When the MSI_TYPER register contains an incorrect value,
168 this property should contain the number of SPIs assigned to the
169 frame, overriding the HW value.
170 $ref: /schemas/types.yaml#/definitions/uint32
177 additionalProperties: false
179 additionalProperties: false
184 intc: interrupt-controller@fff11000 {
185 compatible = "arm,cortex-a9-gic";
186 #interrupt-cells = <3>;
187 #address-cells = <1>;
188 interrupt-controller;
189 reg = <0xfff11000 0x1000>,
195 interrupt-controller@2c001000 {
196 compatible = "arm,cortex-a15-gic";
197 #interrupt-cells = <3>;
198 interrupt-controller;
199 reg = <0x2c001000 0x1000>,
203 interrupts = <1 9 0xf04>;
207 // GICv2m extension for MSI/MSI-x support
208 interrupt-controller@e1101000 {
209 compatible = "arm,gic-400";
210 #interrupt-cells = <3>;
211 #address-cells = <1>;
213 interrupt-controller;
214 interrupts = <1 8 0xf04>;
215 ranges = <0 0xe1100000 0x100000>;
216 reg = <0xe1110000 0x01000>,
217 <0xe112f000 0x02000>,
218 <0xe1140000 0x10000>,
219 <0xe1160000 0x10000>;
222 compatible = "arm,gic-v2m-frame";
224 reg = <0x80000 0x1000>;
230 compatible = "arm,gic-v2m-frame";
232 reg = <0x90000 0x1000>;