Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/gpu/arm,mali-bifrost.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: ARM Mali Bifrost GPU
   8
   9 maintainers:
  10   - Rob Herring <robh@kernel.org>
  11
  12 properties:
  13   $nodename:
  14     pattern: '^gpu@[a-f0-9]+$'
  15
  16   compatible:
  17     items:
  18       - enum:
  19           - amlogic,meson-g12a-mali
  20           - realtek,rtd1619-mali
  21           - rockchip,px30-mali
  22       - const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
  23
  24   reg:
  25     maxItems: 1
  26
  27   interrupts:
  28     items:
  29       - description: Job interrupt
  30       - description: MMU interrupt
  31       - description: GPU interrupt
  32
  33   interrupt-names:
  34     items:
  35       - const: job
  36       - const: mmu
  37       - const: gpu
  38
  39   clocks:
  40     maxItems: 1
  41
  42   mali-supply: true
  43
  44   operating-points-v2: true
  45
  46   power-domains:
  47     maxItems: 1
  48
  49   resets:
  50     maxItems: 2
  51
  52   "#cooling-cells":
  53     const: 2
  54
  55 required:
  56   - compatible
  57   - reg
  58   - interrupts
  59   - interrupt-names
  60   - clocks
  61
  62 additionalProperties: false
  63
  64 allOf:
  65   - if:
  66       properties:
  67         compatible:
  68           contains:
  69             const: amlogic,meson-g12a-mali
  70     then:
  71       required:
  72         - resets
  73
  74 examples:
  75   - |
  76     #include <dt-bindings/interrupt-controller/irq.h>
  77     #include <dt-bindings/interrupt-controller/arm-gic.h>
  78
  79     gpu@ffe40000 {
  80       compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost";
  81       reg = <0xffe40000 0x10000>;
  82       interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
  83              <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
  84              <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
  85       interrupt-names = "job", "mmu", "gpu";
  86       clocks = <&clk 1>;
  87       mali-supply = <&vdd_gpu>;
  88       operating-points-v2 = <&gpu_opp_table>;
  89       resets = <&reset 0>, <&reset 1>;
  90     };
  91
  92     gpu_opp_table: opp_table0 {
  93       compatible = "operating-points-v2";
  94
  95       opp-533000000 {
  96         opp-hz = /bits/ 64 <533000000>;
  97         opp-microvolt = <1250000>;
  98       };
  99       opp-450000000 {
 100         opp-hz = /bits/ 64 <450000000>;
 101         opp-microvolt = <1150000>;
 102       };
 103       opp-400000000 {
 104         opp-hz = /bits/ 64 <400000000>;
 105         opp-microvolt = <1125000>;
 106       };
 107       opp-350000000 {
 108         opp-hz = /bits/ 64 <350000000>;
 109         opp-microvolt = <1075000>;
 110       };
 111       opp-266000000 {
 112         opp-hz = /bits/ 64 <266000000>;
 113         opp-microvolt = <1025000>;
 114       };
 115       opp-160000000 {
 116         opp-hz = /bits/ 64 <160000000>;
 117         opp-microvolt = <925000>;
 118       };
 119       opp-100000000 {
 120         opp-hz = /bits/ 64 <100000000>;
 121         opp-microvolt = <912500>;
 122       };
 123     };
 124
 125 ...