1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/gpio/snps,dw-apb-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare APB GPIO controller
10 Synopsys DesignWare GPIO controllers have a configurable number of ports,
11 each of which are intended to be represented as child nodes with the generic
12 GPIO-controller properties as desribed in this bindings file.
15 - Hoan Tran <hoan@os.amperecomputing.com>
16 - Serge Semin <fancer.lancer@gmail.com>
20 pattern: "^gpio@[0-9a-f]+$"
23 const: snps,dw-apb-gpio
37 - description: APB interface clock source
38 - description: DW GPIO debounce reference clock source
50 "^gpio-(port|controller)@[0-9a-f]+$":
54 const: snps,dw-apb-gpio-port
70 description: The number of GPIO pins exported by the port.
72 $ref: /schemas/types.yaml#/definitions/uint32
79 The interrupts to the parent controller raised when GPIOs generate
80 the interrupts. If the controller provides one combined interrupt
81 for all GPIOs, specify a single interrupt. If the controller provides
82 one interrupt for each GPIO, provide a list of interrupts that
83 correspond to each of the GPIO pins.
87 interrupt-controller: true
99 interrupt-controller: [ interrupts ]
101 additionalProperties: false
103 additionalProperties: false
114 compatible = "snps,dw-apb-gpio";
115 reg = <0x20000 0x1000>;
116 #address-cells = <1>;
120 compatible = "snps,dw-apb-gpio-port";
125 interrupt-controller;
126 #interrupt-cells = <2>;
127 interrupt-parent = <&vic1>;
132 compatible = "snps,dw-apb-gpio-port";