Documentation/devicetree/bindings/gpio/rockchip,gpio-bank.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip GPIO bank
   8
   9 maintainers:
  10   - Heiko Stuebner <heiko@sntech.de>
  11
  12 properties:
  13   compatible:
  14     enum:
  15       - rockchip,gpio-bank
  16       - rockchip,rk3188-gpio-bank0
  17
  18   reg:
  19     maxItems: 1
  20
  21   interrupts:
  22     maxItems: 1
  23
  24   clocks:
  25     maxItems: 1
  26
  27   gpio-controller: true
  28
  29   "#gpio-cells":
  30     const: 2
  31
  32   interrupt-controller: true
  33
  34   "#interrupt-cells":
  35     const: 2
  36
  37 required:
  38   - compatible
  39   - reg
  40   - interrupts
  41   - clocks
  42   - gpio-controller
  43   - "#gpio-cells"
  44   - interrupt-controller
  45   - "#interrupt-cells"
  46
  47 additionalProperties: false
  48
  49 examples:
  50   - |
  51     #include <dt-bindings/interrupt-controller/arm-gic.h>
  52     pinctrl: pinctrl {
  53       #address-cells = <1>;
  54       #size-cells = <1>;
  55       ranges;
  56
  57       gpio0: gpio@2000a000 {
  58         compatible = "rockchip,rk3188-gpio-bank0";
  59         reg = <0x2000a000 0x100>;
  60         interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
  61         clocks = <&clk_gates8 9>;
  62
  63         gpio-controller;
  64         #gpio-cells = <2>;
  65
  66         interrupt-controller;
  67         #interrupt-cells = <2>;
  68       };
  69
  70       gpio1: gpio@2003c000 {
  71         compatible = "rockchip,gpio-bank";
  72         reg = <0x2003c000 0x100>;
  73         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
  74         clocks = <&clk_gates8 10>;
  75
  76         gpio-controller;
  77         #gpio-cells = <2>;
  78
  79         interrupt-controller;
  80         #interrupt-cells = <2>;
  81       };
  82     };