Documentation/devicetree/bindings/dma/qcom,gpi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/dma/qcom,gpi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Technologies Inc GPI DMA controller
   8
   9 maintainers:
  10   - Vinod Koul <vkoul@kernel.org>
  11
  12 description: |
  13   QCOM GPI DMA controller provides DMA capabilities for
  14   peripheral buses such as I2C, UART, and SPI.
  15
  16 allOf:
  17   - $ref: "dma-controller.yaml#"
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - qcom,sdm845-gpi-dma
  23       - qcom,sm8150-gpi-dma
  24       - qcom,sm8250-gpi-dma
  25
  26   reg:
  27     maxItems: 1
  28
  29   interrupts:
  30     description:
  31       Interrupt lines for each GPI instance
  32     minItems: 1
  33     maxItems: 13
  34
  35   "#dma-cells":
  36     const: 3
  37     description: >
  38       DMA clients must use the format described in dma.txt, giving a phandle
  39       to the DMA controller plus the following 3 integer cells:
  40       - channel: if set to 0xffffffff, any available channel will be allocated
  41         for the client. Otherwise, the exact channel specified will be used.
  42       - seid: serial id of the client as defined in the SoC documentation.
  43       - client: type of the client as defined in dt-bindings/dma/qcom-gpi.h
  44
  45   iommus:
  46     maxItems: 1
  47
  48   dma-channels:
  49     maximum: 31
  50
  51   dma-channel-mask:
  52     maxItems: 1
  53
  54 required:
  55   - compatible
  56   - reg
  57   - interrupts
  58   - "#dma-cells"
  59   - iommus
  60   - dma-channels
  61   - dma-channel-mask
  62
  63 additionalProperties: false
  64
  65 examples:
  66   - |
  67     #include <dt-bindings/interrupt-controller/arm-gic.h>
  68     #include <dt-bindings/dma/qcom-gpi.h>
  69     gpi_dma0: dma-controller@800000 {
  70         compatible = "qcom,sdm845-gpi-dma";
  71         #dma-cells = <3>;
  72         reg = <0x00800000 0x60000>;
  73         iommus = <&apps_smmu 0x0016 0x0>;
  74         dma-channels = <13>;
  75         dma-channel-mask = <0xfa>;
  76         interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
  77                      <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
  78                      <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
  79                      <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
  80                      <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
  81                      <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
  82                      <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
  83                      <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
  84                      <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
  85                      <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
  86                      <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
  87                      <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
  88                      <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
  89     };
  90
  91 ...