1 * Freescale Smart Direct Memory Access (SDMA) Controller for i.MX
4 - compatible : Should be one of
6 "fsl,imx31-sdma", "fsl,imx31-to1-sdma", "fsl,imx31-to2-sdma"
7 "fsl,imx35-sdma", "fsl,imx35-to1-sdma", "fsl,imx35-to2-sdma"
17 The -to variants should be preferred since they allow to determine the
18 correct ROM script addresses needed for the driver to work without additional
20 - reg : Should contain SDMA registers location and length
21 - interrupts : Should contain SDMA interrupt
22 - #dma-cells : Must be <3>.
23 The first cell specifies the DMA request/event ID. See details below
24 about the second and third cell.
25 - fsl,sdma-ram-script-name : Should contain the full path of SDMA RAM
28 The second cell of dma phandle specifies the peripheral type of DMA transfer.
29 The full ID of peripheral types can be found below.
45 12 External peripheral
46 13 Memory Stick Host Controller
47 14 Shared Memory Stick Host Controller
55 22 SSI Dual FIFO (needs firmware ver >= 2)
59 The third cell specifies the transfer priority as below.
62 -------------------------
69 - gpr : The phandle to the General Purpose Register (GPR) node.
70 - fsl,sdma-event-remap : Register bits of sdma event remap, the format is
72 reg is the GPR register offset.
73 shift is the bit position inside the GPR register.
74 val is the value of the bit (0 or 1).
79 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
80 reg = <0x83fb0000 0x4000>;
83 fsl,sdma-ram-script-name = "sdma-imx51.bin";
86 DMA clients connected to the i.MX SDMA controller must use the format
87 described in the dma.txt file.
92 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi";
93 reg = <0x70014000 0x4000>;
96 dmas = <&sdma 24 1 0>,
98 dma-names = "rx", "tx";
99 fsl,fifo-depth = <15>;
102 Using the fsl,sdma-event-remap property:
104 If we want to use SDMA on the SAI1 port on a MX6SX:
108 /* SDMA events remap for SAI1_RX and SAI1_TX */
109 fsl,sdma-event-remap = <0 15 1>, <0 16 1>;
112 The fsl,sdma-event-remap property in this case has two values:
113 - <0 15 1> means that the offset is 0, so GPR0 is the register of the
114 SDMA remap. Bit 15 of GPR0 selects between UART4_RX and SAI1_RX.
115 Setting bit 15 to 1 selects SAI1_RX.
116 - <0 16 1> means that the offset is 0, so GPR0 is the register of the
117 SDMA remap. Bit 16 of GPR0 selects between UART4_TX and SAI1_TX.
118 Setting bit 16 to 1 selects SAI1_TX.