Documentation/devicetree/bindings/display/samsung/samsung,exynos-hdmi.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/samsung/samsung,exynos-hdmi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Samsung Exynos SoC HDMI
   8
   9 maintainers:
  10   - Inki Dae <inki.dae@samsung.com>
  11   - Joonyoung Shim <jy0922.shim@samsung.com>
  12   - Seung-Woo Kim <sw0312.kim@samsung.com>
  13   - Kyungmin Park <kyungmin.park@samsung.com>
  14   - Krzysztof Kozlowski <krzk@kernel.org>
  15
  16 properties:
  17   compatible:
  18     enum:
  19       - samsung,exynos4210-hdmi
  20       - samsung,exynos4212-hdmi
  21       - samsung,exynos5420-hdmi
  22       - samsung,exynos5433-hdmi
  23
  24   clocks:
  25     minItems: 5
  26     maxItems: 10
  27
  28   clock-names:
  29     minItems: 5
  30     maxItems: 10
  31
  32   ddc:
  33     $ref: /schemas/types.yaml#/definitions/phandle
  34     description:
  35       Phandle to the HDMI DDC node.
  36
  37   hdmi-en-supply:
  38     description:
  39       Provides voltage source for DCC lines available on HDMI connector. When
  40       there is no power provided for DDC epprom, some TV-sets do not pulls up
  41       HPD (hot plug detect) line, what causes HDMI block to stay turned off.
  42       When provided, the regulator allows TV-set correctly signal HPD event.
  43
  44   hpd-gpios:
  45     maxItems: 1
  46     description:
  47       A GPIO line connected to HPD
  48
  49   interrupts:
  50     maxItems: 1
  51
  52   phy:
  53     $ref: /schemas/types.yaml#/definitions/phandle
  54     description: Phandle to the HDMI PHY node.
  55
  56   ports:
  57     $ref: /schemas/graph.yaml#/properties/ports
  58     description:
  59       Contains a port which is connected to mic node.
  60
  61   power-domains:
  62     maxItems: 1
  63
  64   reg:
  65     maxItems: 1
  66
  67   samsung,syscon-phandle:
  68     $ref: /schemas/types.yaml#/definitions/phandle
  69     description:
  70       Phandle to the PMU system controller node.
  71
  72   samsung,sysreg-phandle:
  73     $ref: /schemas/types.yaml#/definitions/phandle
  74     description:
  75       Phandle to DISP system controller interface.
  76
  77   '#sound-dai-cells':
  78     const: 0
  79
  80   vdd-supply:
  81     description:
  82       VDD 1.0V HDMI TX.
  83
  84   vdd_osc-supply:
  85     description:
  86       VDD 1.8V HDMI OSC.
  87
  88   vdd_pll-supply:
  89     description:
  90       VDD 1.0V HDMI PLL.
  91
  92 required:
  93   - compatible
  94   - clocks
  95   - clock-names
  96   - ddc
  97   - hpd-gpios
  98   - interrupts
  99   - phy
 100   - reg
 101   - samsung,syscon-phandle
 102   - '#sound-dai-cells'
 103   - vdd-supply
 104   - vdd_osc-supply
 105   - vdd_pll-supply
 106
 107 allOf:
 108   - if:
 109       properties:
 110         compatible:
 111           contains:
 112             const: samsung,exynos5433-hdmi
 113     then:
 114       properties:
 115         clocks:
 116           items:
 117             - description: Gate of HDMI IP APB bus.
 118             - description: Gate of HDMI-PHY IP APB bus.
 119             - description: Gate of HDMI TMDS clock.
 120             - description: Gate of HDMI pixel clock.
 121             - description: TMDS clock generated by HDMI-PHY.
 122             - description: MUX used to switch between oscclk and tmds_clko,
 123                 respectively if HDMI-PHY is off and operational.
 124             - description: Pixel clock generated by HDMI-PHY.
 125             - description: MUX used to switch between oscclk and pixel_clko,
 126                 respectively if HDMI-PHY is off and operational.
 127             - description: Oscillator clock, used as parent of following *_user
 128                 clocks in case HDMI-PHY is not operational.
 129             - description: Gate of HDMI SPDIF clock.
 130         clock-names:
 131           items:
 132             - const: hdmi_pclk
 133             - const: hdmi_i_pclk
 134             - const: i_tmds_clk
 135             - const: i_pixel_clk
 136             - const: tmds_clko
 137             - const: tmds_clko_user
 138             - const: pixel_clko
 139             - const: pixel_clko_user
 140             - const: oscclk
 141             - const: i_spdif_clk
 142       required:
 143         - samsung,sysreg-phandle
 144     else:
 145       properties:
 146         clocks:
 147           items:
 148             - description: Gate of HDMI IP bus clock.
 149             - description: Gate of HDMI special clock.
 150             - description: Pixel special clock, one of the two possible inputs
 151                 of HDMI clock mux.
 152             - description: HDMI PHY clock output, one of two possible inputs of
 153                 HDMI clock mux.
 154             - description: It is required by the driver to switch between the 2
 155                 parents i.e. sclk_pixel and sclk_hdmiphy. If hdmiphy is stable
 156                 after configuration, parent is set to sclk_hdmiphy else
 157                 sclk_pixel.
 158         clock-names:
 159           items:
 160             - const: hdmi
 161             - const: sclk_hdmi
 162             - const: sclk_pixel
 163             - const: sclk_hdmiphy
 164             - const: mout_hdmi
 165
 166 additionalProperties: false
 167
 168 examples:
 169   - |
 170     #include <dt-bindings/clock/exynos5433.h>
 171     #include <dt-bindings/gpio/gpio.h>
 172     #include <dt-bindings/interrupt-controller/arm-gic.h>
 173
 174     hdmi@13970000 {
 175         compatible = "samsung,exynos5433-hdmi";
 176         reg = <0x13970000 0x70000>;
 177         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
 178         clocks = <&cmu_disp CLK_PCLK_HDMI>,
 179                  <&cmu_disp CLK_PCLK_HDMIPHY>,
 180                  <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO>,
 181                  <&cmu_disp CLK_PHYCLK_HDMI_PIXEL>,
 182                  <&cmu_disp CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY>,
 183                  <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER>,
 184                  <&cmu_disp CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY>,
 185                  <&cmu_disp CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER>,
 186                  <&xxti>,
 187                  <&cmu_disp CLK_SCLK_HDMI_SPDIF>;
 188         clock-names = "hdmi_pclk",
 189                       "hdmi_i_pclk",
 190                       "i_tmds_clk",
 191                       "i_pixel_clk",
 192                       "tmds_clko",
 193                       "tmds_clko_user",
 194                       "pixel_clko",
 195                       "pixel_clko_user",
 196                       "oscclk",
 197                       "i_spdif_clk";
 198         phy = <&hdmiphy>;
 199         ddc = <&hsi2c_11>;
 200         samsung,syscon-phandle = <&pmu_system_controller>;
 201         samsung,sysreg-phandle = <&syscon_disp>;
 202         #sound-dai-cells = <0>;
 203
 204         hpd-gpios = <&gpa3 0 GPIO_ACTIVE_HIGH>;
 205         vdd-supply = <&ldo6_reg>;
 206         vdd_osc-supply = <&ldo7_reg>;
 207         vdd_pll-supply = <&ldo6_reg>;
 208
 209         ports {
 210             #address-cells = <1>;
 211             #size-cells = <0>;
 212
 213             port@0 {
 214                 reg = <0>;
 215                 hdmi_to_tv: endpoint {
 216                     remote-endpoint = <&tv_to_hdmi>;
 217                 };
 218             };
 219
 220             port@1 {
 221                 reg = <1>;
 222                 hdmi_to_mhl: endpoint {
 223                     remote-endpoint = <&mhl_to_hdmi>;
 224                 };
 225             };
 226         };
 227     };