Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-hdmi.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip DWC HDMI TX Encoder
   8
   9 maintainers:
  10   - Mark Yao <markyao0591@gmail.com>
  11
  12 description: |
  13   The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
  14   with a companion PHY IP.
  15
  16 allOf:
  17   - $ref: ../bridge/synopsys,dw-hdmi.yaml#
  18
  19 properties:
  20   compatible:
  21     enum:
  22       - rockchip,rk3228-dw-hdmi
  23       - rockchip,rk3288-dw-hdmi
  24       - rockchip,rk3328-dw-hdmi
  25       - rockchip,rk3399-dw-hdmi
  26       - rockchip,rk3568-dw-hdmi
  27
  28   reg-io-width:
  29     const: 4
  30
  31   avdd-0v9-supply:
  32     description:
  33       A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
  34       varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
  35       HDMI_AVDD_1V0.
  36
  37   avdd-1v8-supply:
  38     description:
  39       A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
  40       SoC usually is HDMI_TX_AVDD_1V8.
  41
  42   clocks:
  43     minItems: 2
  44     items:
  45       - {}
  46       - {}
  47       # The next three clocks are all optional, but shall be specified in this
  48       # order when present.
  49       - description: The HDMI CEC controller main clock
  50       - description: Power for GRF IO
  51       - description: External clock for some HDMI PHY (old clock name, deprecated)
  52       - description: External clock for some HDMI PHY (new name)
  53
  54   clock-names:
  55     minItems: 2
  56     items:
  57       - {}
  58       - {}
  59       - enum:
  60           - cec
  61           - grf
  62           - vpll
  63           - ref
  64       - enum:
  65           - grf
  66           - vpll
  67           - ref
  68       - enum:
  69           - vpll
  70           - ref
  71
  72   ddc-i2c-bus:
  73     $ref: /schemas/types.yaml#/definitions/phandle
  74     description:
  75       The HDMI DDC bus can be connected to either a system I2C master or the
  76       functionally-reduced I2C master contained in the DWC HDMI. When connected
  77       to a system I2C master this property contains a phandle to that I2C
  78       master controller.
  79
  80   phys:
  81     maxItems: 1
  82     description: The HDMI PHY
  83
  84   phy-names:
  85     const: hdmi
  86
  87   pinctrl-names:
  88     description:
  89       The unwedge pinctrl entry shall drive the DDC SDA line low. This is
  90       intended to work around a hardware errata that can cause the DDC I2C
  91       bus to be wedged.
  92     minItems: 1
  93     items:
  94       - const: default
  95       - const: unwedge
  96
  97   power-domains:
  98     maxItems: 1
  99
 100   ports:
 101     $ref: /schemas/graph.yaml#/properties/ports
 102
 103     properties:
 104       port@0:
 105         $ref: /schemas/graph.yaml#/properties/port
 106         description: Input of the DWC HDMI TX
 107         properties:
 108           endpoint:
 109             description: Connection to the VOP
 110           endpoint@0:
 111             description: Connection to the VOPB
 112           endpoint@1:
 113             description: Connection to the VOPL
 114       port@1:
 115         $ref: /schemas/graph.yaml#/properties/port
 116         description: Output of the DWC HDMI TX
 117
 118     required:
 119       - port@0
 120       - port@1
 121
 122   rockchip,grf:
 123     $ref: /schemas/types.yaml#/definitions/phandle
 124     description:
 125       phandle to the GRF to mux vopl/vopb.
 126
 127 required:
 128   - compatible
 129   - reg
 130   - reg-io-width
 131   - clocks
 132   - clock-names
 133   - interrupts
 134   - ports
 135   - rockchip,grf
 136
 137 unevaluatedProperties: false
 138
 139 examples:
 140   - |
 141     #include <dt-bindings/clock/rk3288-cru.h>
 142     #include <dt-bindings/interrupt-controller/arm-gic.h>
 143     #include <dt-bindings/interrupt-controller/irq.h>
 144     #include <dt-bindings/power/rk3288-power.h>
 145
 146     hdmi: hdmi@ff980000 {
 147         compatible = "rockchip,rk3288-dw-hdmi";
 148         reg = <0xff980000 0x20000>;
 149         reg-io-width = <4>;
 150         interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
 151         clocks = <&cru  PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>;
 152         clock-names = "iahb", "isfr";
 153         ddc-i2c-bus = <&i2c5>;
 154         power-domains = <&power RK3288_PD_VIO>;
 155         rockchip,grf = <&grf>;
 156
 157         ports {
 158             #address-cells = <1>;
 159             #size-cells = <0>;
 160
 161             port@0 {
 162                 reg = <0>;
 163                 #address-cells = <1>;
 164                 #size-cells = <0>;
 165
 166                 hdmi_in_vopb: endpoint@0 {
 167                     reg = <0>;
 168                     remote-endpoint = <&vopb_out_hdmi>;
 169                 };
 170
 171                 hdmi_in_vopl: endpoint@1 {
 172                     reg = <1>;
 173                     remote-endpoint = <&vopl_out_hdmi>;
 174                 };
 175             };
 176
 177             port@1 {
 178                 reg = <1>;
 179
 180                 hdmi_out_con: endpoint {
 181                     remote-endpoint = <&hdmi_con_in>;
 182                 };
 183             };
 184         };
 185     };
 186
 187 ...