Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm Display DSI controller
   8
   9 maintainers:
  10   - Krishna Manikandan <mkrishn@codeaurora.org>
  11
  12 allOf:
  13   - $ref: "../dsi-controller.yaml#"
  14
  15 properties:
  16   compatible:
  17     items:
  18       - const: qcom,mdss-dsi-ctrl
  19
  20   reg:
  21     maxItems: 1
  22
  23   reg-names:
  24     const: dsi_ctrl
  25
  26   interrupts:
  27     maxItems: 1
  28
  29   clocks:
  30     items:
  31       - description: Display byte clock
  32       - description: Display byte interface clock
  33       - description: Display pixel clock
  34       - description: Display escape clock
  35       - description: Display AHB clock
  36       - description: Display AXI clock
  37
  38   clock-names:
  39     items:
  40       - const: byte
  41       - const: byte_intf
  42       - const: pixel
  43       - const: core
  44       - const: iface
  45       - const: bus
  46
  47   phys:
  48     maxItems: 1
  49
  50   phy-names:
  51     const: dsi
  52
  53   "#address-cells": true
  54
  55   "#size-cells": true
  56
  57   syscon-sfpb:
  58     description: A phandle to mmss_sfpb syscon node (only for DSIv2).
  59     $ref: "/schemas/types.yaml#/definitions/phandle"
  60
  61   qcom,dual-dsi-mode:
  62     type: boolean
  63     description: |
  64       Indicates if the DSI controller is driving a panel which needs
  65       2 DSI links.
  66
  67   power-domains:
  68     maxItems: 1
  69
  70   operating-points-v2: true
  71
  72   ports:
  73     $ref: "/schemas/graph.yaml#/properties/ports"
  74     description: |
  75       Contains DSI controller input and output ports as children, each
  76       containing one endpoint subnode.
  77
  78     properties:
  79       port@0:
  80         $ref: "/schemas/graph.yaml#/$defs/port-base"
  81         unevaluatedProperties: false
  82         description: |
  83           Input endpoints of the controller.
  84         properties:
  85           endpoint:
  86             $ref: /schemas/media/video-interfaces.yaml#
  87             unevaluatedProperties: false
  88             properties:
  89               data-lanes:
  90                 maxItems: 4
  91                 minItems: 4
  92                 items:
  93                   enum: [ 0, 1, 2, 3 ]
  94
  95       port@1:
  96         $ref: "/schemas/graph.yaml#/$defs/port-base"
  97         unevaluatedProperties: false
  98         description: |
  99           Output endpoints of the controller.
 100         properties:
 101           endpoint:
 102             $ref: /schemas/media/video-interfaces.yaml#
 103             unevaluatedProperties: false
 104             properties:
 105               data-lanes:
 106                 maxItems: 4
 107                 minItems: 4
 108                 items:
 109                   enum: [ 0, 1, 2, 3 ]
 110
 111     required:
 112       - port@0
 113       - port@1
 114
 115 required:
 116   - compatible
 117   - reg
 118   - reg-names
 119   - interrupts
 120   - clocks
 121   - clock-names
 122   - phys
 123   - phy-names
 124   - power-domains
 125   - operating-points-v2
 126   - ports
 127
 128 additionalProperties: false
 129
 130 examples:
 131   - |
 132      #include <dt-bindings/interrupt-controller/arm-gic.h>
 133      #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
 134      #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 135      #include <dt-bindings/power/qcom-rpmpd.h>
 136
 137      dsi@ae94000 {
 138            compatible = "qcom,mdss-dsi-ctrl";
 139            reg = <0x0ae94000 0x400>;
 140            reg-names = "dsi_ctrl";
 141
 142            #address-cells = <1>;
 143            #size-cells = <0>;
 144
 145            interrupt-parent = <&mdss>;
 146            interrupts = <4>;
 147
 148            clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
 149                     <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
 150                     <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
 151                     <&dispcc DISP_CC_MDSS_ESC0_CLK>,
 152                     <&dispcc DISP_CC_MDSS_AHB_CLK>,
 153                     <&dispcc DISP_CC_MDSS_AXI_CLK>;
 154            clock-names = "byte",
 155                          "byte_intf",
 156                          "pixel",
 157                          "core",
 158                          "iface",
 159                          "bus";
 160
 161            phys = <&dsi0_phy>;
 162            phy-names = "dsi";
 163
 164            power-domains = <&rpmhpd SC7180_CX>;
 165            operating-points-v2 = <&dsi_opp_table>;
 166
 167            ports {
 168                   #address-cells = <1>;
 169                   #size-cells = <0>;
 170
 171                   port@0 {
 172                           reg = <0>;
 173                           dsi0_in: endpoint {
 174                                    remote-endpoint = <&dpu_intf1_out>;
 175                           };
 176                   };
 177
 178                   port@1 {
 179                           reg = <1>;
 180                           dsi0_out: endpoint {
 181                                    remote-endpoint = <&sn65dsi86_in>;
 182                                    data-lanes = <0 1 2 3>;
 183                           };
 184                   };
 185            };
 186      };
 187 ...