1 # SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
4 $id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DPU dt properties for SC7180 target
10 - Krishna Manikandan <mkrishn@codeaurora.org>
13 Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
15 bindings of MDSS and DPU are mentioned for SC7180 target.
20 - const: qcom,sc7180-mdss
33 - description: Display AHB clock from gcc
34 - description: Display AHB clock from dispcc
35 - description: Display core clock
46 interrupt-controller: true
48 "#address-cells": true
57 - description: Phandle to apps_smmu node with SID mask for Hard-Fail port0
63 - description: Interconnect path specifying the port ids for data bus
69 "^display-controller@[0-9a-f]+$":
71 description: Node containing the properties of DPU.
76 - const: qcom,sc7180-dpu
80 - description: Address offset and size for mdp register set
81 - description: Address offset and size for vbif register set
90 - description: Display hf axi clock
91 - description: Display ahb clock
92 - description: Display rotator clock
93 - description: Display lut clock
94 - description: Display core clock
95 - description: Display vsync clock
112 operating-points-v2: true
115 $ref: /schemas/graph.yaml#/properties/ports
117 Contains the list of output ports from DPU device. These ports
118 connect to interfaces that are external to the DPU hardware,
119 such as DSI, DP etc. Each output port contains an endpoint that
120 describes how it is connected to an external interface.
124 $ref: /schemas/graph.yaml#/properties/port
125 description: DPU_INTF1 (DSI1)
128 $ref: /schemas/graph.yaml#/properties/port
129 description: DPU_INTF0 (DP)
141 - operating-points-v2
151 - interrupt-controller
155 additionalProperties: false
159 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
160 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
161 #include <dt-bindings/interrupt-controller/arm-gic.h>
162 #include <dt-bindings/interconnect/qcom,sdm845.h>
163 #include <dt-bindings/power/qcom-rpmpd.h>
165 display-subsystem@ae00000 {
166 #address-cells = <1>;
168 compatible = "qcom,sc7180-mdss";
169 reg = <0xae00000 0x1000>;
171 power-domains = <&dispcc MDSS_GDSC>;
172 clocks = <&gcc GCC_DISP_AHB_CLK>,
173 <&dispcc DISP_CC_MDSS_AHB_CLK>,
174 <&dispcc DISP_CC_MDSS_MDP_CLK>;
175 clock-names = "iface", "ahb", "core";
177 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
178 interrupt-controller;
179 #interrupt-cells = <1>;
181 interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
182 interconnect-names = "mdp0-mem";
184 iommus = <&apps_smmu 0x800 0x2>;
187 display-controller@ae01000 {
188 compatible = "qcom,sc7180-dpu";
189 reg = <0x0ae01000 0x8f000>,
192 reg-names = "mdp", "vbif";
194 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
195 <&dispcc DISP_CC_MDSS_AHB_CLK>,
196 <&dispcc DISP_CC_MDSS_ROT_CLK>,
197 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
198 <&dispcc DISP_CC_MDSS_MDP_CLK>,
199 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
200 clock-names = "bus", "iface", "rot", "lut", "core",
203 interrupt-parent = <&mdss>;
205 power-domains = <&rpmhpd SC7180_CX>;
206 operating-points-v2 = <&mdp_opp_table>;
209 #address-cells = <1>;
214 dpu_intf1_out: endpoint {
215 remote-endpoint = <&dsi0_in>;
221 dpu_intf0_out: endpoint {
222 remote-endpoint = <&dp_in>;