4 The Mediatek HDMI encoder can generate HDMI 1.4a or MHL 2.0 signals from
8 - compatible: Should be "mediatek,<chip>-hdmi".
9 - the supported chips are mt2701, mt7623 and mt8173
10 - reg: Physical base address and length of the controller's registers
11 - interrupts: The interrupt signal from the function block.
12 - clocks: device clocks
13 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
14 - clock-names: must contain "pixel", "pll", "bclk", and "spdif".
15 - phys: phandle link to the HDMI PHY node.
16 See Documentation/devicetree/bindings/phy/phy-bindings.txt for details.
17 - phy-names: must contain "hdmi"
18 - mediatek,syscon-hdmi: phandle link and register offset to the system
19 configuration registers. For mt8173 this must be offset 0x900 into the
20 MMSYS_CONFIG region: <&mmsys 0x900>.
21 - ports: A node containing input and output port nodes with endpoint
22 definitions as documented in Documentation/devicetree/bindings/graph.txt.
23 - port@0: The input port in the ports node should be connected to a DPI output
25 - port@1: The output port in the ports node should be connected to the input
26 port of a connector node that contains a ddc-i2c-bus property, or to the
27 input port of an attached bridge chip, such as a SlimPort transmitter.
32 The HDMI CEC controller handles hotplug detection and CEC communication.
35 - compatible: Should be "mediatek,<chip>-cec"
36 - the supported chips are mt7623 and mt8173
37 - reg: Physical base address and length of the controller's registers
38 - interrupts: The interrupt signal from the function block.
39 - clocks: device clock
44 The HDMI DDC i2c controller is used to interface with the HDMI DDC pins.
45 The Mediatek's I2C controller is used to interface with I2C devices.
48 - compatible: Should be "mediatek,<chip>-hdmi-ddc"
49 - the supported chips are mt7623 and mt8173
50 - reg: Physical base address and length of the controller's registers
51 - clocks: device clock
52 - clock-names: Should be "ddc-i2c".
56 See phy/mediatek,hdmi-phy.yaml
61 compatible = "mediatek,mt8173-cec";
62 reg = <0 0x10013000 0 0xbc>;
63 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
64 clocks = <&infracfg CLK_INFRA_CEC>;
67 hdmi_phy: hdmi-phy@10209100 {
68 compatible = "mediatek,mt8173-hdmi-phy";
69 reg = <0 0x10209100 0 0x24>;
70 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
71 clock-names = "pll_ref";
72 clock-output-names = "hdmitx_dig_cts";
73 mediatek,ibias = <0xa>;
74 mediatek,ibias_up = <0x1c>;
79 hdmi_ddc0: i2c@11012000 {
80 compatible = "mediatek,mt8173-hdmi-ddc";
81 reg = <0 0x11012000 0 0x1c>;
82 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>;
83 clocks = <&pericfg CLK_PERI_I2C5>;
84 clock-names = "ddc-i2c";
87 hdmi0: hdmi@14025000 {
88 compatible = "mediatek,mt8173-hdmi";
89 reg = <0 0x14025000 0 0x400>;
90 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
91 clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
92 <&mmsys CLK_MM_HDMI_PLLCK>,
93 <&mmsys CLK_MM_HDMI_AUDIO>,
94 <&mmsys CLK_MM_HDMI_SPDIF>;
95 clock-names = "pixel", "pll", "bclk", "spdif";
96 pinctrl-names = "default";
97 pinctrl-0 = <&hdmi_pin>;
100 mediatek,syscon-hdmi = <&mmsys 0x900>;
101 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>;
102 assigned-clock-parents = <&hdmi_phy>;
105 #address-cells = <1>;
112 remote-endpoint = <&dpi0_out>;
119 hdmi0_out: endpoint {
120 remote-endpoint = <&hdmi_con_in>;
127 compatible = "hdmi-connector";
129 ddc-i2c-bus = <&hdmiddc0>;
132 hdmi_con_in: endpoint {
133 remote-endpoint = <&hdmi0_out>;