4 The Mediatek DPI function block is a sink of the display subsystem and
5 provides 8-bit RGB/YUV444 or 8/10/10-bit YUV422 pixel data on a parallel
9 - compatible: "mediatek,<chip>-dpi"
10 the supported chips are mt2701 , mt8173 and mt8183.
11 - reg: Physical base address and length of the controller's registers
12 - interrupts: The interrupt signal from the function block.
13 - clocks: device clocks
14 See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15 - clock-names: must contain "pixel", "engine", and "pll"
16 - port: Output port node with endpoint definitions as described in
17 Documentation/devicetree/bindings/graph.txt. This port should be connected
18 to the input port of an attached HDMI or LVDS encoder chip.
21 - pinctrl-names: Contain "default" and "sleep".
26 compatible = "mediatek,mt8173-dpi";
27 reg = <0 0x1401d000 0 0x1000>;
28 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
29 clocks = <&mmsys CLK_MM_DPI_PIXEL>,
30 <&mmsys CLK_MM_DPI_ENGINE>,
31 <&apmixedsys CLK_APMIXED_TVDPLL>;
32 clock-names = "pixel", "engine", "pll";
33 pinctrl-names = "default", "sleep";
34 pinctrl-0 = <&dpi_pin_func>;
35 pinctrl-1 = <&dpi_pin_idle>;
39 remote-endpoint = <&hdmi0_in>;