1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/display/bridge/synopsys,dw-hdmi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Synopsys DesignWare HDMI TX Controller
10 - Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
13 This document defines device tree properties for the Synopsys DesignWare HDMI
14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
15 binding specification by itself but is meant to be referenced by device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
18 When referenced from platform device tree bindings the properties defined in
19 this document are defined as follows. The platform device tree bindings are
20 responsible for defining whether each property is required or optional.
28 Width (in bytes) of the registers specified by the reg property.
29 $ref: /schemas/types.yaml#/definitions/uint32
37 - description: The bus clock for either AHB and APB
38 - description: The internal register configuration clock
52 additionalProperties: true