1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
24 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
25 The AUX and PMA registers are not part of this range, they are instead
26 included in the associated PHY.
28 Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
30 Register block of mhdptx sapb registers.
43 DP bridge clock, used by the IP to know how to translate a number of
44 clock cycles into a time (which is used to comply with DP standard timings
50 phandle to the DisplayPort PHY.
63 $ref: /schemas/graph.yaml#/properties/ports
67 $ref: /schemas/graph.yaml#/properties/port
69 First input port representing the DP bridge input.
72 $ref: /schemas/graph.yaml#/properties/port
74 Second input port representing the DP bridge input.
77 $ref: /schemas/graph.yaml#/properties/port
79 Third input port representing the DP bridge input.
82 $ref: /schemas/graph.yaml#/properties/port
84 Fourth input port representing the DP bridge input.
87 $ref: /schemas/graph.yaml#/properties/port
89 Output port representing the DP bridge output.
100 const: ti,j721e-mhdp8546
128 additionalProperties: false
132 #include <dt-bindings/interrupt-controller/arm-gic.h>
134 #address-cells = <2>;
137 mhdp: dp-bridge@f0fb000000 {
138 compatible = "cdns,mhdp8546";
139 reg = <0xf0 0xfb000000 0x0 0x1000000>;
140 reg-names = "mhdptx";
141 clocks = <&mhdp_clock>;
144 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
147 #address-cells = <1>;
152 dp_bridge_input: endpoint {
153 remote-endpoint = <&xxx_dpi_output>;
159 dp_bridge_output: endpoint {
160 remote-endpoint = <&xxx_dp_connector_input>;