1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Cadence MHDP8546 bridge
10 - Swapnil Jakhade <sjakhade@cadence.com>
11 - Yuti Amonkar <yamonkar@cadence.com>
23 Register block of mhdptx apb registers up to PHY mapped area (AUX_CONFIG_P).
24 The AUX and PMA registers are not part of this range, they are instead
25 included in the associated PHY.
27 Register block for DSS_EDP0_INTG_CFG_VP registers in case of TI J7 SoCs.
29 Register block of mhdptx sapb registers.
41 DP bridge clock, used by the IP to know how to translate a number of
42 clock cycles into a time (which is used to comply with DP standard timings
48 phandle to the DisplayPort PHY.
61 $ref: /schemas/graph.yaml#/properties/ports
65 $ref: /schemas/graph.yaml#/properties/port
67 First input port representing the DP bridge input.
70 $ref: /schemas/graph.yaml#/properties/port
72 Second input port representing the DP bridge input.
75 $ref: /schemas/graph.yaml#/properties/port
77 Third input port representing the DP bridge input.
80 $ref: /schemas/graph.yaml#/properties/port
82 Fourth input port representing the DP bridge input.
85 $ref: /schemas/graph.yaml#/properties/port
87 Output port representing the DP bridge output.
98 const: ti,j721e-mhdp8546
126 additionalProperties: false
130 #include <dt-bindings/interrupt-controller/arm-gic.h>
132 #address-cells = <2>;
135 mhdp: dp-bridge@f0fb000000 {
136 compatible = "cdns,mhdp8546";
137 reg = <0xf0 0xfb000000 0x0 0x1000000>;
138 reg-names = "mhdptx";
139 clocks = <&mhdp_clock>;
142 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
145 #address-cells = <1>;
150 dp_bridge_input: endpoint {
151 remote-endpoint = <&xxx_dpi_output>;
157 dp_bridge_output: endpoint {
158 remote-endpoint = <&xxx_dp_connector_input>;