Documentation/devicetree/bindings/clock/st/st,quadfs.txt

   1 Binding for a type of quad channel digital frequency synthesizer found on
   2 certain STMicroelectronics consumer electronics SoC devices.
   3
   4 This version contains a programmable PLL which can generate up to 216, 432
   5 or 660MHz (from a 30MHz oscillator input) as the input to the digital
   6 synthesizers.
   7
   8 This binding uses the common clock binding[1].
   9
  10 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
  11
  12 Required properties:
  13 - compatible : shall be:
  14   "st,quadfs"
  15   "st,quadfs-d0"
  16   "st,quadfs-d2"
  17   "st,quadfs-d3"
  18   "st,quadfs-pll"
  19
  20
  21 - #clock-cells : from common clock binding; shall be set to 1.
  22
  23 - reg : A Base address and length of the register set.
  24
  25 - clocks : from common clock binding
  26
  27 - clock-output-names : From common clock binding. The block has 4
  28                        clock outputs but not all of them in a specific instance
  29                        have to be used in the SoC. If a clock name is left as
  30                        an empty string then no clock will be created for the
  31                        output associated with that string index. If fewer than
  32                        4 strings are provided then no clocks will be created
  33                        for the remaining outputs.
  34
  35 Example:
  36
  37         clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
  38                 #clock-cells = <1>;
  39                 compatible = "st,quadfs-pll";
  40                 reg = <0x9103000 0x1000>;
  41
  42                 clocks = <&clk_sysin>;
  43
  44                 clock-output-names = "clk-s-c0-fs0-ch0",
  45                                      "clk-s-c0-fs0-ch1",
  46                                      "clk-s-c0-fs0-ch2",
  47                                      "clk-s-c0-fs0-ch3";
  48         };