1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Graphics Clock & Reset Controller Binding
10 - Taniya Das <tdas@codeaurora.org>
13 Qualcomm graphics clock control module which supports the clocks, resets and
14 power domains on Qualcomm SoCs.
17 dt-bindings/clock/qcom,gpucc-sdm845.h
18 dt-bindings/clock/qcom,gpucc-sc7180.h
19 dt-bindings/clock/qcom,gpucc-sc7280.h
20 dt-bindings/clock/qcom,gpucc-sm8150.h
21 dt-bindings/clock/qcom,gpucc-sm8250.h
34 - description: Board XO source
35 - description: GPLL0 main branch source
36 - description: GPLL0 div branch source
41 - const: gcc_gpu_gpll0_clk_src
42 - const: gcc_gpu_gpll0_div_clk_src
50 '#power-domain-cells':
63 - '#power-domain-cells'
65 additionalProperties: false
69 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
70 #include <dt-bindings/clock/qcom,rpmh.h>
71 clock-controller@5090000 {
72 compatible = "qcom,sdm845-gpucc";
73 reg = <0x05090000 0x9000>;
74 clocks = <&rpmhcc RPMH_CXO_CLK>,
75 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
76 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
77 clock-names = "bi_tcxo",
78 "gcc_gpu_gpll0_clk_src",
79 "gcc_gpu_gpll0_div_clk_src";
82 #power-domain-cells = <1>;