1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/clock/cirrus,cs2000-cp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding CIRRUS LOGIC Fractional-N Clock Synthesizer & Clock Multiplier
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
13 The CS2000-CP is an extremely versatile system clocking device that
14 utilizes a programmable phase lock loop.
16 Link: https://www.cirrus.com/products/cs2000/
25 Common clock binding for CLK_IN, XTI/REF_CLK
40 cirrus,aux-output-source:
42 Specifies the function of the auxiliary clock output pin
43 $ref: /schemas/types.yaml#/definitions/uint32
45 - 0 # CS2000CP_AUX_OUTPUT_REF_CLK: ref_clk input
46 - 1 # CS2000CP_AUX_OUTPUT_CLK_IN: clk_in input
47 - 2 # CS2000CP_AUX_OUTPUT_CLK_OUT: clk_out output
48 - 3 # CS2000CP_AUX_OUTPUT_PLL_LOCK: pll lock status
53 This mode allows the PLL to maintain lock even when CLK_IN
54 has missing pulses for up to 20 ms.
55 $ref: /schemas/types.yaml#/definitions/flag
59 In dynamic mode, the CLK_IN input is used to drive the
60 digital PLL of the silicon.
61 If not given, the static mode shall be used to derive the
62 output signal directly from the REF_CLK input.
63 $ref: /schemas/types.yaml#/definitions/flag
72 additionalProperties: false
76 #include <dt-bindings/clock/cirrus,cs2000-cp.h>
85 compatible = "cirrus,cs2000-cp";
87 clocks = <&rcar_sound 0>, <&x12_clk>;
88 clock-names = "clk_in", "ref_clk";
89 cirrus,aux-output-source = <CS2000CP_AUX_OUTPUT_CLK_OUT>;