Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt

   1 Mediatek infracfg controller
   2 ============================
   3
   4 The Mediatek infracfg controller provides various clocks and reset
   5 outputs to the system.
   6
   7 Required Properties:
   8
   9 - compatible: Should be one of:
  10         - "mediatek,mt2701-infracfg", "syscon"
  11         - "mediatek,mt2712-infracfg", "syscon"
  12         - "mediatek,mt6765-infracfg", "syscon"
  13         - "mediatek,mt6779-infracfg_ao", "syscon"
  14         - "mediatek,mt6797-infracfg", "syscon"
  15         - "mediatek,mt7622-infracfg", "syscon"
  16         - "mediatek,mt7623-infracfg", "mediatek,mt2701-infracfg", "syscon"
  17         - "mediatek,mt7629-infracfg", "syscon"
  18         - "mediatek,mt8135-infracfg", "syscon"
  19         - "mediatek,mt8167-infracfg", "syscon"
  20         - "mediatek,mt8173-infracfg", "syscon"
  21         - "mediatek,mt8183-infracfg", "syscon"
  22         - "mediatek,mt8516-infracfg", "syscon"
  23 - #clock-cells: Must be 1
  24 - #reset-cells: Must be 1
  25
  26 The infracfg controller uses the common clk binding from
  27 Documentation/devicetree/bindings/clock/clock-bindings.txt
  28 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  29 Also it uses the common reset controller binding from
  30 Documentation/devicetree/bindings/reset/reset.txt.
  31 The available reset outputs are defined in
  32 dt-bindings/reset/mt*-resets.h
  33
  34 Example:
  35
  36 infracfg: power-controller@10001000 {
  37         compatible = "mediatek,mt8173-infracfg", "syscon";
  38         reg = <0 0x10001000 0 0x1000>;
  39         #clock-cells = <1>;
  40         #reset-cells = <1>;
  41 };