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drm/i915/xehpsdv: add initial XeHP SDV definitions
2021-07-22 Lucas De Marchidrm/i915/xehpsdv: add initial XeHP SDV definitions
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-22 Lucas De Marchidrm/i915: Add XE_HP initial definitions
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-22 Lucas De Marchidrm/i915: Add release id version
 "minor" (Matt Roper and Tvrtko)
...formatted as {ver}.{rel:2} (Jani and Matt Roper)
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-22 Lucas De Marchidrm/i915: do not abbreviate version in debugfs
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/icl: Drop workarounds that only apply to pre...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/cnl: Drop all workarounds
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/dg1: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/rkl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/jsl_ehl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/icl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/glk: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/bxt: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/kbl: Drop pre-production revision from stepping...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915/skl: Use revid->stepping tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Matt Roperdrm/i915: Make pre-production detection use direct...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-07-15 Anusha Srivatsadrm/i915/step: s/<platform>_revid_tbl/<platform>_revids
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2021-05-27 Aditya Swarupdrm/i915: Add Wa_14010733141
Cc: Matt Roper <matthew.d.roper@intel.com>
Co-developed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-26 Gwan-gyeong Mundrm/i915/display: Remove a redundant function argument...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-26 Manasi Navaredrm/i915/xelpd: Add VRR guardband for VRR CTL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-26 Matt Roperdrm/i915/xelpd: Enhanced pipe underrun reporting
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/display/adl_p: Implement Wa_22011320316
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/adl_p: Implement Wa_22011091694
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/adl_p: Add IPs stepping mapping
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Animesh Mannadrm/i915/bigjoiner: atomic commit changes for uncompressed...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Animesh Mannadrm/i915/bigjoiner: Avoid dsc_compute_config for uncompresse...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Animesh Mannadrm/i915/bigjoiner: Mode validation with uncompressed...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Mika Kaholadrm/i915/adl_p: Enable/disable loadgen sharing
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Ville Syrjälädrm/i915: Move intel_modeset_all_pipes()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/adl_p: Enable modular fia
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/display/tc: Rename safe_mode functions ownership
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Anusha Srivatsadrm/i915/adl_p: Add cdclk support for ADL-P
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Matt Roperdrm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 José Roberto de... drm/i915/xelpd: Provide port/phy mapping for vbt
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Vandita Kulkarnidrm/i915: Get slice height before computing rc params
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Vandita Kulkarnidrm/i915/xelpd: Support DP1.4 compression BPPs
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Vandita Kulkarnidrm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Matt Roperdrm/i915/xelpd: Increase maximum watermark lines to 255
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-15 Matt Roperdrm/i915/xelpd: Handle new location of outputs D and E
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Umesh Nerlige Ramappadrm/i915/perf: Enable OA formats for ADL_P
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Clinton Taylordrm/i915/adl_p: Add PCH support
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Matt Roperdrm/i915/xelpd: Add Wa_14011503030
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Matt Roperdrm/i915/xelpd: Required bandwidth increases when VT...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Matt Roperdrm/i915/xelpd: Add XE_LPD power wells
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Matt Roperdrm/i915/xelpd: Define plane capabilities
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-12 Matt Roperdrm/i915/xelpd: Handle proper AUX interrupt bits
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-04-07 Matt Roperdrm/i915/display: Eliminate IS_GEN9_{BC,LP}
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-03-23 Matt Roperdrm/i915/display: Simplify GLK display version tests
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-03-23 Matt Roperdrm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriat...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-03-23 Matt Roperdrm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriat...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-03-23 Matt Roperdrm/i915/display: Eliminate most usage of INTEL_GEN()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-03-23 Matt Roperdrm/i915: Add DISPLAY_VER() and related macros
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-03-23 Matt Roperdrm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-02-13 Matt Roperdrm/i915: Try to detect sudden loss of MMIO access
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-02-13 Matt Roperdrm/i915: FPGA_DBG is display-specific
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-01-12 Matt Roperdrm/i915/dg1: Update voltage swing tables for DP
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-01-06 Matt Roperdrm/i915/rkl: Add DP vswing programming tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-11-17 Bob Paauwedrm/i915: Tweaked Wa_14010685332 for PCHs used on gen11...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-10-16 Matt Roperdrm/i915/rkl: Add new cdclk table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-10-10 Matt Roperdrm/i915: Update gen12 multicast register ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-10-10 Matt Roperdrm/i915: Update gen12 forcewake table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-10-10 Matt Roperdrm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-26 Matt Roperdrm/i915: Extend Wa_14010685332 to all ICP+ PCH's
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-09 Aditya Swarupdrm/i915/rkl: Don't try to read out DSI transcoders
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-09 Matt Roperdrm/i915/rkl: Update TGP's pin mapping when paired...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-09 Matt Roperdrm/i915/rkl: RKL uses ABOX0 for pixel transfers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 José Roberto de... drm/i915/rkl: Disable PSR2
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 Matt Roperdrm/i915/rkl: Don't try to access transcoder D
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 Matt Roperdrm/i915/rkl: Setup ports/phys
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 Matt Roperdrm/i915/rkl: Handle comp master/slave relationships...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 Matt Roperdrm/i915/rkl: Add DDC pin mapping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 Lucas De Marchidrm/i915/rkl: provide port/phy mapping for vbt
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-06-04 Matt Roperdrm/i915/rkl: Set transcoder mask properly
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-05-05 Matt Roperdrm/i915/icp: Add Wa_14010685332
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-27 Matt Roperdrm/i915: Use proper fault mask in interrupt postinstall too
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-21 Matt Roperdrm/i915: Use single set of AUX powerwell ops for gen11+
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-17 Matt Roperdrm/i915/tgl: TBT AUX should use TC power well ops
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-15 Matt Roperdrm/i915/tgl: Initialize multicast register steering...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-15 Matt Roperdrm/i915/tgl: Extend Wa_1409767108:tgl to B0 stepping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-15 Matt Roperdrm/i915/tgl: Add Wa_14010477008:tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-15 Matt Atwooddrm/i915/ehl: extended Wa_2006604312 to ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-02 Swathi Dhanavanthridrm/i915/tgl: Make Wa_14010229206 permanent
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-19 Swathi Dhanavanthridrm/i915/tgl: Add new PCI IDs to TGL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Apply Wa_1406680159:icl,ehl as an engine...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Add Wa_1406306137:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Add Wa_1604278689:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Add Wa_1209644611:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Handle all MCR ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-09 Matt Roperdrm/i915/tgl: Don't treat unslice registers as masked
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-04 Matt Roperdrm/i915/ehl: Check PHY type before reading DPLL frequency
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-26 Matt Atwooddrm/i915/tgl: Add Wa_1606054188:tgl
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-26 Matt Roperdrm/i915/tgl: Allow DC5/DC6 entry while PG2 is active
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-21 Matt Roperdrm/i915/tgl: Add Wa_22010178259:tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-20 Matt Roperdrm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-20 Matt Roperdrm/i915: Program MBUS with rmw during initialization
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-18 Rafael Antognollidrm/i915/tgl: Add Wa_1808121037 to tgl.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-10 Matt Roperdrm/i915/tgl: Update cdclk voltage level settings
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-10 Matt Roperdrm/i915/ehl: Update port clock voltage level requirements
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-16 Matt Atwooddrm/i915: add Wa_14010594013: icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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