Merge tag 'defconfig-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_pll.c

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
index 1f2305b..4eaec44 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c
@@ -80,12 +80,17 @@ static void amdgpu_pll_reduce_ratio(unsigned *nom, unsigned *den,
  * Calculate feedback and reference divider for a given post divider. Makes
  * sure we stay within the limits.
  */
-static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_div,
-                                     unsigned fb_div_max, unsigned ref_div_max,
-                                     unsigned *fb_div, unsigned *ref_div)
+static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int nom,
+                                     unsigned int den, unsigned int post_div,
+                                     unsigned int fb_div_max, unsigned int ref_div_max,
+                                     unsigned int *fb_div, unsigned int *ref_div)
 {
+
        /* limit reference * post divider to a maximum */
-       ref_div_max = min(128 / post_div, ref_div_max);
+       if (adev->family == AMDGPU_FAMILY_SI)
+               ref_div_max = min(100 / post_div, ref_div_max);
+       else
+               ref_div_max = min(128 / post_div, ref_div_max);
 
        /* get matching reference and feedback divider */
        *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max);
@@ -102,16 +107,18 @@ static void amdgpu_pll_get_fb_ref_div(unsigned nom, unsigned den, unsigned post_
  * amdgpu_pll_compute - compute PLL paramaters
  *
  * @pll: information about the PLL
+ * @freq: requested frequency
  * @dot_clock_p: resulting pixel clock
- * fb_div_p: resulting feedback divider
- * frac_fb_div_p: fractional part of the feedback divider
- * ref_div_p: resulting reference divider
- * post_div_p: resulting reference divider
+ * @fb_div_p: resulting feedback divider
+ * @frac_fb_div_p: fractional part of the feedback divider
+ * @ref_div_p: resulting reference divider
+ * @post_div_p: resulting reference divider
  *
  * Try to calculate the PLL parameters to generate the given frequency:
  * dot_clock = (ref_freq * feedback_div) / (ref_div * post_div)
  */
-void amdgpu_pll_compute(struct amdgpu_pll *pll,
+void amdgpu_pll_compute(struct amdgpu_device *adev,
+                       struct amdgpu_pll *pll,
                        u32 freq,
                        u32 *dot_clock_p,
                        u32 *fb_div_p,
@@ -198,7 +205,7 @@ void amdgpu_pll_compute(struct amdgpu_pll *pll,
 
        for (post_div = post_div_min; post_div <= post_div_max; ++post_div) {
                unsigned diff;
-               amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max,
+               amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max,
                                          ref_div_max, &fb_div, &ref_div);
                diff = abs(target_clock - (pll->reference_freq * fb_div) /
                        (ref_div * post_div));
@@ -213,7 +220,7 @@ void amdgpu_pll_compute(struct amdgpu_pll *pll,
        post_div = post_div_best;
 
        /* get the feedback and reference divider for the optimal value */
-       amdgpu_pll_get_fb_ref_div(nom, den, post_div, fb_div_max, ref_div_max,
+       amdgpu_pll_get_fb_ref_div(adev, nom, den, post_div, fb_div_max, ref_div_max,
                                  &fb_div, &ref_div);
 
        /* reduce the numbers to a simpler ratio once more */
@@ -308,7 +315,6 @@ int amdgpu_pll_get_shared_dp_ppll(struct drm_crtc *crtc)
  * amdgpu_pll_get_shared_nondp_ppll - return the PPLL used by another non-DP crtc
  *
  * @crtc: drm crtc
- * @encoder: drm encoder
  *
  * Returns the PPLL (Pixel PLL) used by another non-DP crtc/encoder which can
  * be shared (i.e., same clock).