drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.c
[linux-2.6-microblaze.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_discovery.c
index a9b5480..0c359ad 100644 (file)
@@ -1046,7 +1046,7 @@ static void amdgpu_discovery_sysfs_fini(struct amdgpu_device *adev)
 
 /* ================================================== */
 
-int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
+static int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
        struct ip_discovery_header *ihdr;
@@ -1212,7 +1212,7 @@ int amdgpu_discovery_get_ip_version(struct amdgpu_device *adev, int hw_id, int n
        return -EINVAL;
 }
 
-void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
+static void amdgpu_discovery_harvest_ip(struct amdgpu_device *adev)
 {
        int vcn_harvest_count = 0;
        int umc_harvest_count = 0;
@@ -1257,7 +1257,7 @@ union gc_info {
        struct gc_info_v2_0 v2;
 };
 
-int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
+static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
 {
        struct binary_header *bhdr;
        union gc_info *gc_info;
@@ -1271,10 +1271,8 @@ int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev)
        bhdr = (struct binary_header *)adev->mman.discovery_bin;
        offset = le16_to_cpu(bhdr->table_list[GC].offset);
 
-       if (!offset) {
-               dev_err(adev->dev, "invalid GC table offset\n");
-               return -EINVAL;
-       }
+       if (!offset)
+               return 0;
 
        gc_info = (union gc_info *)(adev->mman.discovery_bin + offset);
 
@@ -1363,10 +1361,8 @@ int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
        bhdr = (struct binary_header *)adev->mman.discovery_bin;
        offset = le16_to_cpu(bhdr->table_list[MALL_INFO].offset);
 
-       if (!offset) {
-               dev_err(adev->dev, "invalid mall table offset\n");
-               return -EINVAL;
-       }
+       if (!offset)
+               return 0;
 
        mall_info = (union mall_info *)(adev->mman.discovery_bin + offset);
 
@@ -1396,6 +1392,52 @@ int amdgpu_discovery_get_mall_info(struct amdgpu_device *adev)
        return 0;
 }
 
+union vcn_info {
+       struct vcn_info_v1_0 v1;
+};
+
+static int amdgpu_discovery_get_vcn_info(struct amdgpu_device *adev)
+{
+       struct binary_header *bhdr;
+       union vcn_info *vcn_info;
+       u16 offset;
+       int v;
+
+       if (!adev->mman.discovery_bin) {
+               DRM_ERROR("ip discovery uninitialized\n");
+               return -EINVAL;
+       }
+
+       if (adev->vcn.num_vcn_inst > VCN_INFO_TABLE_MAX_NUM_INSTANCES) {
+               dev_err(adev->dev, "invalid vcn instances\n");
+               return -EINVAL;
+       }
+
+       bhdr = (struct binary_header *)adev->mman.discovery_bin;
+       offset = le16_to_cpu(bhdr->table_list[VCN_INFO].offset);
+
+       if (!offset)
+               return 0;
+
+       vcn_info = (union vcn_info *)(adev->mman.discovery_bin + offset);
+
+       switch (le16_to_cpu(vcn_info->v1.header.version_major)) {
+       case 1:
+               for (v = 0; v < adev->vcn.num_vcn_inst; v++) {
+                       adev->vcn.vcn_codec_disable_mask[v] =
+                               le32_to_cpu(vcn_info->v1.instance_info[v].fuse_data.all_bits);
+               }
+               break;
+       default:
+               dev_err(adev->dev,
+                       "Unhandled VCN info table %d.%d\n",
+                       le16_to_cpu(vcn_info->v1.header.version_major),
+                       le16_to_cpu(vcn_info->v1.header.version_minor));
+               return -EINVAL;
+       }
+       return 0;
+}
+
 static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
 {
        /* what IP to use for this? */
@@ -1989,6 +2031,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
                        return -EINVAL;
 
                amdgpu_discovery_harvest_ip(adev);
+               amdgpu_discovery_get_gfx_info(adev);
+               amdgpu_discovery_get_mall_info(adev);
+               amdgpu_discovery_get_vcn_info(adev);
                break;
        }