1 // SPDX-License-Identifier: GPL-2.0
3 * Thunderbolt link controller support
5 * Copyright (C) 2019, Intel Corporation
6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
12 * tb_lc_read_uuid() - Read switch UUID from link controller common register
13 * @sw: Switch whose UUID is read
14 * @uuid: UUID is placed here
16 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid)
20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4);
23 static int read_lc_desc(struct tb_switch *sw, u32 *desc)
27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1);
30 static int find_port_lc_cap(struct tb_port *port)
32 struct tb_switch *sw = port->sw;
33 int start, phys, ret, size;
36 ret = read_lc_desc(sw, &desc);
40 /* Start of port LC registers */
41 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
42 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
43 phys = tb_phy_port_from_link(port->port);
45 return sw->cap_lc + start + phys * size;
48 static int tb_lc_set_port_configured(struct tb_port *port, bool configured)
50 bool upstream = tb_is_upstream_port(port);
51 struct tb_switch *sw = port->sw;
55 if (sw->generation < 2)
58 cap = find_port_lc_cap(port);
62 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
66 /* Resolve correct lane */
68 lane = TB_LC_SX_CTRL_L1C;
70 lane = TB_LC_SX_CTRL_L2C;
75 ctrl |= TB_LC_SX_CTRL_UPSTREAM;
79 ctrl &= ~TB_LC_SX_CTRL_UPSTREAM;
82 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
86 * tb_lc_configure_port() - Let LC know about configured port
87 * @port: Port that is set as configured
89 * Sets the port configured for power management purposes.
91 int tb_lc_configure_port(struct tb_port *port)
93 return tb_lc_set_port_configured(port, true);
97 * tb_lc_unconfigure_port() - Let LC know about unconfigured port
98 * @port: Port that is set as configured
100 * Sets the port unconfigured for power management purposes.
102 void tb_lc_unconfigure_port(struct tb_port *port)
104 tb_lc_set_port_configured(port, false);
107 static int tb_lc_set_xdomain_configured(struct tb_port *port, bool configure)
109 struct tb_switch *sw = port->sw;
113 if (sw->generation < 2)
116 cap = find_port_lc_cap(port);
120 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
124 /* Resolve correct lane */
126 lane = TB_LC_SX_CTRL_L1D;
128 lane = TB_LC_SX_CTRL_L2D;
135 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
139 * tb_lc_configure_xdomain() - Inform LC that the link is XDomain
140 * @port: Switch downstream port connected to another host
142 * Sets the lane configured for XDomain accordingly so that the LC knows
143 * about this. Returns %0 in success and negative errno in failure.
145 int tb_lc_configure_xdomain(struct tb_port *port)
147 return tb_lc_set_xdomain_configured(port, true);
151 * tb_lc_unconfigure_xdomain() - Unconfigure XDomain from port
152 * @port: Switch downstream port that was connected to another host
154 * Unsets the lane XDomain configuration.
156 void tb_lc_unconfigure_xdomain(struct tb_port *port)
158 tb_lc_set_xdomain_configured(port, false);
162 * tb_lc_start_lane_initialization() - Start lane initialization
163 * @port: Device router lane 0 adapter
165 * Starts lane initialization for @port after the router resumed from
166 * sleep. Should be called for those downstream lane adapters that were
167 * not connected (tb_lc_configure_port() was not called) before sleep.
169 * Returns %0 in success and negative errno in case of failure.
171 int tb_lc_start_lane_initialization(struct tb_port *port)
173 struct tb_switch *sw = port->sw;
180 if (sw->generation < 2)
183 cap = find_port_lc_cap(port);
187 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
191 ctrl |= TB_LC_SX_CTRL_SLI;
193 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1);
196 static int tb_lc_set_wake_one(struct tb_switch *sw, unsigned int offset,
203 * Enable wake on PCIe and USB4 (wake coming from another
206 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
207 offset + TB_LC_SX_CTRL, 1);
211 ctrl &= ~(TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD | TB_LC_SX_CTRL_WOP |
214 if (flags & TB_WAKE_ON_CONNECT)
215 ctrl |= TB_LC_SX_CTRL_WOC | TB_LC_SX_CTRL_WOD;
216 if (flags & TB_WAKE_ON_USB4)
217 ctrl |= TB_LC_SX_CTRL_WOU4;
218 if (flags & TB_WAKE_ON_PCIE)
219 ctrl |= TB_LC_SX_CTRL_WOP;
221 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, offset + TB_LC_SX_CTRL, 1);
225 * tb_lc_set_wake() - Enable/disable wake
226 * @sw: Switch whose wakes to configure
227 * @flags: Wakeup flags (%0 to disable)
229 * For each LC sets wake bits accordingly.
231 int tb_lc_set_wake(struct tb_switch *sw, unsigned int flags)
233 int start, size, nlc, ret, i;
236 if (sw->generation < 2)
242 ret = read_lc_desc(sw, &desc);
246 /* Figure out number of link controllers */
247 nlc = desc & TB_LC_DESC_NLC_MASK;
248 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
249 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
251 /* For each link controller set sleep bit */
252 for (i = 0; i < nlc; i++) {
253 unsigned int offset = sw->cap_lc + start + i * size;
255 ret = tb_lc_set_wake_one(sw, offset, flags);
264 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep
265 * @sw: Switch to set sleep
267 * Let the switch link controllers know that the switch is going to
270 int tb_lc_set_sleep(struct tb_switch *sw)
272 int start, size, nlc, ret, i;
275 if (sw->generation < 2)
278 ret = read_lc_desc(sw, &desc);
282 /* Figure out number of link controllers */
283 nlc = desc & TB_LC_DESC_NLC_MASK;
284 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT;
285 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT;
287 /* For each link controller set sleep bit */
288 for (i = 0; i < nlc; i++) {
289 unsigned int offset = sw->cap_lc + start + i * size;
292 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH,
293 offset + TB_LC_SX_CTRL, 1);
297 ctrl |= TB_LC_SX_CTRL_SLP;
298 ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH,
299 offset + TB_LC_SX_CTRL, 1);
308 * tb_lc_lane_bonding_possible() - Is lane bonding possible towards switch
309 * @sw: Switch to check
311 * Checks whether conditions for lane bonding from parent to @sw are
314 bool tb_lc_lane_bonding_possible(struct tb_switch *sw)
320 if (sw->generation < 2)
323 up = tb_upstream_port(sw);
324 cap = find_port_lc_cap(up);
328 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1);
332 return !!(val & TB_LC_PORT_ATTR_BE);
335 static int tb_lc_dp_sink_from_port(const struct tb_switch *sw,
338 struct tb_port *port;
340 /* The first DP IN port is sink 0 and second is sink 1 */
341 tb_switch_for_each_port(sw, port) {
342 if (tb_port_is_dpin(port))
349 static int tb_lc_dp_sink_available(struct tb_switch *sw, int sink)
354 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
355 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
360 * Sink is available for CM/SW to use if the allocation valie is
364 alloc = val & TB_LC_SNK_ALLOCATION_SNK0_MASK;
365 if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK0_CM)
368 alloc = (val & TB_LC_SNK_ALLOCATION_SNK1_MASK) >>
369 TB_LC_SNK_ALLOCATION_SNK1_SHIFT;
370 if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK1_CM)
378 * tb_lc_dp_sink_query() - Is DP sink available for DP IN port
379 * @sw: Switch whose DP sink is queried
380 * @in: DP IN port to check
382 * Queries through LC SNK_ALLOCATION registers whether DP sink is available
383 * for the given DP IN port or not.
385 bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in)
390 * For older generations sink is always available as there is no
391 * allocation mechanism.
393 if (sw->generation < 3)
396 sink = tb_lc_dp_sink_from_port(sw, in);
400 return !tb_lc_dp_sink_available(sw, sink);
404 * tb_lc_dp_sink_alloc() - Allocate DP sink
405 * @sw: Switch whose DP sink is allocated
406 * @in: DP IN port the DP sink is allocated for
408 * Allocate DP sink for @in via LC SNK_ALLOCATION registers. If the
409 * resource is available and allocation is successful returns %0. In all
410 * other cases returs negative errno. In particular %-EBUSY is returned if
411 * the resource was not available.
413 int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in)
418 if (sw->generation < 3)
421 sink = tb_lc_dp_sink_from_port(sw, in);
425 ret = tb_lc_dp_sink_available(sw, sink);
429 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
430 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
435 val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK;
436 val |= TB_LC_SNK_ALLOCATION_SNK0_CM;
438 val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK;
439 val |= TB_LC_SNK_ALLOCATION_SNK1_CM <<
440 TB_LC_SNK_ALLOCATION_SNK1_SHIFT;
443 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
444 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
449 tb_port_dbg(in, "sink %d allocated\n", sink);
454 * tb_lc_dp_sink_dealloc() - De-allocate DP sink
455 * @sw: Switch whose DP sink is de-allocated
456 * @in: DP IN port whose DP sink is de-allocated
458 * De-allocate DP sink from @in using LC SNK_ALLOCATION registers.
460 int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in)
465 if (sw->generation < 3)
468 sink = tb_lc_dp_sink_from_port(sw, in);
472 /* Needs to be owned by CM/SW */
473 ret = tb_lc_dp_sink_available(sw, sink);
477 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
478 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
483 val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK;
485 val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK;
487 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
488 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1);
492 tb_port_dbg(in, "sink %d de-allocated\n", sink);
497 * tb_lc_force_power() - Forces LC to be powered on
498 * @sw: Thunderbolt switch
500 * This is useful to let authentication cycle pass even without
501 * a Thunderbolt link present.
503 int tb_lc_force_power(struct tb_switch *sw)
507 return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1);