2 * PWM driver for Rockchip SoCs
4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
5 * Copyright (C) 2014 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
12 #include <linux/clk.h>
14 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pwm.h>
19 #include <linux/time.h>
21 #define PWM_CTRL_TIMER_EN (1 << 0)
22 #define PWM_CTRL_OUTPUT_EN (1 << 3)
24 #define PWM_ENABLE (1 << 0)
25 #define PWM_CONTINUOUS (1 << 1)
26 #define PWM_DUTY_POSITIVE (1 << 3)
27 #define PWM_DUTY_NEGATIVE (0 << 3)
28 #define PWM_INACTIVE_NEGATIVE (0 << 4)
29 #define PWM_INACTIVE_POSITIVE (1 << 4)
30 #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE)
31 #define PWM_OUTPUT_LEFT (0 << 5)
32 #define PWM_LOCK_EN (1 << 6)
33 #define PWM_LP_DISABLE (0 << 8)
35 struct rockchip_pwm_chip {
39 const struct rockchip_pwm_data *data;
43 struct rockchip_pwm_regs {
50 struct rockchip_pwm_data {
51 struct rockchip_pwm_regs regs;
52 unsigned int prescaler;
53 bool supports_polarity;
58 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c)
60 return container_of(c, struct rockchip_pwm_chip, chip);
63 static void rockchip_pwm_get_state(struct pwm_chip *chip,
64 struct pwm_device *pwm,
65 struct pwm_state *state)
67 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
68 u32 enable_conf = pc->data->enable_conf;
69 unsigned long clk_rate;
74 ret = clk_enable(pc->pclk);
78 clk_rate = clk_get_rate(pc->clk);
80 tmp = readl_relaxed(pc->base + pc->data->regs.period);
81 tmp *= pc->data->prescaler * NSEC_PER_SEC;
82 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
84 tmp = readl_relaxed(pc->base + pc->data->regs.duty);
85 tmp *= pc->data->prescaler * NSEC_PER_SEC;
86 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
88 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
89 if (pc->data->supports_polarity)
90 state->enabled = ((val & enable_conf) != enable_conf) ?
93 state->enabled = ((val & enable_conf) == enable_conf) ?
96 if (pc->data->supports_polarity) {
97 if (!(val & PWM_DUTY_POSITIVE))
98 state->polarity = PWM_POLARITY_INVERSED;
101 clk_disable(pc->pclk);
104 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
105 struct pwm_state *state)
107 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
108 unsigned long period, duty;
112 clk_rate = clk_get_rate(pc->clk);
115 * Since period and duty cycle registers have a width of 32
116 * bits, every possible input period can be obtained using the
117 * default prescaler value for all practical clock rate values.
119 div = clk_rate * state->period;
120 period = DIV_ROUND_CLOSEST_ULL(div,
121 pc->data->prescaler * NSEC_PER_SEC);
123 div = clk_rate * state->duty_cycle;
124 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC);
127 * Lock the period and duty of previous configuration, then
128 * change the duty and period, that would not be effective.
130 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl);
131 if (pc->data->supports_lock) {
133 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl);
136 writel(period, pc->base + pc->data->regs.period);
137 writel(duty, pc->base + pc->data->regs.duty);
139 if (pc->data->supports_polarity) {
140 ctrl &= ~PWM_POLARITY_MASK;
141 if (state->polarity == PWM_POLARITY_INVERSED)
142 ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE;
144 ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE;
148 * Unlock and set polarity at the same time,
149 * the configuration of duty, period and polarity
150 * would be effective together at next period.
152 if (pc->data->supports_lock)
153 ctrl &= ~PWM_LOCK_EN;
155 writel(ctrl, pc->base + pc->data->regs.ctrl);
158 static int rockchip_pwm_enable(struct pwm_chip *chip,
159 struct pwm_device *pwm,
162 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
163 u32 enable_conf = pc->data->enable_conf;
168 ret = clk_enable(pc->clk);
173 val = readl_relaxed(pc->base + pc->data->regs.ctrl);
180 writel_relaxed(val, pc->base + pc->data->regs.ctrl);
183 clk_disable(pc->clk);
188 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
189 struct pwm_state *state)
191 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip);
192 struct pwm_state curstate;
196 ret = clk_enable(pc->pclk);
200 pwm_get_state(pwm, &curstate);
201 enabled = curstate.enabled;
203 if (state->polarity != curstate.polarity && enabled &&
204 !pc->data->supports_lock) {
205 ret = rockchip_pwm_enable(chip, pwm, false);
211 rockchip_pwm_config(chip, pwm, state);
212 if (state->enabled != enabled) {
213 ret = rockchip_pwm_enable(chip, pwm, state->enabled);
219 * Update the state with the real hardware, which can differ a bit
220 * because of period/duty_cycle approximation.
222 rockchip_pwm_get_state(chip, pwm, state);
225 clk_disable(pc->pclk);
230 static const struct pwm_ops rockchip_pwm_ops = {
231 .get_state = rockchip_pwm_get_state,
232 .apply = rockchip_pwm_apply,
233 .owner = THIS_MODULE,
236 static const struct rockchip_pwm_data pwm_data_v1 = {
244 .supports_polarity = false,
245 .supports_lock = false,
246 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN,
249 static const struct rockchip_pwm_data pwm_data_v2 = {
257 .supports_polarity = true,
258 .supports_lock = false,
259 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
263 static const struct rockchip_pwm_data pwm_data_vop = {
271 .supports_polarity = true,
272 .supports_lock = false,
273 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
277 static const struct rockchip_pwm_data pwm_data_v3 = {
285 .supports_polarity = true,
286 .supports_lock = true,
287 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE |
291 static const struct of_device_id rockchip_pwm_dt_ids[] = {
292 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1},
293 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2},
294 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop},
295 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3},
298 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids);
300 static int rockchip_pwm_probe(struct platform_device *pdev)
302 const struct of_device_id *id;
303 struct rockchip_pwm_chip *pc;
307 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev);
311 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
315 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
316 pc->base = devm_ioremap_resource(&pdev->dev, r);
317 if (IS_ERR(pc->base))
318 return PTR_ERR(pc->base);
320 pc->clk = devm_clk_get(&pdev->dev, "pwm");
321 if (IS_ERR(pc->clk)) {
322 pc->clk = devm_clk_get(&pdev->dev, NULL);
323 if (IS_ERR(pc->clk)) {
324 ret = PTR_ERR(pc->clk);
325 if (ret != -EPROBE_DEFER)
326 dev_err(&pdev->dev, "Can't get bus clk: %d\n",
332 count = of_count_phandle_with_args(pdev->dev.of_node,
333 "clocks", "#clock-cells");
335 pc->pclk = devm_clk_get(&pdev->dev, "pclk");
339 if (IS_ERR(pc->pclk)) {
340 ret = PTR_ERR(pc->pclk);
341 if (ret != -EPROBE_DEFER)
342 dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret);
346 ret = clk_prepare_enable(pc->clk);
348 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret);
352 ret = clk_prepare(pc->pclk);
354 dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret);
358 platform_set_drvdata(pdev, pc);
361 pc->chip.dev = &pdev->dev;
362 pc->chip.ops = &rockchip_pwm_ops;
366 if (pc->data->supports_polarity) {
367 pc->chip.of_xlate = of_pwm_xlate_with_flags;
368 pc->chip.of_pwm_n_cells = 3;
371 ret = pwmchip_add(&pc->chip);
373 clk_unprepare(pc->clk);
374 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
378 /* Keep the PWM clk enabled if the PWM appears to be up and running. */
379 if (!pwm_is_enabled(pc->chip.pwms))
380 clk_disable(pc->clk);
385 clk_unprepare(pc->pclk);
387 clk_disable_unprepare(pc->clk);
392 static int rockchip_pwm_remove(struct platform_device *pdev)
394 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev);
397 * Disable the PWM clk before unpreparing it if the PWM device is still
398 * running. This should only happen when the last PWM user left it
399 * enabled, or when nobody requested a PWM that was previously enabled
402 * FIXME: Maybe the core should disable all PWM devices in
403 * pwmchip_remove(). In this case we'd only have to call
404 * clk_unprepare() after pwmchip_remove().
407 if (pwm_is_enabled(pc->chip.pwms))
408 clk_disable(pc->clk);
410 clk_unprepare(pc->pclk);
411 clk_unprepare(pc->clk);
413 return pwmchip_remove(&pc->chip);
416 static struct platform_driver rockchip_pwm_driver = {
418 .name = "rockchip-pwm",
419 .of_match_table = rockchip_pwm_dt_ids,
421 .probe = rockchip_pwm_probe,
422 .remove = rockchip_pwm_remove,
424 module_platform_driver(rockchip_pwm_driver);
426 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>");
427 MODULE_DESCRIPTION("Rockchip SoC PWM driver");
428 MODULE_LICENSE("GPL v2");