drivers/misc/habanalabs/include/goya/asic_reg/goya_masks.h

   1 /* SPDX-License-Identifier: GPL-2.0
   2  *
   3  * Copyright 2016-2018 HabanaLabs, Ltd.
   4  * All Rights Reserved.
   5  *
   6  */
   7
   8 #ifndef ASIC_REG_GOYA_MASKS_H_
   9 #define ASIC_REG_GOYA_MASKS_H_
  10
  11 #include "goya_regs.h"
  12
  13 /* Useful masks for bits in various registers */
  14 #define QMAN_DMA_ENABLE         (\
  15         (1 << DMA_QM_0_GLBL_CFG0_PQF_EN_SHIFT) | \
  16         (1 << DMA_QM_0_GLBL_CFG0_CQF_EN_SHIFT) | \
  17         (1 << DMA_QM_0_GLBL_CFG0_CP_EN_SHIFT) | \
  18         (1 << DMA_QM_0_GLBL_CFG0_DMA_EN_SHIFT))
  19
  20 #define QMAN_DMA_FULLY_TRUSTED  (\
  21         (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \
  22         (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \
  23         (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \
  24         (1 << DMA_QM_0_GLBL_PROT_DMA_PROT_SHIFT) | \
  25         (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
  26         (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
  27         (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
  28         (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT))
  29
  30 #define QMAN_DMA_PARTLY_TRUSTED (\
  31         (1 << DMA_QM_0_GLBL_PROT_PQF_PROT_SHIFT) | \
  32         (1 << DMA_QM_0_GLBL_PROT_CQF_PROT_SHIFT) | \
  33         (1 << DMA_QM_0_GLBL_PROT_CP_PROT_SHIFT) | \
  34         (1 << DMA_QM_0_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
  35         (1 << DMA_QM_0_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
  36         (1 << DMA_QM_0_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
  37         (1 << DMA_QM_0_GLBL_PROT_DMA_ERR_PROT_SHIFT))
  38
  39 #define QMAN_DMA_STOP           (\
  40         (1 << DMA_QM_0_GLBL_CFG1_PQF_STOP_SHIFT) | \
  41         (1 << DMA_QM_0_GLBL_CFG1_CQF_STOP_SHIFT) | \
  42         (1 << DMA_QM_0_GLBL_CFG1_CP_STOP_SHIFT) | \
  43         (1 << DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT))
  44
  45 #define QMAN_DMA_IS_STOPPED             (\
  46         (1 << DMA_QM_0_GLBL_STS0_PQF_IS_STOP_SHIFT) | \
  47         (1 << DMA_QM_0_GLBL_STS0_CQF_IS_STOP_SHIFT) | \
  48         (1 << DMA_QM_0_GLBL_STS0_CP_IS_STOP_SHIFT) | \
  49         (1 << DMA_QM_0_GLBL_STS0_DMA_IS_STOP_SHIFT))
  50
  51 #define QMAN_DMA_ERR_MSG_EN     (\
  52         (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
  53         (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
  54         (1 << DMA_QM_0_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
  55         (1 << DMA_QM_0_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
  56         (1 << DMA_QM_0_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
  57         (1 << DMA_QM_0_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
  58         (1 << DMA_QM_0_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT))
  59
  60 #define QMAN_MME_ENABLE         (\
  61         (1 << MME_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
  62         (1 << MME_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
  63         (1 << MME_QM_GLBL_CFG0_CP_EN_SHIFT))
  64
  65 #define CMDQ_MME_ENABLE         (\
  66         (1 << MME_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \
  67         (1 << MME_CMDQ_GLBL_CFG0_CP_EN_SHIFT))
  68
  69 #define QMAN_MME_STOP           (\
  70         (1 << MME_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \
  71         (1 << MME_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \
  72         (1 << MME_QM_GLBL_CFG1_CP_STOP_SHIFT))
  73
  74 #define CMDQ_MME_STOP           (\
  75         (1 << MME_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \
  76         (1 << MME_CMDQ_GLBL_CFG1_CP_STOP_SHIFT))
  77
  78 #define QMAN_MME_ERR_MSG_EN     (\
  79         (1 << MME_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
  80         (1 << MME_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
  81         (1 << MME_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
  82         (1 << MME_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
  83         (1 << MME_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
  84         (1 << MME_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
  85         (1 << MME_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
  86         (1 << MME_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
  87
  88 #define CMDQ_MME_ERR_MSG_EN     (\
  89         (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
  90         (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
  91         (1 << MME_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
  92         (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
  93         (1 << MME_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
  94         (1 << MME_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
  95         (1 << MME_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
  96         (1 << MME_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
  97
  98 #define QMAN_MME_ERR_PROT       (\
  99         (1 << MME_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
 100         (1 << MME_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
 101         (1 << MME_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
 102         (1 << MME_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT))
 103
 104 #define CMDQ_MME_ERR_PROT       (\
 105         (1 << MME_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
 106         (1 << MME_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
 107         (1 << MME_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
 108         (1 << MME_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT))
 109
 110 #define QMAN_TPC_ENABLE         (\
 111         (1 << TPC0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
 112         (1 << TPC0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
 113         (1 << TPC0_QM_GLBL_CFG0_CP_EN_SHIFT))
 114
 115 #define CMDQ_TPC_ENABLE         (\
 116         (1 << TPC0_CMDQ_GLBL_CFG0_CQF_EN_SHIFT) | \
 117         (1 << TPC0_CMDQ_GLBL_CFG0_CP_EN_SHIFT))
 118
 119 #define QMAN_TPC_STOP           (\
 120         (1 << TPC0_QM_GLBL_CFG1_PQF_STOP_SHIFT) | \
 121         (1 << TPC0_QM_GLBL_CFG1_CQF_STOP_SHIFT) | \
 122         (1 << TPC0_QM_GLBL_CFG1_CP_STOP_SHIFT))
 123
 124 #define CMDQ_TPC_STOP           (\
 125         (1 << TPC0_CMDQ_GLBL_CFG1_CQF_STOP_SHIFT) | \
 126         (1 << TPC0_CMDQ_GLBL_CFG1_CP_STOP_SHIFT))
 127
 128 #define QMAN_TPC_ERR_MSG_EN     (\
 129         (1 << TPC0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
 130         (1 << TPC0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
 131         (1 << TPC0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
 132         (1 << TPC0_QM_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
 133         (1 << TPC0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
 134         (1 << TPC0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
 135         (1 << TPC0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
 136         (1 << TPC0_QM_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
 137
 138 #define CMDQ_TPC_ERR_MSG_EN     (\
 139         (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \
 140         (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \
 141         (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT) | \
 142         (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_ERR_MSG_EN_SHIFT) | \
 143         (1 << TPC0_CMDQ_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \
 144         (1 << TPC0_CMDQ_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \
 145         (1 << TPC0_CMDQ_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \
 146         (1 << TPC0_CMDQ_GLBL_ERR_CFG_DMA_STOP_ON_ERR_SHIFT))
 147
 148 #define QMAN_TPC_ERR_PROT       (\
 149         (1 << TPC0_QM_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
 150         (1 << TPC0_QM_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
 151         (1 << TPC0_QM_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
 152         (1 << TPC0_QM_GLBL_PROT_DMA_ERR_PROT_SHIFT))
 153
 154 #define CMDQ_TPC_ERR_PROT       (\
 155         (1 << TPC0_CMDQ_GLBL_PROT_PQF_ERR_PROT_SHIFT) | \
 156         (1 << TPC0_CMDQ_GLBL_PROT_CQF_ERR_PROT_SHIFT) | \
 157         (1 << TPC0_CMDQ_GLBL_PROT_CP_ERR_PROT_SHIFT) | \
 158         (1 << TPC0_CMDQ_GLBL_PROT_DMA_ERR_PROT_SHIFT))
 159
 160 /* RESETS */
 161 #define DMA_MME_TPC_RESET       (\
 162                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\
 163                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\
 164                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT)
 165
 166 #define RESET_ALL       (\
 167                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_TPC_SHIFT |\
 168                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MME_SHIFT |\
 169                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_MC_SHIFT |\
 170                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_CPU_SHIFT |\
 171                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_PSOC_SHIFT |\
 172                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_IC_IF_SHIFT |\
 173                         PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_SRAM_MASK |\
 174                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_SHIFT |\
 175                         1 << PSOC_GLOBAL_CONF_SW_ALL_RST_CFG_DMA_IF_SHIFT)
 176
 177 #define CA53_RESET              (\
 178                         (~\
 179                         (1 << PSOC_GLOBAL_CONF_UNIT_RST_N_CPU_SHIFT)\
 180                         ) & 0x7FFFFF)
 181
 182 #define CPU_RESET_ASSERT        (\
 183                         1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
 184
 185 #define CPU_RESET_CORE0_DEASSERT        (\
 186                         1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCPUPORESET_SHIFT |\
 187                         1 << CPU_CA53_CFG_ARM_RST_CONTROL_NCORERESET_SHIFT |\
 188                         1 << CPU_CA53_CFG_ARM_RST_CONTROL_NL2RESET_SHIFT |\
 189                         1 << CPU_CA53_CFG_ARM_RST_CONTROL_NMBISTRESET_SHIFT)
 190
 191 #define GOYA_IRQ_HBW_ID_MASK                    0x1FFF
 192 #define GOYA_IRQ_HBW_ID_SHIFT                   0
 193 #define GOYA_IRQ_HBW_INTERNAL_ID_MASK           0xE000
 194 #define GOYA_IRQ_HBW_INTERNAL_ID_SHIFT          13
 195 #define GOYA_IRQ_HBW_AGENT_ID_MASK              0x1F0000
 196 #define GOYA_IRQ_HBW_AGENT_ID_SHIFT             16
 197 #define GOYA_IRQ_HBW_Y_MASK                     0xE00000
 198 #define GOYA_IRQ_HBW_Y_SHIFT                    21
 199 #define GOYA_IRQ_HBW_X_MASK                     0x7000000
 200 #define GOYA_IRQ_HBW_X_SHIFT                    24
 201 #define GOYA_IRQ_LBW_ID_MASK                    0xFF
 202 #define GOYA_IRQ_LBW_ID_SHIFT                   0
 203 #define GOYA_IRQ_LBW_INTERNAL_ID_MASK           0x700
 204 #define GOYA_IRQ_LBW_INTERNAL_ID_SHIFT          8
 205 #define GOYA_IRQ_LBW_AGENT_ID_MASK              0xF800
 206 #define GOYA_IRQ_LBW_AGENT_ID_SHIFT             11
 207 #define GOYA_IRQ_LBW_Y_MASK                     0x70000
 208 #define GOYA_IRQ_LBW_Y_SHIFT                    16
 209 #define GOYA_IRQ_LBW_X_MASK                     0x380000
 210 #define GOYA_IRQ_LBW_X_SHIFT                    19
 211
 212 #define DMA_QM_IDLE_MASK        (DMA_QM_0_GLBL_STS0_PQF_IDLE_MASK | \
 213                                 DMA_QM_0_GLBL_STS0_CQF_IDLE_MASK | \
 214                                 DMA_QM_0_GLBL_STS0_CP_IDLE_MASK | \
 215                                 DMA_QM_0_GLBL_STS0_DMA_IDLE_MASK)
 216
 217 #define TPC_QM_IDLE_MASK        (TPC0_QM_GLBL_STS0_PQF_IDLE_MASK | \
 218                                 TPC0_QM_GLBL_STS0_CQF_IDLE_MASK | \
 219                                 TPC0_QM_GLBL_STS0_CP_IDLE_MASK)
 220
 221 #define TPC_CMDQ_IDLE_MASK      (TPC0_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \
 222                                 TPC0_CMDQ_GLBL_STS0_CP_IDLE_MASK)
 223
 224 #define TPC_CFG_IDLE_MASK       (TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \
 225                                 TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \
 226                                 TPC0_CFG_STATUS_IQ_EMPTY_MASK | \
 227                                 TPC0_CFG_STATUS_NO_INFLIGH_MEM_ACCESSES_MASK)
 228
 229 #define MME_QM_IDLE_MASK        (MME_QM_GLBL_STS0_PQF_IDLE_MASK | \
 230                                 MME_QM_GLBL_STS0_CQF_IDLE_MASK | \
 231                                 MME_QM_GLBL_STS0_CP_IDLE_MASK)
 232
 233 #define MME_CMDQ_IDLE_MASK      (MME_CMDQ_GLBL_STS0_CQF_IDLE_MASK | \
 234                                 MME_CMDQ_GLBL_STS0_CP_IDLE_MASK)
 235
 236 #define MME_ARCH_IDLE_MASK      (MME_ARCH_STATUS_SB_A_EMPTY_MASK | \
 237                                 MME_ARCH_STATUS_SB_B_EMPTY_MASK | \
 238                                 MME_ARCH_STATUS_SB_CIN_EMPTY_MASK | \
 239                                 MME_ARCH_STATUS_SB_COUT_EMPTY_MASK)
 240
 241 #define MME_SHADOW_IDLE_MASK    (MME_SHADOW_0_STATUS_A_MASK | \
 242                                 MME_SHADOW_0_STATUS_B_MASK | \
 243                                 MME_SHADOW_0_STATUS_CIN_MASK | \
 244                                 MME_SHADOW_0_STATUS_COUT_MASK | \
 245                                 MME_SHADOW_0_STATUS_TE_MASK | \
 246                                 MME_SHADOW_0_STATUS_LD_MASK | \
 247                                 MME_SHADOW_0_STATUS_ST_MASK)
 248
 249 #define TPC1_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 250 #define TPC2_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 251 #define TPC3_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 252 #define TPC4_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 253 #define TPC5_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 254 #define TPC6_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 255 #define TPC7_CFG_TPC_STALL_V_SHIFT TPC0_CFG_TPC_STALL_V_SHIFT
 256
 257 #define DMA_QM_1_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 258 #define DMA_QM_2_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 259 #define DMA_QM_3_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 260 #define DMA_QM_4_GLBL_CFG1_DMA_STOP_SHIFT DMA_QM_0_GLBL_CFG1_DMA_STOP_SHIFT
 261
 262 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT      1
 263 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK       0x1
 264 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK       0x2
 265 #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK         0xF00
 266
 267 #endif /* ASIC_REG_GOYA_MASKS_H_ */