2 * Copyright © 2014 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <linux/firmware.h>
29 #include "intel_csr.h"
33 * DOC: csr support for dmc
35 * Display Context Save and Restore (CSR) firmware support added from gen9
36 * onwards to drive newly added DMC (Display microcontroller) in display
37 * engine to save and restore the state of display engine when it enter into
38 * low-power state and comes back to normal.
41 #define GEN12_CSR_MAX_FW_SIZE ICL_CSR_MAX_FW_SIZE
43 #define ADLS_CSR_PATH "i915/adls_dmc_ver2_01.bin"
44 #define ADLS_CSR_VERSION_REQUIRED CSR_VERSION(2, 1)
45 MODULE_FIRMWARE(ADLS_CSR_PATH);
47 #define DG1_CSR_PATH "i915/dg1_dmc_ver2_02.bin"
48 #define DG1_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
49 MODULE_FIRMWARE(DG1_CSR_PATH);
51 #define RKL_CSR_PATH "i915/rkl_dmc_ver2_02.bin"
52 #define RKL_CSR_VERSION_REQUIRED CSR_VERSION(2, 2)
53 MODULE_FIRMWARE(RKL_CSR_PATH);
55 #define TGL_CSR_PATH "i915/tgl_dmc_ver2_08.bin"
56 #define TGL_CSR_VERSION_REQUIRED CSR_VERSION(2, 8)
57 MODULE_FIRMWARE(TGL_CSR_PATH);
59 #define ICL_CSR_PATH "i915/icl_dmc_ver1_09.bin"
60 #define ICL_CSR_VERSION_REQUIRED CSR_VERSION(1, 9)
61 #define ICL_CSR_MAX_FW_SIZE 0x6000
62 MODULE_FIRMWARE(ICL_CSR_PATH);
64 #define CNL_CSR_PATH "i915/cnl_dmc_ver1_07.bin"
65 #define CNL_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
66 #define CNL_CSR_MAX_FW_SIZE GLK_CSR_MAX_FW_SIZE
67 MODULE_FIRMWARE(CNL_CSR_PATH);
69 #define GLK_CSR_PATH "i915/glk_dmc_ver1_04.bin"
70 #define GLK_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
71 #define GLK_CSR_MAX_FW_SIZE 0x4000
72 MODULE_FIRMWARE(GLK_CSR_PATH);
74 #define KBL_CSR_PATH "i915/kbl_dmc_ver1_04.bin"
75 #define KBL_CSR_VERSION_REQUIRED CSR_VERSION(1, 4)
76 #define KBL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
77 MODULE_FIRMWARE(KBL_CSR_PATH);
79 #define SKL_CSR_PATH "i915/skl_dmc_ver1_27.bin"
80 #define SKL_CSR_VERSION_REQUIRED CSR_VERSION(1, 27)
81 #define SKL_CSR_MAX_FW_SIZE BXT_CSR_MAX_FW_SIZE
82 MODULE_FIRMWARE(SKL_CSR_PATH);
84 #define BXT_CSR_PATH "i915/bxt_dmc_ver1_07.bin"
85 #define BXT_CSR_VERSION_REQUIRED CSR_VERSION(1, 7)
86 #define BXT_CSR_MAX_FW_SIZE 0x3000
87 MODULE_FIRMWARE(BXT_CSR_PATH);
89 #define CSR_DEFAULT_FW_OFFSET 0xFFFFFFFF
90 #define PACKAGE_MAX_FW_INFO_ENTRIES 20
91 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32
92 #define DMC_V1_MAX_MMIO_COUNT 8
93 #define DMC_V3_MAX_MMIO_COUNT 20
95 struct intel_css_header {
99 /* Includes the DMC specific header in dwords */
102 /* always value would be 0x10000 */
111 /* in YYYYMMDD format */
114 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */
136 u32 kernel_header_info;
139 struct intel_fw_info {
142 /* reserved on package_header version 1, must be 0 on version 2 */
145 /* Stepping (A, B, C, ..., *). * is a wildcard */
148 /* Sub-stepping (0, 1, ..., *). * is a wildcard */
155 struct intel_package_header {
156 /* DMC container header length in dwords */
164 /* Number of valid entries in the FWInfo array below */
168 struct intel_dmc_header_base {
169 /* always value would be 0x40403E3E */
172 /* DMC binary header length */
184 /* Firmware program size (excluding header) in dwords */
187 /* Major Minor version */
191 struct intel_dmc_header_v1 {
192 struct intel_dmc_header_base base;
194 /* Number of valid MMIO cycles present. */
198 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT];
201 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT];
209 struct intel_dmc_header_v3 {
210 struct intel_dmc_header_base base;
212 /* DMC RAM start MMIO address */
220 /* Number of valid MMIO cycles present. */
224 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT];
227 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT];
230 struct stepping_info {
235 static const struct stepping_info skl_stepping_info[] = {
236 {'A', '0'}, {'B', '0'}, {'C', '0'},
237 {'D', '0'}, {'E', '0'}, {'F', '0'},
238 {'G', '0'}, {'H', '0'}, {'I', '0'},
239 {'J', '0'}, {'K', '0'}
242 static const struct stepping_info bxt_stepping_info[] = {
243 {'A', '0'}, {'A', '1'}, {'A', '2'},
244 {'B', '0'}, {'B', '1'}, {'B', '2'}
247 static const struct stepping_info icl_stepping_info[] = {
248 {'A', '0'}, {'A', '1'}, {'A', '2'},
249 {'B', '0'}, {'B', '2'},
253 static const struct stepping_info no_stepping_info = { '*', '*' };
255 static const struct stepping_info *
256 intel_get_stepping_info(struct drm_i915_private *dev_priv)
258 const struct stepping_info *si;
261 if (IS_ICELAKE(dev_priv)) {
262 size = ARRAY_SIZE(icl_stepping_info);
263 si = icl_stepping_info;
264 } else if (IS_SKYLAKE(dev_priv)) {
265 size = ARRAY_SIZE(skl_stepping_info);
266 si = skl_stepping_info;
267 } else if (IS_BROXTON(dev_priv)) {
268 size = ARRAY_SIZE(bxt_stepping_info);
269 si = bxt_stepping_info;
275 if (INTEL_REVID(dev_priv) < size)
276 return si + INTEL_REVID(dev_priv);
278 return &no_stepping_info;
281 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv)
285 mask = DC_STATE_DEBUG_MASK_MEMORY_UP;
287 if (IS_GEN9_LP(dev_priv))
288 mask |= DC_STATE_DEBUG_MASK_CORES;
290 /* The below bit doesn't need to be cleared ever afterwards */
291 val = intel_de_read(dev_priv, DC_STATE_DEBUG);
292 if ((val & mask) != mask) {
294 intel_de_write(dev_priv, DC_STATE_DEBUG, val);
295 intel_de_posting_read(dev_priv, DC_STATE_DEBUG);
300 * intel_csr_load_program() - write the firmware from memory to register.
301 * @dev_priv: i915 drm device.
303 * CSR firmware is read from a .bin file and kept in internal memory one time.
304 * Everytime display comes back from low power state this function is called to
305 * copy the firmware from internal memory to registers.
307 void intel_csr_load_program(struct drm_i915_private *dev_priv)
309 u32 *payload = dev_priv->csr.dmc_payload;
312 if (!HAS_CSR(dev_priv)) {
313 drm_err(&dev_priv->drm,
314 "No CSR support available for this platform\n");
318 if (!dev_priv->csr.dmc_payload) {
319 drm_err(&dev_priv->drm,
320 "Tried to program CSR with empty payload\n");
324 fw_size = dev_priv->csr.dmc_fw_size;
325 assert_rpm_wakelock_held(&dev_priv->runtime_pm);
329 for (i = 0; i < fw_size; i++)
330 intel_uncore_write_fw(&dev_priv->uncore, CSR_PROGRAM(i),
335 for (i = 0; i < dev_priv->csr.mmio_count; i++) {
336 intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i],
337 dev_priv->csr.mmiodata[i]);
340 dev_priv->csr.dc_state = 0;
342 gen9_set_dc_state_debugmask(dev_priv);
346 * Search fw_info table for dmc_offset to find firmware binary: num_entries is
349 static u32 find_dmc_fw_offset(const struct intel_fw_info *fw_info,
350 unsigned int num_entries,
351 const struct stepping_info *si,
354 u32 dmc_offset = CSR_DEFAULT_FW_OFFSET;
357 for (i = 0; i < num_entries; i++) {
358 if (package_ver > 1 && fw_info[i].dmc_id != 0)
361 if (fw_info[i].substepping == '*' &&
362 si->stepping == fw_info[i].stepping) {
363 dmc_offset = fw_info[i].offset;
367 if (si->stepping == fw_info[i].stepping &&
368 si->substepping == fw_info[i].substepping) {
369 dmc_offset = fw_info[i].offset;
373 if (fw_info[i].stepping == '*' &&
374 fw_info[i].substepping == '*') {
376 * In theory we should stop the search as generic
377 * entries should always come after the more specific
378 * ones, but let's continue to make sure to work even
379 * with "broken" firmwares. If we don't find a more
380 * specific one, then we use this entry
382 dmc_offset = fw_info[i].offset;
389 static u32 parse_csr_fw_dmc(struct intel_csr *csr,
390 const struct intel_dmc_header_base *dmc_header,
393 unsigned int header_len_bytes, dmc_header_size, payload_size, i;
394 const u32 *mmioaddr, *mmiodata;
395 u32 mmio_count, mmio_count_max;
398 BUILD_BUG_ON(ARRAY_SIZE(csr->mmioaddr) < DMC_V3_MAX_MMIO_COUNT ||
399 ARRAY_SIZE(csr->mmioaddr) < DMC_V1_MAX_MMIO_COUNT);
402 * Check if we can access common fields, we will checkc again below
403 * after we have read the version
405 if (rem_size < sizeof(struct intel_dmc_header_base))
406 goto error_truncated;
408 /* Cope with small differences between v1 and v3 */
409 if (dmc_header->header_ver == 3) {
410 const struct intel_dmc_header_v3 *v3 =
411 (const struct intel_dmc_header_v3 *)dmc_header;
413 if (rem_size < sizeof(struct intel_dmc_header_v3))
414 goto error_truncated;
416 mmioaddr = v3->mmioaddr;
417 mmiodata = v3->mmiodata;
418 mmio_count = v3->mmio_count;
419 mmio_count_max = DMC_V3_MAX_MMIO_COUNT;
420 /* header_len is in dwords */
421 header_len_bytes = dmc_header->header_len * 4;
422 dmc_header_size = sizeof(*v3);
423 } else if (dmc_header->header_ver == 1) {
424 const struct intel_dmc_header_v1 *v1 =
425 (const struct intel_dmc_header_v1 *)dmc_header;
427 if (rem_size < sizeof(struct intel_dmc_header_v1))
428 goto error_truncated;
430 mmioaddr = v1->mmioaddr;
431 mmiodata = v1->mmiodata;
432 mmio_count = v1->mmio_count;
433 mmio_count_max = DMC_V1_MAX_MMIO_COUNT;
434 header_len_bytes = dmc_header->header_len;
435 dmc_header_size = sizeof(*v1);
437 DRM_ERROR("Unknown DMC fw header version: %u\n",
438 dmc_header->header_ver);
442 if (header_len_bytes != dmc_header_size) {
443 DRM_ERROR("DMC firmware has wrong dmc header length "
444 "(%u bytes)\n", header_len_bytes);
448 /* Cache the dmc header info. */
449 if (mmio_count > mmio_count_max) {
450 DRM_ERROR("DMC firmware has wrong mmio count %u\n", mmio_count);
454 for (i = 0; i < mmio_count; i++) {
455 if (mmioaddr[i] < CSR_MMIO_START_RANGE ||
456 mmioaddr[i] > CSR_MMIO_END_RANGE) {
457 DRM_ERROR("DMC firmware has wrong mmio address 0x%x\n",
461 csr->mmioaddr[i] = _MMIO(mmioaddr[i]);
462 csr->mmiodata[i] = mmiodata[i];
464 csr->mmio_count = mmio_count;
466 rem_size -= header_len_bytes;
468 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */
469 payload_size = dmc_header->fw_size * 4;
470 if (rem_size < payload_size)
471 goto error_truncated;
473 if (payload_size > csr->max_fw_size) {
474 DRM_ERROR("DMC FW too big (%u bytes)\n", payload_size);
477 csr->dmc_fw_size = dmc_header->fw_size;
479 csr->dmc_payload = kmalloc(payload_size, GFP_KERNEL);
480 if (!csr->dmc_payload) {
481 DRM_ERROR("Memory allocation failed for dmc payload\n");
485 payload = (u8 *)(dmc_header) + header_len_bytes;
486 memcpy(csr->dmc_payload, payload, payload_size);
488 return header_len_bytes + payload_size;
491 DRM_ERROR("Truncated DMC firmware, refusing.\n");
496 parse_csr_fw_package(struct intel_csr *csr,
497 const struct intel_package_header *package_header,
498 const struct stepping_info *si,
501 u32 package_size = sizeof(struct intel_package_header);
502 u32 num_entries, max_entries, dmc_offset;
503 const struct intel_fw_info *fw_info;
505 if (rem_size < package_size)
506 goto error_truncated;
508 if (package_header->header_ver == 1) {
509 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES;
510 } else if (package_header->header_ver == 2) {
511 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES;
513 DRM_ERROR("DMC firmware has unknown header version %u\n",
514 package_header->header_ver);
519 * We should always have space for max_entries,
520 * even if not all are used
522 package_size += max_entries * sizeof(struct intel_fw_info);
523 if (rem_size < package_size)
524 goto error_truncated;
526 if (package_header->header_len * 4 != package_size) {
527 DRM_ERROR("DMC firmware has wrong package header length "
528 "(%u bytes)\n", package_size);
532 num_entries = package_header->num_entries;
533 if (WARN_ON(package_header->num_entries > max_entries))
534 num_entries = max_entries;
536 fw_info = (const struct intel_fw_info *)
537 ((u8 *)package_header + sizeof(*package_header));
538 dmc_offset = find_dmc_fw_offset(fw_info, num_entries, si,
539 package_header->header_ver);
540 if (dmc_offset == CSR_DEFAULT_FW_OFFSET) {
541 DRM_ERROR("DMC firmware not supported for %c stepping\n",
546 /* dmc_offset is in dwords */
547 return package_size + dmc_offset * 4;
550 DRM_ERROR("Truncated DMC firmware, refusing.\n");
554 /* Return number of bytes parsed or 0 on error */
555 static u32 parse_csr_fw_css(struct intel_csr *csr,
556 struct intel_css_header *css_header,
559 if (rem_size < sizeof(struct intel_css_header)) {
560 DRM_ERROR("Truncated DMC firmware, refusing.\n");
564 if (sizeof(struct intel_css_header) !=
565 (css_header->header_len * 4)) {
566 DRM_ERROR("DMC firmware has wrong CSS header length "
568 (css_header->header_len * 4));
572 if (csr->required_version &&
573 css_header->version != csr->required_version) {
574 DRM_INFO("Refusing to load DMC firmware v%u.%u,"
575 " please use v%u.%u\n",
576 CSR_VERSION_MAJOR(css_header->version),
577 CSR_VERSION_MINOR(css_header->version),
578 CSR_VERSION_MAJOR(csr->required_version),
579 CSR_VERSION_MINOR(csr->required_version));
583 csr->version = css_header->version;
585 return sizeof(struct intel_css_header);
588 static void parse_csr_fw(struct drm_i915_private *dev_priv,
589 const struct firmware *fw)
591 struct intel_css_header *css_header;
592 struct intel_package_header *package_header;
593 struct intel_dmc_header_base *dmc_header;
594 struct intel_csr *csr = &dev_priv->csr;
595 const struct stepping_info *si = intel_get_stepping_info(dev_priv);
602 /* Extract CSS Header information */
603 css_header = (struct intel_css_header *)fw->data;
604 r = parse_csr_fw_css(csr, css_header, fw->size);
610 /* Extract Package Header information */
611 package_header = (struct intel_package_header *)&fw->data[readcount];
612 r = parse_csr_fw_package(csr, package_header, si, fw->size - readcount);
618 /* Extract dmc_header information */
619 dmc_header = (struct intel_dmc_header_base *)&fw->data[readcount];
620 parse_csr_fw_dmc(csr, dmc_header, fw->size - readcount);
623 static void intel_csr_runtime_pm_get(struct drm_i915_private *dev_priv)
625 drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
626 dev_priv->csr.wakeref =
627 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
630 static void intel_csr_runtime_pm_put(struct drm_i915_private *dev_priv)
632 intel_wakeref_t wakeref __maybe_unused =
633 fetch_and_zero(&dev_priv->csr.wakeref);
635 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
638 static void csr_load_work_fn(struct work_struct *work)
640 struct drm_i915_private *dev_priv;
641 struct intel_csr *csr;
642 const struct firmware *fw = NULL;
644 dev_priv = container_of(work, typeof(*dev_priv), csr.work);
645 csr = &dev_priv->csr;
647 request_firmware(&fw, dev_priv->csr.fw_path, dev_priv->drm.dev);
648 parse_csr_fw(dev_priv, fw);
650 if (dev_priv->csr.dmc_payload) {
651 intel_csr_load_program(dev_priv);
652 intel_csr_runtime_pm_put(dev_priv);
654 drm_info(&dev_priv->drm,
655 "Finished loading DMC firmware %s (v%u.%u)\n",
656 dev_priv->csr.fw_path, CSR_VERSION_MAJOR(csr->version),
657 CSR_VERSION_MINOR(csr->version));
659 drm_notice(&dev_priv->drm,
660 "Failed to load DMC firmware %s."
661 " Disabling runtime power management.\n",
663 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s",
664 INTEL_UC_FIRMWARE_URL);
667 release_firmware(fw);
671 * intel_csr_ucode_init() - initialize the firmware loading.
672 * @dev_priv: i915 drm device.
674 * This function is called at the time of loading the display driver to read
675 * firmware from a .bin file and copied into a internal memory.
677 void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
679 struct intel_csr *csr = &dev_priv->csr;
681 INIT_WORK(&dev_priv->csr.work, csr_load_work_fn);
683 if (!HAS_CSR(dev_priv))
687 * Obtain a runtime pm reference, until CSR is loaded, to avoid entering
690 * On error, we return with the rpm wakeref held to prevent runtime
691 * suspend as runtime suspend *requires* a working CSR for whatever
694 intel_csr_runtime_pm_get(dev_priv);
696 if (IS_ALDERLAKE_S(dev_priv)) {
697 csr->fw_path = ADLS_CSR_PATH;
698 csr->required_version = ADLS_CSR_VERSION_REQUIRED;
699 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
700 } else if (IS_DG1(dev_priv)) {
701 csr->fw_path = DG1_CSR_PATH;
702 csr->required_version = DG1_CSR_VERSION_REQUIRED;
703 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
704 } else if (IS_ROCKETLAKE(dev_priv)) {
705 csr->fw_path = RKL_CSR_PATH;
706 csr->required_version = RKL_CSR_VERSION_REQUIRED;
707 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
708 } else if (DISPLAY_VER(dev_priv) >= 12) {
709 csr->fw_path = TGL_CSR_PATH;
710 csr->required_version = TGL_CSR_VERSION_REQUIRED;
711 csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
712 } else if (IS_DISPLAY_VER(dev_priv, 11)) {
713 csr->fw_path = ICL_CSR_PATH;
714 csr->required_version = ICL_CSR_VERSION_REQUIRED;
715 csr->max_fw_size = ICL_CSR_MAX_FW_SIZE;
716 } else if (IS_CANNONLAKE(dev_priv)) {
717 csr->fw_path = CNL_CSR_PATH;
718 csr->required_version = CNL_CSR_VERSION_REQUIRED;
719 csr->max_fw_size = CNL_CSR_MAX_FW_SIZE;
720 } else if (IS_GEMINILAKE(dev_priv)) {
721 csr->fw_path = GLK_CSR_PATH;
722 csr->required_version = GLK_CSR_VERSION_REQUIRED;
723 csr->max_fw_size = GLK_CSR_MAX_FW_SIZE;
724 } else if (IS_KABYLAKE(dev_priv) ||
725 IS_COFFEELAKE(dev_priv) ||
726 IS_COMETLAKE(dev_priv)) {
727 csr->fw_path = KBL_CSR_PATH;
728 csr->required_version = KBL_CSR_VERSION_REQUIRED;
729 csr->max_fw_size = KBL_CSR_MAX_FW_SIZE;
730 } else if (IS_SKYLAKE(dev_priv)) {
731 csr->fw_path = SKL_CSR_PATH;
732 csr->required_version = SKL_CSR_VERSION_REQUIRED;
733 csr->max_fw_size = SKL_CSR_MAX_FW_SIZE;
734 } else if (IS_BROXTON(dev_priv)) {
735 csr->fw_path = BXT_CSR_PATH;
736 csr->required_version = BXT_CSR_VERSION_REQUIRED;
737 csr->max_fw_size = BXT_CSR_MAX_FW_SIZE;
740 if (dev_priv->params.dmc_firmware_path) {
741 if (strlen(dev_priv->params.dmc_firmware_path) == 0) {
743 drm_info(&dev_priv->drm,
744 "Disabling CSR firmware and runtime PM\n");
748 csr->fw_path = dev_priv->params.dmc_firmware_path;
749 /* Bypass version check for firmware override. */
750 csr->required_version = 0;
753 if (csr->fw_path == NULL) {
754 drm_dbg_kms(&dev_priv->drm,
755 "No known CSR firmware for platform, disabling runtime PM\n");
759 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", csr->fw_path);
760 schedule_work(&dev_priv->csr.work);
764 * intel_csr_ucode_suspend() - prepare CSR firmware before system suspend
765 * @dev_priv: i915 drm device
767 * Prepare the DMC firmware before entering system suspend. This includes
768 * flushing pending work items and releasing any resources acquired during
771 void intel_csr_ucode_suspend(struct drm_i915_private *dev_priv)
773 if (!HAS_CSR(dev_priv))
776 flush_work(&dev_priv->csr.work);
778 /* Drop the reference held in case DMC isn't loaded. */
779 if (!dev_priv->csr.dmc_payload)
780 intel_csr_runtime_pm_put(dev_priv);
784 * intel_csr_ucode_resume() - init CSR firmware during system resume
785 * @dev_priv: i915 drm device
787 * Reinitialize the DMC firmware during system resume, reacquiring any
788 * resources released in intel_csr_ucode_suspend().
790 void intel_csr_ucode_resume(struct drm_i915_private *dev_priv)
792 if (!HAS_CSR(dev_priv))
796 * Reacquire the reference to keep RPM disabled in case DMC isn't
799 if (!dev_priv->csr.dmc_payload)
800 intel_csr_runtime_pm_get(dev_priv);
804 * intel_csr_ucode_fini() - unload the CSR firmware.
805 * @dev_priv: i915 drm device.
807 * Firmmware unloading includes freeing the internal memory and reset the
808 * firmware loading status.
810 void intel_csr_ucode_fini(struct drm_i915_private *dev_priv)
812 if (!HAS_CSR(dev_priv))
815 intel_csr_ucode_suspend(dev_priv);
816 drm_WARN_ON(&dev_priv->drm, dev_priv->csr.wakeref);
818 kfree(dev_priv->csr.dmc_payload);