Merge tag 'perf-core-2021-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull perf event updates from Ingo Molnar:

 - Improve Intel uncore PMU support:

     - Parse uncore 'discovery tables' - a new hardware capability
       enumeration method introduced on the latest Intel platforms. This
       table is in a well-defined PCI namespace location and is read via
       MMIO. It is organized in an rbtree.

       These uncore tables will allow the discovery of standard counter
       blocks, but fancier counters still need to be enumerated
       explicitly.

     - Add Alder Lake support

     - Improve IIO stacks to PMON mapping support on Skylake servers

 - Add Intel Alder Lake PMU support - which requires the introduction of
   'hybrid' CPUs and PMUs. Alder Lake is a mix of Golden Cove ('big')
   and Gracemont ('small' - Atom derived) cores.

   The CPU-side feature set is entirely symmetrical - but on the PMU
   side there's core type dependent PMU functionality.

 - Reduce data loss with CPU level hardware tracing on Intel PT / AUX
   profiling, by fixing the AUX allocation watermark logic.

 - Improve ring buffer allocation on NUMA systems

 - Put 'struct perf_event' into their separate kmem_cache pool

 - Add support for synchronous signals for select perf events. The
   immediate motivation is to support low-overhead sampling-based race
   detection for user-space code. The feature consists of the following
   main changes:

     - Add thread-only event inheritance via
       perf_event_attr::inherit_thread, which limits inheritance of
       events to CLONE_THREAD.

     - Add the ability for events to not leak through exec(), via
       perf_event_attr::remove_on_exec.

     - Allow the generation of SIGTRAP via perf_event_attr::sigtrap,
       extend siginfo with an u64 ::si_perf, and add the breakpoint
       information to ::si_addr and ::si_perf if the event is
       PERF_TYPE_BREAKPOINT.

   The siginfo support is adequate for breakpoints right now - but the
   new field can be used to introduce support for other types of
   metadata passed over siginfo as well.

 - Misc fixes, cleanups and smaller updates.

* tag 'perf-core-2021-04-28' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (53 commits)
  signal, perf: Add missing TRAP_PERF case in siginfo_layout()
  signal, perf: Fix siginfo_t by avoiding u64 on 32-bit architectures
  perf/x86: Allow for 8<num_fixed_counters<16
  perf/x86/rapl: Add support for Intel Alder Lake
  perf/x86/cstate: Add Alder Lake CPU support
  perf/x86/msr: Add Alder Lake CPU support
  perf/x86/intel/uncore: Add Alder Lake support
  perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE
  perf/x86/intel: Add Alder Lake Hybrid support
  perf/x86: Support filter_match callback
  perf/x86/intel: Add attr_update for Hybrid PMUs
  perf/x86: Add structures for the attributes of Hybrid PMUs
  perf/x86: Register hybrid PMUs
  perf/x86: Factor out x86_pmu_show_pmu_cap
  perf/x86: Remove temporary pmu assignment in event_init
  perf/x86/intel: Factor out intel_pmu_check_extra_regs
  perf/x86/intel: Factor out intel_pmu_check_event_constraints
  perf/x86/intel: Factor out intel_pmu_check_num_counters
  perf/x86: Hybrid PMU support for extra_regs
  perf/x86: Hybrid PMU support for event constraints
  ...

diff --cc arch/x86/events/core.c
Simple merge

diff --cc arch/x86/events/intel/core.c
Simple merge

diff --cc arch/x86/events/intel/ds.c
Simple merge

diff --cc arch/x86/events/intel/lbr.c
Simple merge

diff --cc arch/x86/events/intel/p4.c
Simple merge

diff --cc arch/x86/events/intel/uncore_snbep.c
Simple merge

diff --cc arch/x86/include/asm/cpu.h
index 0d7fc0e,610905d..33d41e3
--- 1/arch/x86/include/asm/cpu.h
--- 2/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@@ -45,9 -45,9 +45,10 @@@ extern void __init sld_setup(struct cpu
  extern void switch_to_sld(unsigned long tifn);
  extern bool handle_user_split_lock(struct pt_regs *regs, long error_code);
  extern bool handle_guest_split_lock(unsigned long ip);
 +extern void handle_bus_lock(struct pt_regs *regs);
+ u8 get_this_hybrid_cpu_type(void);
  #else
 -static inline void __init cpu_set_core_cap_bits(struct cpuinfo_x86 *c) {}
 +static inline void __init sld_setup(struct cpuinfo_x86 *c) {}
  static inline void switch_to_sld(unsigned long tifn) {}
  static inline bool handle_user_split_lock(struct pt_regs *regs, long error_code)
  {
@@@ -59,7 -59,10 +60,12 @@@ static inline bool handle_guest_split_l
        return false;
  }
  
 +static inline void handle_bus_lock(struct pt_regs *regs) {}
++
+ static inline u8 get_this_hybrid_cpu_type(void)
+ {
+       return 0;
+ }
  #endif
  #ifdef CONFIG_IA32_FEAT_CTL
  void init_ia32_feat_ctl(struct cpuinfo_x86 *c);

diff --cc arch/x86/include/asm/cpufeatures.h
Simple merge

diff --cc arch/x86/include/asm/msr-index.h
Simple merge

diff --cc arch/x86/kernel/cpu/intel.c
index fe0bec1,26fb626..8adffc1
--- 1/arch/x86/kernel/cpu/intel.c
--- 2/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@@ -1231,40 -1193,21 +1231,56 @@@ static void __init split_lock_setup(str
        }
  
        cpu_model_supports_sld = true;
 -      split_lock_setup();
 +      __split_lock_setup();
 +}
 +
 +static void sld_state_show(void)
 +{
 +      if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
 +          !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
 +              return;
 +
 +      switch (sld_state) {
 +      case sld_off:
 +              pr_info("disabled\n");
 +              break;
 +      case sld_warn:
 +              if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
 +                      pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
 +              else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
 +                      pr_info("#DB: warning on user-space bus_locks\n");
 +              break;
 +      case sld_fatal:
 +              if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
 +                      pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
 +              } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
 +                      pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
 +                              boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
 +                              " from non-WB" : "");
 +              }
 +              break;
 +      }
 +}
 +
 +void __init sld_setup(struct cpuinfo_x86 *c)
 +{
 +      split_lock_setup(c);
 +      sld_state_setup();
 +      sld_state_show();
  }
+ 
+ #define X86_HYBRID_CPU_TYPE_ID_SHIFT  24
+ 
+ /**
+  * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
+  *
+  * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
+  * a hybrid processor. If the processor is not hybrid, returns 0.
+  */
+ u8 get_this_hybrid_cpu_type(void)
+ {
+       if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
+               return 0;
+ 
+       return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
+ }

diff --cc kernel/fork.c
Simple merge

diff --cc kernel/signal.c
Simple merge