drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/pm_qos.h>
  28 #include <trace/events/power.h>
  29
  30 #include <asm/div64.h>
  31 #include <asm/msr.h>
  32 #include <asm/cpu_device_id.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/intel-family.h>
  35 #include "../drivers/thermal/intel/thermal_interrupt.h"
  36
  37 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  38
  39 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  40 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP      5000
  41 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  42
  43 #ifdef CONFIG_ACPI
  44 #include <acpi/processor.h>
  45 #include <acpi/cppc_acpi.h>
  46 #endif
  47
  48 #define FRAC_BITS 8
  49 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  50 #define fp_toint(X) ((X) >> FRAC_BITS)
  51
  52 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  53
  54 #define EXT_BITS 6
  55 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  56 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  57 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  58
  59 static inline int32_t mul_fp(int32_t x, int32_t y)
  60 {
  61         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  62 }
  63
  64 static inline int32_t div_fp(s64 x, s64 y)
  65 {
  66         return div64_s64((int64_t)x << FRAC_BITS, y);
  67 }
  68
  69 static inline int ceiling_fp(int32_t x)
  70 {
  71         int mask, ret;
  72
  73         ret = fp_toint(x);
  74         mask = (1 << FRAC_BITS) - 1;
  75         if (x & mask)
  76                 ret += 1;
  77         return ret;
  78 }
  79
  80 static inline u64 mul_ext_fp(u64 x, u64 y)
  81 {
  82         return (x * y) >> EXT_FRAC_BITS;
  83 }
  84
  85 static inline u64 div_ext_fp(u64 x, u64 y)
  86 {
  87         return div64_u64(x << EXT_FRAC_BITS, y);
  88 }
  89
  90 /**
  91  * struct sample -      Store performance sample
  92  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  93  *                      performance during last sample period
  94  * @busy_scaled:        Scaled busy value which is used to calculate next
  95  *                      P state. This can be different than core_avg_perf
  96  *                      to account for cpu idle period
  97  * @aperf:              Difference of actual performance frequency clock count
  98  *                      read from APERF MSR between last and current sample
  99  * @mperf:              Difference of maximum performance frequency clock count
 100  *                      read from MPERF MSR between last and current sample
 101  * @tsc:                Difference of time stamp counter between last and
 102  *                      current sample
 103  * @time:               Current time from scheduler
 104  *
 105  * This structure is used in the cpudata structure to store performance sample
 106  * data for choosing next P State.
 107  */
 108 struct sample {
 109         int32_t core_avg_perf;
 110         int32_t busy_scaled;
 111         u64 aperf;
 112         u64 mperf;
 113         u64 tsc;
 114         u64 time;
 115 };
 116
 117 /**
 118  * struct pstate_data - Store P state data
 119  * @current_pstate:     Current requested P state
 120  * @min_pstate:         Min P state possible for this platform
 121  * @max_pstate:         Max P state possible for this platform
 122  * @max_pstate_physical:This is physical Max P state for a processor
 123  *                      This can be higher than the max_pstate which can
 124  *                      be limited by platform thermal design power limits
 125  * @perf_ctl_scaling:   PERF_CTL P-state to frequency scaling factor
 126  * @scaling:            Scaling factor between performance and frequency
 127  * @turbo_pstate:       Max Turbo P state possible for this platform
 128  * @min_freq:           @min_pstate frequency in cpufreq units
 129  * @max_freq:           @max_pstate frequency in cpufreq units
 130  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 131  *
 132  * Stores the per cpu model P state limits and current P state.
 133  */
 134 struct pstate_data {
 135         int     current_pstate;
 136         int     min_pstate;
 137         int     max_pstate;
 138         int     max_pstate_physical;
 139         int     perf_ctl_scaling;
 140         int     scaling;
 141         int     turbo_pstate;
 142         unsigned int min_freq;
 143         unsigned int max_freq;
 144         unsigned int turbo_freq;
 145 };
 146
 147 /**
 148  * struct vid_data -    Stores voltage information data
 149  * @min:                VID data for this platform corresponding to
 150  *                      the lowest P state
 151  * @max:                VID data corresponding to the highest P State.
 152  * @turbo:              VID data for turbo P state
 153  * @ratio:              Ratio of (vid max - vid min) /
 154  *                      (max P state - Min P State)
 155  *
 156  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 157  * This data is used in Atom platforms, where in addition to target P state,
 158  * the voltage data needs to be specified to select next P State.
 159  */
 160 struct vid_data {
 161         int min;
 162         int max;
 163         int turbo;
 164         int32_t ratio;
 165 };
 166
 167 /**
 168  * struct global_params - Global parameters, mostly tunable via sysfs.
 169  * @no_turbo:           Whether or not to use turbo P-states.
 170  * @turbo_disabled:     Whether or not turbo P-states are available at all,
 171  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 172  *                      not the maximum reported turbo P-state is different from
 173  *                      the maximum reported non-turbo one.
 174  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 175  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 176  *                      P-state capacity.
 177  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 178  *                      P-state capacity.
 179  */
 180 struct global_params {
 181         bool no_turbo;
 182         bool turbo_disabled;
 183         bool turbo_disabled_mf;
 184         int max_perf_pct;
 185         int min_perf_pct;
 186 };
 187
 188 /**
 189  * struct cpudata -     Per CPU instance data storage
 190  * @cpu:                CPU number for this instance data
 191  * @policy:             CPUFreq policy value
 192  * @update_util:        CPUFreq utility callback information
 193  * @update_util_set:    CPUFreq utility callback is set
 194  * @iowait_boost:       iowait-related boost fraction
 195  * @last_update:        Time of the last update.
 196  * @pstate:             Stores P state limits for this CPU
 197  * @vid:                Stores VID limits for this CPU
 198  * @last_sample_time:   Last Sample time
 199  * @aperf_mperf_shift:  APERF vs MPERF counting frequency difference
 200  * @prev_aperf:         Last APERF value read from APERF MSR
 201  * @prev_mperf:         Last MPERF value read from MPERF MSR
 202  * @prev_tsc:           Last timestamp counter (TSC) value
 203  * @prev_cummulative_iowait: IO Wait time difference from last and
 204  *                      current sample
 205  * @sample:             Storage for storing last Sample data
 206  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 207  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 208  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 209  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 210  * @epp_powersave:      Last saved HWP energy performance preference
 211  *                      (EPP) or energy performance bias (EPB),
 212  *                      when policy switched to performance
 213  * @epp_policy:         Last saved policy used to set EPP/EPB
 214  * @epp_default:        Power on default HWP energy performance
 215  *                      preference/bias
 216  * @epp_cached          Cached HWP energy-performance preference value
 217  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 218  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 219  * @last_io_update:     Last time when IO wake flag was set
 220  * @sched_flags:        Store scheduler flags for possible cross CPU update
 221  * @hwp_boost_min:      Last HWP boosted min performance
 222  * @suspended:          Whether or not the driver has been suspended.
 223  * @hwp_notify_work:    workqueue for HWP notifications.
 224  *
 225  * This structure stores per CPU instance data for all CPUs.
 226  */
 227 struct cpudata {
 228         int cpu;
 229
 230         unsigned int policy;
 231         struct update_util_data update_util;
 232         bool   update_util_set;
 233
 234         struct pstate_data pstate;
 235         struct vid_data vid;
 236
 237         u64     last_update;
 238         u64     last_sample_time;
 239         u64     aperf_mperf_shift;
 240         u64     prev_aperf;
 241         u64     prev_mperf;
 242         u64     prev_tsc;
 243         u64     prev_cummulative_iowait;
 244         struct sample sample;
 245         int32_t min_perf_ratio;
 246         int32_t max_perf_ratio;
 247 #ifdef CONFIG_ACPI
 248         struct acpi_processor_performance acpi_perf_data;
 249         bool valid_pss_table;
 250 #endif
 251         unsigned int iowait_boost;
 252         s16 epp_powersave;
 253         s16 epp_policy;
 254         s16 epp_default;
 255         s16 epp_cached;
 256         u64 hwp_req_cached;
 257         u64 hwp_cap_cached;
 258         u64 last_io_update;
 259         unsigned int sched_flags;
 260         u32 hwp_boost_min;
 261         bool suspended;
 262         struct delayed_work hwp_notify_work;
 263 };
 264
 265 static struct cpudata **all_cpu_data;
 266
 267 /**
 268  * struct pstate_funcs - Per CPU model specific callbacks
 269  * @get_max:            Callback to get maximum non turbo effective P state
 270  * @get_max_physical:   Callback to get maximum non turbo physical P state
 271  * @get_min:            Callback to get minimum P state
 272  * @get_turbo:          Callback to get turbo P state
 273  * @get_scaling:        Callback to get frequency scaling factor
 274  * @get_cpu_scaling:    Get frequency scaling factor for a given cpu
 275  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
 276  * @get_val:            Callback to convert P state to actual MSR write value
 277  * @get_vid:            Callback to get VID data for Atom platforms
 278  *
 279  * Core and Atom CPU models have different way to get P State limits. This
 280  * structure is used to store those callbacks.
 281  */
 282 struct pstate_funcs {
 283         int (*get_max)(void);
 284         int (*get_max_physical)(void);
 285         int (*get_min)(void);
 286         int (*get_turbo)(void);
 287         int (*get_scaling)(void);
 288         int (*get_cpu_scaling)(int cpu);
 289         int (*get_aperf_mperf_shift)(void);
 290         u64 (*get_val)(struct cpudata*, int pstate);
 291         void (*get_vid)(struct cpudata *);
 292 };
 293
 294 static struct pstate_funcs pstate_funcs __read_mostly;
 295
 296 static int hwp_active __read_mostly;
 297 static int hwp_mode_bdw __read_mostly;
 298 static bool per_cpu_limits __read_mostly;
 299 static bool hwp_boost __read_mostly;
 300
 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 302
 303 #ifdef CONFIG_ACPI
 304 static bool acpi_ppc;
 305 #endif
 306
 307 static struct global_params global;
 308
 309 static DEFINE_MUTEX(intel_pstate_driver_lock);
 310 static DEFINE_MUTEX(intel_pstate_limits_lock);
 311
 312 #ifdef CONFIG_ACPI
 313
 314 static bool intel_pstate_acpi_pm_profile_server(void)
 315 {
 316         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 317             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 318                 return true;
 319
 320         return false;
 321 }
 322
 323 static bool intel_pstate_get_ppc_enable_status(void)
 324 {
 325         if (intel_pstate_acpi_pm_profile_server())
 326                 return true;
 327
 328         return acpi_ppc;
 329 }
 330
 331 #ifdef CONFIG_ACPI_CPPC_LIB
 332
 333 /* The work item is needed to avoid CPU hotplug locking issues */
 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 335 {
 336         sched_set_itmt_support();
 337 }
 338
 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 340
 341 #define CPPC_MAX_PERF   U8_MAX
 342
 343 static void intel_pstate_set_itmt_prio(int cpu)
 344 {
 345         struct cppc_perf_caps cppc_perf;
 346         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 347         int ret;
 348
 349         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 350         if (ret)
 351                 return;
 352
 353         /*
 354          * On some systems with overclocking enabled, CPPC.highest_perf is hardcoded to 0xff.
 355          * In this case we can't use CPPC.highest_perf to enable ITMT.
 356          * In this case we can look at MSR_HWP_CAPABILITIES bits [8:0] to decide.
 357          */
 358         if (cppc_perf.highest_perf == CPPC_MAX_PERF)
 359                 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
 360
 361         /*
 362          * The priorities can be set regardless of whether or not
 363          * sched_set_itmt_support(true) has been called and it is valid to
 364          * update them at any time after it has been called.
 365          */
 366         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 367
 368         if (max_highest_perf <= min_highest_perf) {
 369                 if (cppc_perf.highest_perf > max_highest_perf)
 370                         max_highest_perf = cppc_perf.highest_perf;
 371
 372                 if (cppc_perf.highest_perf < min_highest_perf)
 373                         min_highest_perf = cppc_perf.highest_perf;
 374
 375                 if (max_highest_perf > min_highest_perf) {
 376                         /*
 377                          * This code can be run during CPU online under the
 378                          * CPU hotplug locks, so sched_set_itmt_support()
 379                          * cannot be called from here.  Queue up a work item
 380                          * to invoke it.
 381                          */
 382                         schedule_work(&sched_itmt_work);
 383                 }
 384         }
 385 }
 386
 387 static int intel_pstate_get_cppc_guaranteed(int cpu)
 388 {
 389         struct cppc_perf_caps cppc_perf;
 390         int ret;
 391
 392         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 393         if (ret)
 394                 return ret;
 395
 396         if (cppc_perf.guaranteed_perf)
 397                 return cppc_perf.guaranteed_perf;
 398
 399         return cppc_perf.nominal_perf;
 400 }
 401
 402 static u32 intel_pstate_cppc_nominal(int cpu)
 403 {
 404         u64 nominal_perf;
 405
 406         if (cppc_get_nominal_perf(cpu, &nominal_perf))
 407                 return 0;
 408
 409         return nominal_perf;
 410 }
 411 #else /* CONFIG_ACPI_CPPC_LIB */
 412 static inline void intel_pstate_set_itmt_prio(int cpu)
 413 {
 414 }
 415 #endif /* CONFIG_ACPI_CPPC_LIB */
 416
 417 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 418 {
 419         struct cpudata *cpu;
 420         int ret;
 421         int i;
 422
 423         if (hwp_active) {
 424                 intel_pstate_set_itmt_prio(policy->cpu);
 425                 return;
 426         }
 427
 428         if (!intel_pstate_get_ppc_enable_status())
 429                 return;
 430
 431         cpu = all_cpu_data[policy->cpu];
 432
 433         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 434                                                   policy->cpu);
 435         if (ret)
 436                 return;
 437
 438         /*
 439          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 440          * guarantee that the states returned by it map to the states in our
 441          * list directly.
 442          */
 443         if (cpu->acpi_perf_data.control_register.space_id !=
 444                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 445                 goto err;
 446
 447         /*
 448          * If there is only one entry _PSS, simply ignore _PSS and continue as
 449          * usual without taking _PSS into account
 450          */
 451         if (cpu->acpi_perf_data.state_count < 2)
 452                 goto err;
 453
 454         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 455         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 456                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 457                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 458                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 459                          (u32) cpu->acpi_perf_data.states[i].power,
 460                          (u32) cpu->acpi_perf_data.states[i].control);
 461         }
 462
 463         /*
 464          * The _PSS table doesn't contain whole turbo frequency range.
 465          * This just contains +1 MHZ above the max non turbo frequency,
 466          * with control value corresponding to max turbo ratio. But
 467          * when cpufreq set policy is called, it will call with this
 468          * max frequency, which will cause a reduced performance as
 469          * this driver uses real max turbo frequency as the max
 470          * frequency. So correct this frequency in _PSS table to
 471          * correct max turbo frequency based on the turbo state.
 472          * Also need to convert to MHz as _PSS freq is in MHz.
 473          */
 474         if (!global.turbo_disabled)
 475                 cpu->acpi_perf_data.states[0].core_frequency =
 476                                         policy->cpuinfo.max_freq / 1000;
 477         cpu->valid_pss_table = true;
 478         pr_debug("_PPC limits will be enforced\n");
 479
 480         return;
 481
 482  err:
 483         cpu->valid_pss_table = false;
 484         acpi_processor_unregister_performance(policy->cpu);
 485 }
 486
 487 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 488 {
 489         struct cpudata *cpu;
 490
 491         cpu = all_cpu_data[policy->cpu];
 492         if (!cpu->valid_pss_table)
 493                 return;
 494
 495         acpi_processor_unregister_performance(policy->cpu);
 496 }
 497 #else /* CONFIG_ACPI */
 498 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 499 {
 500 }
 501
 502 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 503 {
 504 }
 505
 506 static inline bool intel_pstate_acpi_pm_profile_server(void)
 507 {
 508         return false;
 509 }
 510 #endif /* CONFIG_ACPI */
 511
 512 #ifndef CONFIG_ACPI_CPPC_LIB
 513 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
 514 {
 515         return -ENOTSUPP;
 516 }
 517 #endif /* CONFIG_ACPI_CPPC_LIB */
 518
 519 /**
 520  * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
 521  * @cpu: Target CPU.
 522  *
 523  * On hybrid processors, HWP may expose more performance levels than there are
 524  * P-states accessible through the PERF_CTL interface.  If that happens, the
 525  * scaling factor between HWP performance levels and CPU frequency will be less
 526  * than the scaling factor between P-state values and CPU frequency.
 527  *
 528  * In that case, adjust the CPU parameters used in computations accordingly.
 529  */
 530 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
 531 {
 532         int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
 533         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 534         int perf_ctl_turbo = pstate_funcs.get_turbo();
 535         int turbo_freq = perf_ctl_turbo * perf_ctl_scaling;
 536         int scaling = cpu->pstate.scaling;
 537
 538         pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
 539         pr_debug("CPU%d: perf_ctl_max = %d\n", cpu->cpu, pstate_funcs.get_max());
 540         pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
 541         pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
 542         pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
 543         pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
 544         pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
 545
 546         /*
 547          * If the product of the HWP performance scaling factor and the HWP_CAP
 548          * highest performance is greater than the maximum turbo frequency
 549          * corresponding to the pstate_funcs.get_turbo() return value, the
 550          * scaling factor is too high, so recompute it to make the HWP_CAP
 551          * highest performance correspond to the maximum turbo frequency.
 552          */
 553         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
 554         if (turbo_freq < cpu->pstate.turbo_freq) {
 555                 cpu->pstate.turbo_freq = turbo_freq;
 556                 scaling = DIV_ROUND_UP(turbo_freq, cpu->pstate.turbo_pstate);
 557                 cpu->pstate.scaling = scaling;
 558
 559                 pr_debug("CPU%d: refined HWP-to-frequency scaling factor: %d\n",
 560                          cpu->cpu, scaling);
 561         }
 562
 563         cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
 564                                          perf_ctl_scaling);
 565
 566         cpu->pstate.max_pstate_physical =
 567                         DIV_ROUND_UP(perf_ctl_max_phys * perf_ctl_scaling,
 568                                      scaling);
 569
 570         cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
 571         /*
 572          * Cast the min P-state value retrieved via pstate_funcs.get_min() to
 573          * the effective range of HWP performance levels.
 574          */
 575         cpu->pstate.min_pstate = DIV_ROUND_UP(cpu->pstate.min_freq, scaling);
 576 }
 577
 578 static inline void update_turbo_state(void)
 579 {
 580         u64 misc_en;
 581         struct cpudata *cpu;
 582
 583         cpu = all_cpu_data[0];
 584         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 585         global.turbo_disabled =
 586                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 587                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 588 }
 589
 590 static int min_perf_pct_min(void)
 591 {
 592         struct cpudata *cpu = all_cpu_data[0];
 593         int turbo_pstate = cpu->pstate.turbo_pstate;
 594
 595         return turbo_pstate ?
 596                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 597 }
 598
 599 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 600 {
 601         u64 epb;
 602         int ret;
 603
 604         if (!boot_cpu_has(X86_FEATURE_EPB))
 605                 return -ENXIO;
 606
 607         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 608         if (ret)
 609                 return (s16)ret;
 610
 611         return (s16)(epb & 0x0f);
 612 }
 613
 614 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 615 {
 616         s16 epp;
 617
 618         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 619                 /*
 620                  * When hwp_req_data is 0, means that caller didn't read
 621                  * MSR_HWP_REQUEST, so need to read and get EPP.
 622                  */
 623                 if (!hwp_req_data) {
 624                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 625                                             &hwp_req_data);
 626                         if (epp)
 627                                 return epp;
 628                 }
 629                 epp = (hwp_req_data >> 24) & 0xff;
 630         } else {
 631                 /* When there is no EPP present, HWP uses EPB settings */
 632                 epp = intel_pstate_get_epb(cpu_data);
 633         }
 634
 635         return epp;
 636 }
 637
 638 static int intel_pstate_set_epb(int cpu, s16 pref)
 639 {
 640         u64 epb;
 641         int ret;
 642
 643         if (!boot_cpu_has(X86_FEATURE_EPB))
 644                 return -ENXIO;
 645
 646         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 647         if (ret)
 648                 return ret;
 649
 650         epb = (epb & ~0x0f) | pref;
 651         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 652
 653         return 0;
 654 }
 655
 656 /*
 657  * EPP/EPB display strings corresponding to EPP index in the
 658  * energy_perf_strings[]
 659  *      index           String
 660  *-------------------------------------
 661  *      0               default
 662  *      1               performance
 663  *      2               balance_performance
 664  *      3               balance_power
 665  *      4               power
 666  */
 667
 668 enum energy_perf_value_index {
 669         EPP_INDEX_DEFAULT = 0,
 670         EPP_INDEX_PERFORMANCE,
 671         EPP_INDEX_BALANCE_PERFORMANCE,
 672         EPP_INDEX_BALANCE_POWERSAVE,
 673         EPP_INDEX_POWERSAVE,
 674 };
 675
 676 static const char * const energy_perf_strings[] = {
 677         [EPP_INDEX_DEFAULT] = "default",
 678         [EPP_INDEX_PERFORMANCE] = "performance",
 679         [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
 680         [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
 681         [EPP_INDEX_POWERSAVE] = "power",
 682         NULL
 683 };
 684 static unsigned int epp_values[] = {
 685         [EPP_INDEX_DEFAULT] = 0, /* Unused index */
 686         [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
 687         [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
 688         [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
 689         [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
 690 };
 691
 692 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
 693 {
 694         s16 epp;
 695         int index = -EINVAL;
 696
 697         *raw_epp = 0;
 698         epp = intel_pstate_get_epp(cpu_data, 0);
 699         if (epp < 0)
 700                 return epp;
 701
 702         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 703                 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
 704                         return EPP_INDEX_PERFORMANCE;
 705                 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
 706                         return EPP_INDEX_BALANCE_PERFORMANCE;
 707                 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
 708                         return EPP_INDEX_BALANCE_POWERSAVE;
 709                 if (epp == epp_values[EPP_INDEX_POWERSAVE])
 710                         return EPP_INDEX_POWERSAVE;
 711                 *raw_epp = epp;
 712                 return 0;
 713         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 714                 /*
 715                  * Range:
 716                  *      0x00-0x03       :       Performance
 717                  *      0x04-0x07       :       Balance performance
 718                  *      0x08-0x0B       :       Balance power
 719                  *      0x0C-0x0F       :       Power
 720                  * The EPB is a 4 bit value, but our ranges restrict the
 721                  * value which can be set. Here only using top two bits
 722                  * effectively.
 723                  */
 724                 index = (epp >> 2) + 1;
 725         }
 726
 727         return index;
 728 }
 729
 730 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
 731 {
 732         int ret;
 733
 734         /*
 735          * Use the cached HWP Request MSR value, because in the active mode the
 736          * register itself may be updated by intel_pstate_hwp_boost_up() or
 737          * intel_pstate_hwp_boost_down() at any time.
 738          */
 739         u64 value = READ_ONCE(cpu->hwp_req_cached);
 740
 741         value &= ~GENMASK_ULL(31, 24);
 742         value |= (u64)epp << 24;
 743         /*
 744          * The only other updater of hwp_req_cached in the active mode,
 745          * intel_pstate_hwp_set(), is called under the same lock as this
 746          * function, so it cannot run in parallel with the update below.
 747          */
 748         WRITE_ONCE(cpu->hwp_req_cached, value);
 749         ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
 750         if (!ret)
 751                 cpu->epp_cached = epp;
 752
 753         return ret;
 754 }
 755
 756 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 757                                               int pref_index, bool use_raw,
 758                                               u32 raw_epp)
 759 {
 760         int epp = -EINVAL;
 761         int ret;
 762
 763         if (!pref_index)
 764                 epp = cpu_data->epp_default;
 765
 766         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 767                 if (use_raw)
 768                         epp = raw_epp;
 769                 else if (epp == -EINVAL)
 770                         epp = epp_values[pref_index];
 771
 772                 /*
 773                  * To avoid confusion, refuse to set EPP to any values different
 774                  * from 0 (performance) if the current policy is "performance",
 775                  * because those values would be overridden.
 776                  */
 777                 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 778                         return -EBUSY;
 779
 780                 ret = intel_pstate_set_epp(cpu_data, epp);
 781         } else {
 782                 if (epp == -EINVAL)
 783                         epp = (pref_index - 1) << 2;
 784                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 785         }
 786
 787         return ret;
 788 }
 789
 790 static ssize_t show_energy_performance_available_preferences(
 791                                 struct cpufreq_policy *policy, char *buf)
 792 {
 793         int i = 0;
 794         int ret = 0;
 795
 796         while (energy_perf_strings[i] != NULL)
 797                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 798
 799         ret += sprintf(&buf[ret], "\n");
 800
 801         return ret;
 802 }
 803
 804 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 805
 806 static struct cpufreq_driver intel_pstate;
 807
 808 static ssize_t store_energy_performance_preference(
 809                 struct cpufreq_policy *policy, const char *buf, size_t count)
 810 {
 811         struct cpudata *cpu = all_cpu_data[policy->cpu];
 812         char str_preference[21];
 813         bool raw = false;
 814         ssize_t ret;
 815         u32 epp = 0;
 816
 817         ret = sscanf(buf, "%20s", str_preference);
 818         if (ret != 1)
 819                 return -EINVAL;
 820
 821         ret = match_string(energy_perf_strings, -1, str_preference);
 822         if (ret < 0) {
 823                 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
 824                         return ret;
 825
 826                 ret = kstrtouint(buf, 10, &epp);
 827                 if (ret)
 828                         return ret;
 829
 830                 if (epp > 255)
 831                         return -EINVAL;
 832
 833                 raw = true;
 834         }
 835
 836         /*
 837          * This function runs with the policy R/W semaphore held, which
 838          * guarantees that the driver pointer will not change while it is
 839          * running.
 840          */
 841         if (!intel_pstate_driver)
 842                 return -EAGAIN;
 843
 844         mutex_lock(&intel_pstate_limits_lock);
 845
 846         if (intel_pstate_driver == &intel_pstate) {
 847                 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
 848         } else {
 849                 /*
 850                  * In the passive mode the governor needs to be stopped on the
 851                  * target CPU before the EPP update and restarted after it,
 852                  * which is super-heavy-weight, so make sure it is worth doing
 853                  * upfront.
 854                  */
 855                 if (!raw)
 856                         epp = ret ? epp_values[ret] : cpu->epp_default;
 857
 858                 if (cpu->epp_cached != epp) {
 859                         int err;
 860
 861                         cpufreq_stop_governor(policy);
 862                         ret = intel_pstate_set_epp(cpu, epp);
 863                         err = cpufreq_start_governor(policy);
 864                         if (!ret)
 865                                 ret = err;
 866                 }
 867         }
 868
 869         mutex_unlock(&intel_pstate_limits_lock);
 870
 871         return ret ?: count;
 872 }
 873
 874 static ssize_t show_energy_performance_preference(
 875                                 struct cpufreq_policy *policy, char *buf)
 876 {
 877         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 878         int preference, raw_epp;
 879
 880         preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
 881         if (preference < 0)
 882                 return preference;
 883
 884         if (raw_epp)
 885                 return  sprintf(buf, "%d\n", raw_epp);
 886         else
 887                 return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 888 }
 889
 890 cpufreq_freq_attr_rw(energy_performance_preference);
 891
 892 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 893 {
 894         struct cpudata *cpu = all_cpu_data[policy->cpu];
 895         int ratio, freq;
 896
 897         ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
 898         if (ratio <= 0) {
 899                 u64 cap;
 900
 901                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 902                 ratio = HWP_GUARANTEED_PERF(cap);
 903         }
 904
 905         freq = ratio * cpu->pstate.scaling;
 906         if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
 907                 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
 908
 909         return sprintf(buf, "%d\n", freq);
 910 }
 911
 912 cpufreq_freq_attr_ro(base_frequency);
 913
 914 static struct freq_attr *hwp_cpufreq_attrs[] = {
 915         &energy_performance_preference,
 916         &energy_performance_available_preferences,
 917         &base_frequency,
 918         NULL,
 919 };
 920
 921 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
 922 {
 923         u64 cap;
 924
 925         rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
 926         WRITE_ONCE(cpu->hwp_cap_cached, cap);
 927         cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
 928         cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
 929 }
 930
 931 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
 932 {
 933         int scaling = cpu->pstate.scaling;
 934
 935         __intel_pstate_get_hwp_cap(cpu);
 936
 937         cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
 938         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
 939         if (scaling != cpu->pstate.perf_ctl_scaling) {
 940                 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
 941
 942                 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
 943                                                  perf_ctl_scaling);
 944                 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
 945                                                    perf_ctl_scaling);
 946         }
 947 }
 948
 949 static void intel_pstate_hwp_set(unsigned int cpu)
 950 {
 951         struct cpudata *cpu_data = all_cpu_data[cpu];
 952         int max, min;
 953         u64 value;
 954         s16 epp;
 955
 956         max = cpu_data->max_perf_ratio;
 957         min = cpu_data->min_perf_ratio;
 958
 959         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 960                 min = max;
 961
 962         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 963
 964         value &= ~HWP_MIN_PERF(~0L);
 965         value |= HWP_MIN_PERF(min);
 966
 967         value &= ~HWP_MAX_PERF(~0L);
 968         value |= HWP_MAX_PERF(max);
 969
 970         if (cpu_data->epp_policy == cpu_data->policy)
 971                 goto skip_epp;
 972
 973         cpu_data->epp_policy = cpu_data->policy;
 974
 975         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 976                 epp = intel_pstate_get_epp(cpu_data, value);
 977                 cpu_data->epp_powersave = epp;
 978                 /* If EPP read was failed, then don't try to write */
 979                 if (epp < 0)
 980                         goto skip_epp;
 981
 982                 epp = 0;
 983         } else {
 984                 /* skip setting EPP, when saved value is invalid */
 985                 if (cpu_data->epp_powersave < 0)
 986                         goto skip_epp;
 987
 988                 /*
 989                  * No need to restore EPP when it is not zero. This
 990                  * means:
 991                  *  - Policy is not changed
 992                  *  - user has manually changed
 993                  *  - Error reading EPB
 994                  */
 995                 epp = intel_pstate_get_epp(cpu_data, value);
 996                 if (epp)
 997                         goto skip_epp;
 998
 999                 epp = cpu_data->epp_powersave;
1000         }
1001         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1002                 value &= ~GENMASK_ULL(31, 24);
1003                 value |= (u64)epp << 24;
1004         } else {
1005                 intel_pstate_set_epb(cpu, epp);
1006         }
1007 skip_epp:
1008         WRITE_ONCE(cpu_data->hwp_req_cached, value);
1009         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1010 }
1011
1012 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1013
1014 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1015 {
1016         u64 value = READ_ONCE(cpu->hwp_req_cached);
1017         int min_perf;
1018
1019         intel_pstate_disable_hwp_interrupt(cpu);
1020
1021         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1022                 /*
1023                  * In case the EPP has been set to "performance" by the
1024                  * active mode "performance" scaling algorithm, replace that
1025                  * temporary value with the cached EPP one.
1026                  */
1027                 value &= ~GENMASK_ULL(31, 24);
1028                 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1029                 /*
1030                  * However, make sure that EPP will be set to "performance" when
1031                  * the CPU is brought back online again and the "performance"
1032                  * scaling algorithm is still in effect.
1033                  */
1034                 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1035         }
1036
1037         /*
1038          * Clear the desired perf field in the cached HWP request value to
1039          * prevent nonzero desired values from being leaked into the active
1040          * mode.
1041          */
1042         value &= ~HWP_DESIRED_PERF(~0L);
1043         WRITE_ONCE(cpu->hwp_req_cached, value);
1044
1045         value &= ~GENMASK_ULL(31, 0);
1046         min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1047
1048         /* Set hwp_max = hwp_min */
1049         value |= HWP_MAX_PERF(min_perf);
1050         value |= HWP_MIN_PERF(min_perf);
1051
1052         /* Set EPP to min */
1053         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1054                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1055
1056         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1057 }
1058
1059 #define POWER_CTL_EE_ENABLE     1
1060 #define POWER_CTL_EE_DISABLE    2
1061
1062 static int power_ctl_ee_state;
1063
1064 static void set_power_ctl_ee_state(bool input)
1065 {
1066         u64 power_ctl;
1067
1068         mutex_lock(&intel_pstate_driver_lock);
1069         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1070         if (input) {
1071                 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1072                 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1073         } else {
1074                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1075                 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1076         }
1077         wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1078         mutex_unlock(&intel_pstate_driver_lock);
1079 }
1080
1081 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1082
1083 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1084 {
1085         intel_pstate_hwp_enable(cpu);
1086         wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1087 }
1088
1089 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1090 {
1091         struct cpudata *cpu = all_cpu_data[policy->cpu];
1092
1093         pr_debug("CPU %d suspending\n", cpu->cpu);
1094
1095         cpu->suspended = true;
1096
1097         /* disable HWP interrupt and cancel any pending work */
1098         intel_pstate_disable_hwp_interrupt(cpu);
1099
1100         return 0;
1101 }
1102
1103 static int intel_pstate_resume(struct cpufreq_policy *policy)
1104 {
1105         struct cpudata *cpu = all_cpu_data[policy->cpu];
1106
1107         pr_debug("CPU %d resuming\n", cpu->cpu);
1108
1109         /* Only restore if the system default is changed */
1110         if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1111                 set_power_ctl_ee_state(true);
1112         else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1113                 set_power_ctl_ee_state(false);
1114
1115         if (cpu->suspended && hwp_active) {
1116                 mutex_lock(&intel_pstate_limits_lock);
1117
1118                 /* Re-enable HWP, because "online" has not done that. */
1119                 intel_pstate_hwp_reenable(cpu);
1120
1121                 mutex_unlock(&intel_pstate_limits_lock);
1122         }
1123
1124         cpu->suspended = false;
1125
1126         return 0;
1127 }
1128
1129 static void intel_pstate_update_policies(void)
1130 {
1131         int cpu;
1132
1133         for_each_possible_cpu(cpu)
1134                 cpufreq_update_policy(cpu);
1135 }
1136
1137 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1138                                            struct cpufreq_policy *policy)
1139 {
1140         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1141                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1142         refresh_frequency_limits(policy);
1143 }
1144
1145 static void intel_pstate_update_max_freq(unsigned int cpu)
1146 {
1147         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1148
1149         if (!policy)
1150                 return;
1151
1152         __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1153
1154         cpufreq_cpu_release(policy);
1155 }
1156
1157 static void intel_pstate_update_limits(unsigned int cpu)
1158 {
1159         mutex_lock(&intel_pstate_driver_lock);
1160
1161         update_turbo_state();
1162         /*
1163          * If turbo has been turned on or off globally, policy limits for
1164          * all CPUs need to be updated to reflect that.
1165          */
1166         if (global.turbo_disabled_mf != global.turbo_disabled) {
1167                 global.turbo_disabled_mf = global.turbo_disabled;
1168                 arch_set_max_freq_ratio(global.turbo_disabled);
1169                 for_each_possible_cpu(cpu)
1170                         intel_pstate_update_max_freq(cpu);
1171         } else {
1172                 cpufreq_update_policy(cpu);
1173         }
1174
1175         mutex_unlock(&intel_pstate_driver_lock);
1176 }
1177
1178 /************************** sysfs begin ************************/
1179 #define show_one(file_name, object)                                     \
1180         static ssize_t show_##file_name                                 \
1181         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
1182         {                                                               \
1183                 return sprintf(buf, "%u\n", global.object);             \
1184         }
1185
1186 static ssize_t intel_pstate_show_status(char *buf);
1187 static int intel_pstate_update_status(const char *buf, size_t size);
1188
1189 static ssize_t show_status(struct kobject *kobj,
1190                            struct kobj_attribute *attr, char *buf)
1191 {
1192         ssize_t ret;
1193
1194         mutex_lock(&intel_pstate_driver_lock);
1195         ret = intel_pstate_show_status(buf);
1196         mutex_unlock(&intel_pstate_driver_lock);
1197
1198         return ret;
1199 }
1200
1201 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1202                             const char *buf, size_t count)
1203 {
1204         char *p = memchr(buf, '\n', count);
1205         int ret;
1206
1207         mutex_lock(&intel_pstate_driver_lock);
1208         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1209         mutex_unlock(&intel_pstate_driver_lock);
1210
1211         return ret < 0 ? ret : count;
1212 }
1213
1214 static ssize_t show_turbo_pct(struct kobject *kobj,
1215                                 struct kobj_attribute *attr, char *buf)
1216 {
1217         struct cpudata *cpu;
1218         int total, no_turbo, turbo_pct;
1219         uint32_t turbo_fp;
1220
1221         mutex_lock(&intel_pstate_driver_lock);
1222
1223         if (!intel_pstate_driver) {
1224                 mutex_unlock(&intel_pstate_driver_lock);
1225                 return -EAGAIN;
1226         }
1227
1228         cpu = all_cpu_data[0];
1229
1230         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1231         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1232         turbo_fp = div_fp(no_turbo, total);
1233         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1234
1235         mutex_unlock(&intel_pstate_driver_lock);
1236
1237         return sprintf(buf, "%u\n", turbo_pct);
1238 }
1239
1240 static ssize_t show_num_pstates(struct kobject *kobj,
1241                                 struct kobj_attribute *attr, char *buf)
1242 {
1243         struct cpudata *cpu;
1244         int total;
1245
1246         mutex_lock(&intel_pstate_driver_lock);
1247
1248         if (!intel_pstate_driver) {
1249                 mutex_unlock(&intel_pstate_driver_lock);
1250                 return -EAGAIN;
1251         }
1252
1253         cpu = all_cpu_data[0];
1254         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1255
1256         mutex_unlock(&intel_pstate_driver_lock);
1257
1258         return sprintf(buf, "%u\n", total);
1259 }
1260
1261 static ssize_t show_no_turbo(struct kobject *kobj,
1262                              struct kobj_attribute *attr, char *buf)
1263 {
1264         ssize_t ret;
1265
1266         mutex_lock(&intel_pstate_driver_lock);
1267
1268         if (!intel_pstate_driver) {
1269                 mutex_unlock(&intel_pstate_driver_lock);
1270                 return -EAGAIN;
1271         }
1272
1273         update_turbo_state();
1274         if (global.turbo_disabled)
1275                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1276         else
1277                 ret = sprintf(buf, "%u\n", global.no_turbo);
1278
1279         mutex_unlock(&intel_pstate_driver_lock);
1280
1281         return ret;
1282 }
1283
1284 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1285                               const char *buf, size_t count)
1286 {
1287         unsigned int input;
1288         int ret;
1289
1290         ret = sscanf(buf, "%u", &input);
1291         if (ret != 1)
1292                 return -EINVAL;
1293
1294         mutex_lock(&intel_pstate_driver_lock);
1295
1296         if (!intel_pstate_driver) {
1297                 mutex_unlock(&intel_pstate_driver_lock);
1298                 return -EAGAIN;
1299         }
1300
1301         mutex_lock(&intel_pstate_limits_lock);
1302
1303         update_turbo_state();
1304         if (global.turbo_disabled) {
1305                 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1306                 mutex_unlock(&intel_pstate_limits_lock);
1307                 mutex_unlock(&intel_pstate_driver_lock);
1308                 return -EPERM;
1309         }
1310
1311         global.no_turbo = clamp_t(int, input, 0, 1);
1312
1313         if (global.no_turbo) {
1314                 struct cpudata *cpu = all_cpu_data[0];
1315                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1316
1317                 /* Squash the global minimum into the permitted range. */
1318                 if (global.min_perf_pct > pct)
1319                         global.min_perf_pct = pct;
1320         }
1321
1322         mutex_unlock(&intel_pstate_limits_lock);
1323
1324         intel_pstate_update_policies();
1325
1326         mutex_unlock(&intel_pstate_driver_lock);
1327
1328         return count;
1329 }
1330
1331 static void update_qos_request(enum freq_qos_req_type type)
1332 {
1333         struct freq_qos_request *req;
1334         struct cpufreq_policy *policy;
1335         int i;
1336
1337         for_each_possible_cpu(i) {
1338                 struct cpudata *cpu = all_cpu_data[i];
1339                 unsigned int freq, perf_pct;
1340
1341                 policy = cpufreq_cpu_get(i);
1342                 if (!policy)
1343                         continue;
1344
1345                 req = policy->driver_data;
1346                 cpufreq_cpu_put(policy);
1347
1348                 if (!req)
1349                         continue;
1350
1351                 if (hwp_active)
1352                         intel_pstate_get_hwp_cap(cpu);
1353
1354                 if (type == FREQ_QOS_MIN) {
1355                         perf_pct = global.min_perf_pct;
1356                 } else {
1357                         req++;
1358                         perf_pct = global.max_perf_pct;
1359                 }
1360
1361                 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1362
1363                 if (freq_qos_update_request(req, freq) < 0)
1364                         pr_warn("Failed to update freq constraint: CPU%d\n", i);
1365         }
1366 }
1367
1368 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1369                                   const char *buf, size_t count)
1370 {
1371         unsigned int input;
1372         int ret;
1373
1374         ret = sscanf(buf, "%u", &input);
1375         if (ret != 1)
1376                 return -EINVAL;
1377
1378         mutex_lock(&intel_pstate_driver_lock);
1379
1380         if (!intel_pstate_driver) {
1381                 mutex_unlock(&intel_pstate_driver_lock);
1382                 return -EAGAIN;
1383         }
1384
1385         mutex_lock(&intel_pstate_limits_lock);
1386
1387         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1388
1389         mutex_unlock(&intel_pstate_limits_lock);
1390
1391         if (intel_pstate_driver == &intel_pstate)
1392                 intel_pstate_update_policies();
1393         else
1394                 update_qos_request(FREQ_QOS_MAX);
1395
1396         mutex_unlock(&intel_pstate_driver_lock);
1397
1398         return count;
1399 }
1400
1401 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1402                                   const char *buf, size_t count)
1403 {
1404         unsigned int input;
1405         int ret;
1406
1407         ret = sscanf(buf, "%u", &input);
1408         if (ret != 1)
1409                 return -EINVAL;
1410
1411         mutex_lock(&intel_pstate_driver_lock);
1412
1413         if (!intel_pstate_driver) {
1414                 mutex_unlock(&intel_pstate_driver_lock);
1415                 return -EAGAIN;
1416         }
1417
1418         mutex_lock(&intel_pstate_limits_lock);
1419
1420         global.min_perf_pct = clamp_t(int, input,
1421                                       min_perf_pct_min(), global.max_perf_pct);
1422
1423         mutex_unlock(&intel_pstate_limits_lock);
1424
1425         if (intel_pstate_driver == &intel_pstate)
1426                 intel_pstate_update_policies();
1427         else
1428                 update_qos_request(FREQ_QOS_MIN);
1429
1430         mutex_unlock(&intel_pstate_driver_lock);
1431
1432         return count;
1433 }
1434
1435 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1436                                 struct kobj_attribute *attr, char *buf)
1437 {
1438         return sprintf(buf, "%u\n", hwp_boost);
1439 }
1440
1441 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1442                                        struct kobj_attribute *b,
1443                                        const char *buf, size_t count)
1444 {
1445         unsigned int input;
1446         int ret;
1447
1448         ret = kstrtouint(buf, 10, &input);
1449         if (ret)
1450                 return ret;
1451
1452         mutex_lock(&intel_pstate_driver_lock);
1453         hwp_boost = !!input;
1454         intel_pstate_update_policies();
1455         mutex_unlock(&intel_pstate_driver_lock);
1456
1457         return count;
1458 }
1459
1460 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1461                                       char *buf)
1462 {
1463         u64 power_ctl;
1464         int enable;
1465
1466         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1467         enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1468         return sprintf(buf, "%d\n", !enable);
1469 }
1470
1471 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1472                                        const char *buf, size_t count)
1473 {
1474         bool input;
1475         int ret;
1476
1477         ret = kstrtobool(buf, &input);
1478         if (ret)
1479                 return ret;
1480
1481         set_power_ctl_ee_state(input);
1482
1483         return count;
1484 }
1485
1486 show_one(max_perf_pct, max_perf_pct);
1487 show_one(min_perf_pct, min_perf_pct);
1488
1489 define_one_global_rw(status);
1490 define_one_global_rw(no_turbo);
1491 define_one_global_rw(max_perf_pct);
1492 define_one_global_rw(min_perf_pct);
1493 define_one_global_ro(turbo_pct);
1494 define_one_global_ro(num_pstates);
1495 define_one_global_rw(hwp_dynamic_boost);
1496 define_one_global_rw(energy_efficiency);
1497
1498 static struct attribute *intel_pstate_attributes[] = {
1499         &status.attr,
1500         &no_turbo.attr,
1501         NULL
1502 };
1503
1504 static const struct attribute_group intel_pstate_attr_group = {
1505         .attrs = intel_pstate_attributes,
1506 };
1507
1508 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1509
1510 static struct kobject *intel_pstate_kobject;
1511
1512 static void __init intel_pstate_sysfs_expose_params(void)
1513 {
1514         int rc;
1515
1516         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1517                                                 &cpu_subsys.dev_root->kobj);
1518         if (WARN_ON(!intel_pstate_kobject))
1519                 return;
1520
1521         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1522         if (WARN_ON(rc))
1523                 return;
1524
1525         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1526                 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1527                 WARN_ON(rc);
1528
1529                 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1530                 WARN_ON(rc);
1531         }
1532
1533         /*
1534          * If per cpu limits are enforced there are no global limits, so
1535          * return without creating max/min_perf_pct attributes
1536          */
1537         if (per_cpu_limits)
1538                 return;
1539
1540         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1541         WARN_ON(rc);
1542
1543         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1544         WARN_ON(rc);
1545
1546         if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1547                 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1548                 WARN_ON(rc);
1549         }
1550 }
1551
1552 static void __init intel_pstate_sysfs_remove(void)
1553 {
1554         if (!intel_pstate_kobject)
1555                 return;
1556
1557         sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1558
1559         if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1560                 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1561                 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1562         }
1563
1564         if (!per_cpu_limits) {
1565                 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1566                 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1567
1568                 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1569                         sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1570         }
1571
1572         kobject_put(intel_pstate_kobject);
1573 }
1574
1575 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1576 {
1577         int rc;
1578
1579         if (!hwp_active)
1580                 return;
1581
1582         rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1583         WARN_ON_ONCE(rc);
1584 }
1585
1586 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1587 {
1588         if (!hwp_active)
1589                 return;
1590
1591         sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1592 }
1593
1594 /************************** sysfs end ************************/
1595
1596 static void intel_pstate_notify_work(struct work_struct *work)
1597 {
1598         struct cpudata *cpudata =
1599                 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1600         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1601
1602         if (policy) {
1603                 intel_pstate_get_hwp_cap(cpudata);
1604                 __intel_pstate_update_max_freq(cpudata, policy);
1605
1606                 cpufreq_cpu_release(policy);
1607         }
1608
1609         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1610 }
1611
1612 static DEFINE_SPINLOCK(hwp_notify_lock);
1613 static cpumask_t hwp_intr_enable_mask;
1614
1615 void notify_hwp_interrupt(void)
1616 {
1617         unsigned int this_cpu = smp_processor_id();
1618         struct cpudata *cpudata;
1619         unsigned long flags;
1620         u64 value;
1621
1622         if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1623                 return;
1624
1625         rdmsrl_safe(MSR_HWP_STATUS, &value);
1626         if (!(value & 0x01))
1627                 return;
1628
1629         spin_lock_irqsave(&hwp_notify_lock, flags);
1630
1631         if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1632                 goto ack_intr;
1633
1634         /*
1635          * Currently we never free all_cpu_data. And we can't reach here
1636          * without this allocated. But for safety for future changes, added
1637          * check.
1638          */
1639         if (unlikely(!READ_ONCE(all_cpu_data)))
1640                 goto ack_intr;
1641
1642         /*
1643          * The free is done during cleanup, when cpufreq registry is failed.
1644          * We wouldn't be here if it fails on init or switch status. But for
1645          * future changes, added check.
1646          */
1647         cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1648         if (unlikely(!cpudata))
1649                 goto ack_intr;
1650
1651         schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1652
1653         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1654
1655         return;
1656
1657 ack_intr:
1658         wrmsrl_safe(MSR_HWP_STATUS, 0);
1659         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1660 }
1661
1662 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1663 {
1664         unsigned long flags;
1665
1666         if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1667                 return;
1668
1669         /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1670         wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1671
1672         spin_lock_irqsave(&hwp_notify_lock, flags);
1673         if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1674                 cancel_delayed_work(&cpudata->hwp_notify_work);
1675         spin_unlock_irqrestore(&hwp_notify_lock, flags);
1676 }
1677
1678 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1679 {
1680         /* Enable HWP notification interrupt for guaranteed performance change */
1681         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1682                 unsigned long flags;
1683
1684                 spin_lock_irqsave(&hwp_notify_lock, flags);
1685                 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1686                 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1687                 spin_unlock_irqrestore(&hwp_notify_lock, flags);
1688
1689                 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1690                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1691                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1692         }
1693 }
1694
1695 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1696 {
1697         cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1698
1699         /*
1700          * If this CPU gen doesn't call for change in balance_perf
1701          * EPP return.
1702          */
1703         if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1704                 return;
1705
1706         /*
1707          * If powerup EPP is something other than chipset default 0x80 and
1708          * - is more performance oriented than 0x80 (default balance_perf EPP)
1709          * - But less performance oriented than performance EPP
1710          *   then use this as new balance_perf EPP.
1711          */
1712         if (cpudata->epp_default < HWP_EPP_BALANCE_PERFORMANCE &&
1713             cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1714                 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1715                 return;
1716         }
1717
1718         /*
1719          * Use hard coded value per gen to update the balance_perf
1720          * and default EPP.
1721          */
1722         cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1723         intel_pstate_set_epp(cpudata, cpudata->epp_default);
1724 }
1725
1726 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1727 {
1728         /* First disable HWP notification interrupt till we activate again */
1729         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1730                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1731
1732         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1733
1734         intel_pstate_enable_hwp_interrupt(cpudata);
1735
1736         if (cpudata->epp_default >= 0)
1737                 return;
1738
1739         intel_pstate_update_epp_defaults(cpudata);
1740 }
1741
1742 static int atom_get_min_pstate(void)
1743 {
1744         u64 value;
1745
1746         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1747         return (value >> 8) & 0x7F;
1748 }
1749
1750 static int atom_get_max_pstate(void)
1751 {
1752         u64 value;
1753
1754         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1755         return (value >> 16) & 0x7F;
1756 }
1757
1758 static int atom_get_turbo_pstate(void)
1759 {
1760         u64 value;
1761
1762         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1763         return value & 0x7F;
1764 }
1765
1766 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1767 {
1768         u64 val;
1769         int32_t vid_fp;
1770         u32 vid;
1771
1772         val = (u64)pstate << 8;
1773         if (global.no_turbo && !global.turbo_disabled)
1774                 val |= (u64)1 << 32;
1775
1776         vid_fp = cpudata->vid.min + mul_fp(
1777                 int_tofp(pstate - cpudata->pstate.min_pstate),
1778                 cpudata->vid.ratio);
1779
1780         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1781         vid = ceiling_fp(vid_fp);
1782
1783         if (pstate > cpudata->pstate.max_pstate)
1784                 vid = cpudata->vid.turbo;
1785
1786         return val | vid;
1787 }
1788
1789 static int silvermont_get_scaling(void)
1790 {
1791         u64 value;
1792         int i;
1793         /* Defined in Table 35-6 from SDM (Sept 2015) */
1794         static int silvermont_freq_table[] = {
1795                 83300, 100000, 133300, 116700, 80000};
1796
1797         rdmsrl(MSR_FSB_FREQ, value);
1798         i = value & 0x7;
1799         WARN_ON(i > 4);
1800
1801         return silvermont_freq_table[i];
1802 }
1803
1804 static int airmont_get_scaling(void)
1805 {
1806         u64 value;
1807         int i;
1808         /* Defined in Table 35-10 from SDM (Sept 2015) */
1809         static int airmont_freq_table[] = {
1810                 83300, 100000, 133300, 116700, 80000,
1811                 93300, 90000, 88900, 87500};
1812
1813         rdmsrl(MSR_FSB_FREQ, value);
1814         i = value & 0xF;
1815         WARN_ON(i > 8);
1816
1817         return airmont_freq_table[i];
1818 }
1819
1820 static void atom_get_vid(struct cpudata *cpudata)
1821 {
1822         u64 value;
1823
1824         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1825         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1826         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1827         cpudata->vid.ratio = div_fp(
1828                 cpudata->vid.max - cpudata->vid.min,
1829                 int_tofp(cpudata->pstate.max_pstate -
1830                         cpudata->pstate.min_pstate));
1831
1832         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1833         cpudata->vid.turbo = value & 0x7f;
1834 }
1835
1836 static int core_get_min_pstate(void)
1837 {
1838         u64 value;
1839
1840         rdmsrl(MSR_PLATFORM_INFO, value);
1841         return (value >> 40) & 0xFF;
1842 }
1843
1844 static int core_get_max_pstate_physical(void)
1845 {
1846         u64 value;
1847
1848         rdmsrl(MSR_PLATFORM_INFO, value);
1849         return (value >> 8) & 0xFF;
1850 }
1851
1852 static int core_get_tdp_ratio(u64 plat_info)
1853 {
1854         /* Check how many TDP levels present */
1855         if (plat_info & 0x600000000) {
1856                 u64 tdp_ctrl;
1857                 u64 tdp_ratio;
1858                 int tdp_msr;
1859                 int err;
1860
1861                 /* Get the TDP level (0, 1, 2) to get ratios */
1862                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1863                 if (err)
1864                         return err;
1865
1866                 /* TDP MSR are continuous starting at 0x648 */
1867                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1868                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1869                 if (err)
1870                         return err;
1871
1872                 /* For level 1 and 2, bits[23:16] contain the ratio */
1873                 if (tdp_ctrl & 0x03)
1874                         tdp_ratio >>= 16;
1875
1876                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1877                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1878
1879                 return (int)tdp_ratio;
1880         }
1881
1882         return -ENXIO;
1883 }
1884
1885 static int core_get_max_pstate(void)
1886 {
1887         u64 tar;
1888         u64 plat_info;
1889         int max_pstate;
1890         int tdp_ratio;
1891         int err;
1892
1893         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1894         max_pstate = (plat_info >> 8) & 0xFF;
1895
1896         tdp_ratio = core_get_tdp_ratio(plat_info);
1897         if (tdp_ratio <= 0)
1898                 return max_pstate;
1899
1900         if (hwp_active) {
1901                 /* Turbo activation ratio is not used on HWP platforms */
1902                 return tdp_ratio;
1903         }
1904
1905         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1906         if (!err) {
1907                 int tar_levels;
1908
1909                 /* Do some sanity checking for safety */
1910                 tar_levels = tar & 0xff;
1911                 if (tdp_ratio - 1 == tar_levels) {
1912                         max_pstate = tar_levels;
1913                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1914                 }
1915         }
1916
1917         return max_pstate;
1918 }
1919
1920 static int core_get_turbo_pstate(void)
1921 {
1922         u64 value;
1923         int nont, ret;
1924
1925         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1926         nont = core_get_max_pstate();
1927         ret = (value) & 255;
1928         if (ret <= nont)
1929                 ret = nont;
1930         return ret;
1931 }
1932
1933 static inline int core_get_scaling(void)
1934 {
1935         return 100000;
1936 }
1937
1938 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1939 {
1940         u64 val;
1941
1942         val = (u64)pstate << 8;
1943         if (global.no_turbo && !global.turbo_disabled)
1944                 val |= (u64)1 << 32;
1945
1946         return val;
1947 }
1948
1949 static int knl_get_aperf_mperf_shift(void)
1950 {
1951         return 10;
1952 }
1953
1954 static int knl_get_turbo_pstate(void)
1955 {
1956         u64 value;
1957         int nont, ret;
1958
1959         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1960         nont = core_get_max_pstate();
1961         ret = (((value) >> 8) & 0xFF);
1962         if (ret <= nont)
1963                 ret = nont;
1964         return ret;
1965 }
1966
1967 #ifdef CONFIG_ACPI_CPPC_LIB
1968 static u32 hybrid_ref_perf;
1969
1970 static int hybrid_get_cpu_scaling(int cpu)
1971 {
1972         return DIV_ROUND_UP(core_get_scaling() * hybrid_ref_perf,
1973                             intel_pstate_cppc_nominal(cpu));
1974 }
1975
1976 static void intel_pstate_cppc_set_cpu_scaling(void)
1977 {
1978         u32 min_nominal_perf = U32_MAX;
1979         int cpu;
1980
1981         for_each_present_cpu(cpu) {
1982                 u32 nominal_perf = intel_pstate_cppc_nominal(cpu);
1983
1984                 if (nominal_perf && nominal_perf < min_nominal_perf)
1985                         min_nominal_perf = nominal_perf;
1986         }
1987
1988         if (min_nominal_perf < U32_MAX) {
1989                 hybrid_ref_perf = min_nominal_perf;
1990                 pstate_funcs.get_cpu_scaling = hybrid_get_cpu_scaling;
1991         }
1992 }
1993 #else
1994 static inline void intel_pstate_cppc_set_cpu_scaling(void)
1995 {
1996 }
1997 #endif /* CONFIG_ACPI_CPPC_LIB */
1998
1999 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2000 {
2001         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2002         cpu->pstate.current_pstate = pstate;
2003         /*
2004          * Generally, there is no guarantee that this code will always run on
2005          * the CPU being updated, so force the register update to run on the
2006          * right CPU.
2007          */
2008         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2009                       pstate_funcs.get_val(cpu, pstate));
2010 }
2011
2012 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2013 {
2014         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2015 }
2016
2017 static void intel_pstate_max_within_limits(struct cpudata *cpu)
2018 {
2019         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2020
2021         update_turbo_state();
2022         intel_pstate_set_pstate(cpu, pstate);
2023 }
2024
2025 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2026 {
2027         int perf_ctl_max_phys = pstate_funcs.get_max_physical();
2028         int perf_ctl_scaling = pstate_funcs.get_scaling();
2029
2030         cpu->pstate.min_pstate = pstate_funcs.get_min();
2031         cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2032         cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2033
2034         if (hwp_active && !hwp_mode_bdw) {
2035                 __intel_pstate_get_hwp_cap(cpu);
2036
2037                 if (pstate_funcs.get_cpu_scaling) {
2038                         cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2039                         if (cpu->pstate.scaling != perf_ctl_scaling)
2040                                 intel_pstate_hybrid_hwp_adjust(cpu);
2041                 } else {
2042                         cpu->pstate.scaling = perf_ctl_scaling;
2043                 }
2044         } else {
2045                 cpu->pstate.scaling = perf_ctl_scaling;
2046                 cpu->pstate.max_pstate = pstate_funcs.get_max();
2047                 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
2048         }
2049
2050         if (cpu->pstate.scaling == perf_ctl_scaling) {
2051                 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2052                 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2053                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2054         }
2055
2056         if (pstate_funcs.get_aperf_mperf_shift)
2057                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2058
2059         if (pstate_funcs.get_vid)
2060                 pstate_funcs.get_vid(cpu);
2061
2062         intel_pstate_set_min_pstate(cpu);
2063 }
2064
2065 /*
2066  * Long hold time will keep high perf limits for long time,
2067  * which negatively impacts perf/watt for some workloads,
2068  * like specpower. 3ms is based on experiements on some
2069  * workoads.
2070  */
2071 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2072
2073 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2074 {
2075         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2076         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2077         u32 max_limit = (hwp_req & 0xff00) >> 8;
2078         u32 min_limit = (hwp_req & 0xff);
2079         u32 boost_level1;
2080
2081         /*
2082          * Cases to consider (User changes via sysfs or boot time):
2083          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2084          *      No boost, return.
2085          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2086          *     Should result in one level boost only for P0.
2087          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2088          *     Should result in two level boost:
2089          *         (min + p1)/2 and P1.
2090          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2091          *     Should result in three level boost:
2092          *        (min + p1)/2, P1 and P0.
2093          */
2094
2095         /* If max and min are equal or already at max, nothing to boost */
2096         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2097                 return;
2098
2099         if (!cpu->hwp_boost_min)
2100                 cpu->hwp_boost_min = min_limit;
2101
2102         /* level at half way mark between min and guranteed */
2103         boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2104
2105         if (cpu->hwp_boost_min < boost_level1)
2106                 cpu->hwp_boost_min = boost_level1;
2107         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2108                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2109         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2110                  max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2111                 cpu->hwp_boost_min = max_limit;
2112         else
2113                 return;
2114
2115         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2116         wrmsrl(MSR_HWP_REQUEST, hwp_req);
2117         cpu->last_update = cpu->sample.time;
2118 }
2119
2120 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2121 {
2122         if (cpu->hwp_boost_min) {
2123                 bool expired;
2124
2125                 /* Check if we are idle for hold time to boost down */
2126                 expired = time_after64(cpu->sample.time, cpu->last_update +
2127                                        hwp_boost_hold_time_ns);
2128                 if (expired) {
2129                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2130                         cpu->hwp_boost_min = 0;
2131                 }
2132         }
2133         cpu->last_update = cpu->sample.time;
2134 }
2135
2136 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2137                                                       u64 time)
2138 {
2139         cpu->sample.time = time;
2140
2141         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2142                 bool do_io = false;
2143
2144                 cpu->sched_flags = 0;
2145                 /*
2146                  * Set iowait_boost flag and update time. Since IO WAIT flag
2147                  * is set all the time, we can't just conclude that there is
2148                  * some IO bound activity is scheduled on this CPU with just
2149                  * one occurrence. If we receive at least two in two
2150                  * consecutive ticks, then we treat as boost candidate.
2151                  */
2152                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2153                         do_io = true;
2154
2155                 cpu->last_io_update = time;
2156
2157                 if (do_io)
2158                         intel_pstate_hwp_boost_up(cpu);
2159
2160         } else {
2161                 intel_pstate_hwp_boost_down(cpu);
2162         }
2163 }
2164
2165 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2166                                                 u64 time, unsigned int flags)
2167 {
2168         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2169
2170         cpu->sched_flags |= flags;
2171
2172         if (smp_processor_id() == cpu->cpu)
2173                 intel_pstate_update_util_hwp_local(cpu, time);
2174 }
2175
2176 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2177 {
2178         struct sample *sample = &cpu->sample;
2179
2180         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2181 }
2182
2183 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2184 {
2185         u64 aperf, mperf;
2186         unsigned long flags;
2187         u64 tsc;
2188
2189         local_irq_save(flags);
2190         rdmsrl(MSR_IA32_APERF, aperf);
2191         rdmsrl(MSR_IA32_MPERF, mperf);
2192         tsc = rdtsc();
2193         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2194                 local_irq_restore(flags);
2195                 return false;
2196         }
2197         local_irq_restore(flags);
2198
2199         cpu->last_sample_time = cpu->sample.time;
2200         cpu->sample.time = time;
2201         cpu->sample.aperf = aperf;
2202         cpu->sample.mperf = mperf;
2203         cpu->sample.tsc =  tsc;
2204         cpu->sample.aperf -= cpu->prev_aperf;
2205         cpu->sample.mperf -= cpu->prev_mperf;
2206         cpu->sample.tsc -= cpu->prev_tsc;
2207
2208         cpu->prev_aperf = aperf;
2209         cpu->prev_mperf = mperf;
2210         cpu->prev_tsc = tsc;
2211         /*
2212          * First time this function is invoked in a given cycle, all of the
2213          * previous sample data fields are equal to zero or stale and they must
2214          * be populated with meaningful numbers for things to work, so assume
2215          * that sample.time will always be reset before setting the utilization
2216          * update hook and make the caller skip the sample then.
2217          */
2218         if (cpu->last_sample_time) {
2219                 intel_pstate_calc_avg_perf(cpu);
2220                 return true;
2221         }
2222         return false;
2223 }
2224
2225 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2226 {
2227         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2228 }
2229
2230 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2231 {
2232         return mul_ext_fp(cpu->pstate.max_pstate_physical,
2233                           cpu->sample.core_avg_perf);
2234 }
2235
2236 static inline int32_t get_target_pstate(struct cpudata *cpu)
2237 {
2238         struct sample *sample = &cpu->sample;
2239         int32_t busy_frac;
2240         int target, avg_pstate;
2241
2242         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2243                            sample->tsc);
2244
2245         if (busy_frac < cpu->iowait_boost)
2246                 busy_frac = cpu->iowait_boost;
2247
2248         sample->busy_scaled = busy_frac * 100;
2249
2250         target = global.no_turbo || global.turbo_disabled ?
2251                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2252         target += target >> 2;
2253         target = mul_fp(target, busy_frac);
2254         if (target < cpu->pstate.min_pstate)
2255                 target = cpu->pstate.min_pstate;
2256
2257         /*
2258          * If the average P-state during the previous cycle was higher than the
2259          * current target, add 50% of the difference to the target to reduce
2260          * possible performance oscillations and offset possible performance
2261          * loss related to moving the workload from one CPU to another within
2262          * a package/module.
2263          */
2264         avg_pstate = get_avg_pstate(cpu);
2265         if (avg_pstate > target)
2266                 target += (avg_pstate - target) >> 1;
2267
2268         return target;
2269 }
2270
2271 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2272 {
2273         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2274         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2275
2276         return clamp_t(int, pstate, min_pstate, max_pstate);
2277 }
2278
2279 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2280 {
2281         if (pstate == cpu->pstate.current_pstate)
2282                 return;
2283
2284         cpu->pstate.current_pstate = pstate;
2285         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2286 }
2287
2288 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2289 {
2290         int from = cpu->pstate.current_pstate;
2291         struct sample *sample;
2292         int target_pstate;
2293
2294         update_turbo_state();
2295
2296         target_pstate = get_target_pstate(cpu);
2297         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2298         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2299         intel_pstate_update_pstate(cpu, target_pstate);
2300
2301         sample = &cpu->sample;
2302         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2303                 fp_toint(sample->busy_scaled),
2304                 from,
2305                 cpu->pstate.current_pstate,
2306                 sample->mperf,
2307                 sample->aperf,
2308                 sample->tsc,
2309                 get_avg_frequency(cpu),
2310                 fp_toint(cpu->iowait_boost * 100));
2311 }
2312
2313 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2314                                      unsigned int flags)
2315 {
2316         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2317         u64 delta_ns;
2318
2319         /* Don't allow remote callbacks */
2320         if (smp_processor_id() != cpu->cpu)
2321                 return;
2322
2323         delta_ns = time - cpu->last_update;
2324         if (flags & SCHED_CPUFREQ_IOWAIT) {
2325                 /* Start over if the CPU may have been idle. */
2326                 if (delta_ns > TICK_NSEC) {
2327                         cpu->iowait_boost = ONE_EIGHTH_FP;
2328                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2329                         cpu->iowait_boost <<= 1;
2330                         if (cpu->iowait_boost > int_tofp(1))
2331                                 cpu->iowait_boost = int_tofp(1);
2332                 } else {
2333                         cpu->iowait_boost = ONE_EIGHTH_FP;
2334                 }
2335         } else if (cpu->iowait_boost) {
2336                 /* Clear iowait_boost if the CPU may have been idle. */
2337                 if (delta_ns > TICK_NSEC)
2338                         cpu->iowait_boost = 0;
2339                 else
2340                         cpu->iowait_boost >>= 1;
2341         }
2342         cpu->last_update = time;
2343         delta_ns = time - cpu->sample.time;
2344         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2345                 return;
2346
2347         if (intel_pstate_sample(cpu, time))
2348                 intel_pstate_adjust_pstate(cpu);
2349 }
2350
2351 static struct pstate_funcs core_funcs = {
2352         .get_max = core_get_max_pstate,
2353         .get_max_physical = core_get_max_pstate_physical,
2354         .get_min = core_get_min_pstate,
2355         .get_turbo = core_get_turbo_pstate,
2356         .get_scaling = core_get_scaling,
2357         .get_val = core_get_val,
2358 };
2359
2360 static const struct pstate_funcs silvermont_funcs = {
2361         .get_max = atom_get_max_pstate,
2362         .get_max_physical = atom_get_max_pstate,
2363         .get_min = atom_get_min_pstate,
2364         .get_turbo = atom_get_turbo_pstate,
2365         .get_val = atom_get_val,
2366         .get_scaling = silvermont_get_scaling,
2367         .get_vid = atom_get_vid,
2368 };
2369
2370 static const struct pstate_funcs airmont_funcs = {
2371         .get_max = atom_get_max_pstate,
2372         .get_max_physical = atom_get_max_pstate,
2373         .get_min = atom_get_min_pstate,
2374         .get_turbo = atom_get_turbo_pstate,
2375         .get_val = atom_get_val,
2376         .get_scaling = airmont_get_scaling,
2377         .get_vid = atom_get_vid,
2378 };
2379
2380 static const struct pstate_funcs knl_funcs = {
2381         .get_max = core_get_max_pstate,
2382         .get_max_physical = core_get_max_pstate_physical,
2383         .get_min = core_get_min_pstate,
2384         .get_turbo = knl_get_turbo_pstate,
2385         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2386         .get_scaling = core_get_scaling,
2387         .get_val = core_get_val,
2388 };
2389
2390 #define X86_MATCH(model, policy)                                         \
2391         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2392                                            X86_FEATURE_APERFMPERF, &policy)
2393
2394 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2395         X86_MATCH(SANDYBRIDGE,          core_funcs),
2396         X86_MATCH(SANDYBRIDGE_X,        core_funcs),
2397         X86_MATCH(ATOM_SILVERMONT,      silvermont_funcs),
2398         X86_MATCH(IVYBRIDGE,            core_funcs),
2399         X86_MATCH(HASWELL,              core_funcs),
2400         X86_MATCH(BROADWELL,            core_funcs),
2401         X86_MATCH(IVYBRIDGE_X,          core_funcs),
2402         X86_MATCH(HASWELL_X,            core_funcs),
2403         X86_MATCH(HASWELL_L,            core_funcs),
2404         X86_MATCH(HASWELL_G,            core_funcs),
2405         X86_MATCH(BROADWELL_G,          core_funcs),
2406         X86_MATCH(ATOM_AIRMONT,         airmont_funcs),
2407         X86_MATCH(SKYLAKE_L,            core_funcs),
2408         X86_MATCH(BROADWELL_X,          core_funcs),
2409         X86_MATCH(SKYLAKE,              core_funcs),
2410         X86_MATCH(BROADWELL_D,          core_funcs),
2411         X86_MATCH(XEON_PHI_KNL,         knl_funcs),
2412         X86_MATCH(XEON_PHI_KNM,         knl_funcs),
2413         X86_MATCH(ATOM_GOLDMONT,        core_funcs),
2414         X86_MATCH(ATOM_GOLDMONT_PLUS,   core_funcs),
2415         X86_MATCH(SKYLAKE_X,            core_funcs),
2416         X86_MATCH(COMETLAKE,            core_funcs),
2417         X86_MATCH(ICELAKE_X,            core_funcs),
2418         {}
2419 };
2420 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2421
2422 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2423         X86_MATCH(BROADWELL_D,          core_funcs),
2424         X86_MATCH(BROADWELL_X,          core_funcs),
2425         X86_MATCH(SKYLAKE_X,            core_funcs),
2426         X86_MATCH(ICELAKE_X,            core_funcs),
2427         {}
2428 };
2429
2430 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2431         X86_MATCH(KABYLAKE,             core_funcs),
2432         {}
2433 };
2434
2435 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2436         X86_MATCH(SKYLAKE_X,            core_funcs),
2437         X86_MATCH(SKYLAKE,              core_funcs),
2438         {}
2439 };
2440
2441 static int intel_pstate_init_cpu(unsigned int cpunum)
2442 {
2443         struct cpudata *cpu;
2444
2445         cpu = all_cpu_data[cpunum];
2446
2447         if (!cpu) {
2448                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2449                 if (!cpu)
2450                         return -ENOMEM;
2451
2452                 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2453
2454                 cpu->cpu = cpunum;
2455
2456                 cpu->epp_default = -EINVAL;
2457
2458                 if (hwp_active) {
2459                         const struct x86_cpu_id *id;
2460
2461                         intel_pstate_hwp_enable(cpu);
2462
2463                         id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2464                         if (id && intel_pstate_acpi_pm_profile_server())
2465                                 hwp_boost = true;
2466                 }
2467         } else if (hwp_active) {
2468                 /*
2469                  * Re-enable HWP in case this happens after a resume from ACPI
2470                  * S3 if the CPU was offline during the whole system/resume
2471                  * cycle.
2472                  */
2473                 intel_pstate_hwp_reenable(cpu);
2474         }
2475
2476         cpu->epp_powersave = -EINVAL;
2477         cpu->epp_policy = 0;
2478
2479         intel_pstate_get_cpu_pstates(cpu);
2480
2481         pr_debug("controlling: cpu %d\n", cpunum);
2482
2483         return 0;
2484 }
2485
2486 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2487 {
2488         struct cpudata *cpu = all_cpu_data[cpu_num];
2489
2490         if (hwp_active && !hwp_boost)
2491                 return;
2492
2493         if (cpu->update_util_set)
2494                 return;
2495
2496         /* Prevent intel_pstate_update_util() from using stale data. */
2497         cpu->sample.time = 0;
2498         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2499                                      (hwp_active ?
2500                                       intel_pstate_update_util_hwp :
2501                                       intel_pstate_update_util));
2502         cpu->update_util_set = true;
2503 }
2504
2505 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2506 {
2507         struct cpudata *cpu_data = all_cpu_data[cpu];
2508
2509         if (!cpu_data->update_util_set)
2510                 return;
2511
2512         cpufreq_remove_update_util_hook(cpu);
2513         cpu_data->update_util_set = false;
2514         synchronize_rcu();
2515 }
2516
2517 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2518 {
2519         return global.turbo_disabled || global.no_turbo ?
2520                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2521 }
2522
2523 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2524                                             unsigned int policy_min,
2525                                             unsigned int policy_max)
2526 {
2527         int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2528         int32_t max_policy_perf, min_policy_perf;
2529
2530         max_policy_perf = policy_max / perf_ctl_scaling;
2531         if (policy_max == policy_min) {
2532                 min_policy_perf = max_policy_perf;
2533         } else {
2534                 min_policy_perf = policy_min / perf_ctl_scaling;
2535                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2536                                           0, max_policy_perf);
2537         }
2538
2539         /*
2540          * HWP needs some special consideration, because HWP_REQUEST uses
2541          * abstract values to represent performance rather than pure ratios.
2542          */
2543         if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2544                 int scaling = cpu->pstate.scaling;
2545                 int freq;
2546
2547                 freq = max_policy_perf * perf_ctl_scaling;
2548                 max_policy_perf = DIV_ROUND_UP(freq, scaling);
2549                 freq = min_policy_perf * perf_ctl_scaling;
2550                 min_policy_perf = DIV_ROUND_UP(freq, scaling);
2551         }
2552
2553         pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2554                  cpu->cpu, min_policy_perf, max_policy_perf);
2555
2556         /* Normalize user input to [min_perf, max_perf] */
2557         if (per_cpu_limits) {
2558                 cpu->min_perf_ratio = min_policy_perf;
2559                 cpu->max_perf_ratio = max_policy_perf;
2560         } else {
2561                 int turbo_max = cpu->pstate.turbo_pstate;
2562                 int32_t global_min, global_max;
2563
2564                 /* Global limits are in percent of the maximum turbo P-state. */
2565                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2566                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2567                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2568
2569                 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2570                          global_min, global_max);
2571
2572                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2573                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2574                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2575                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2576
2577                 /* Make sure min_perf <= max_perf */
2578                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2579                                           cpu->max_perf_ratio);
2580
2581         }
2582         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2583                  cpu->max_perf_ratio,
2584                  cpu->min_perf_ratio);
2585 }
2586
2587 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2588 {
2589         struct cpudata *cpu;
2590
2591         if (!policy->cpuinfo.max_freq)
2592                 return -ENODEV;
2593
2594         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2595                  policy->cpuinfo.max_freq, policy->max);
2596
2597         cpu = all_cpu_data[policy->cpu];
2598         cpu->policy = policy->policy;
2599
2600         mutex_lock(&intel_pstate_limits_lock);
2601
2602         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2603
2604         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2605                 /*
2606                  * NOHZ_FULL CPUs need this as the governor callback may not
2607                  * be invoked on them.
2608                  */
2609                 intel_pstate_clear_update_util_hook(policy->cpu);
2610                 intel_pstate_max_within_limits(cpu);
2611         } else {
2612                 intel_pstate_set_update_util_hook(policy->cpu);
2613         }
2614
2615         if (hwp_active) {
2616                 /*
2617                  * When hwp_boost was active before and dynamically it
2618                  * was turned off, in that case we need to clear the
2619                  * update util hook.
2620                  */
2621                 if (!hwp_boost)
2622                         intel_pstate_clear_update_util_hook(policy->cpu);
2623                 intel_pstate_hwp_set(policy->cpu);
2624         }
2625
2626         mutex_unlock(&intel_pstate_limits_lock);
2627
2628         return 0;
2629 }
2630
2631 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2632                                            struct cpufreq_policy_data *policy)
2633 {
2634         if (!hwp_active &&
2635             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2636             policy->max < policy->cpuinfo.max_freq &&
2637             policy->max > cpu->pstate.max_freq) {
2638                 pr_debug("policy->max > max non turbo frequency\n");
2639                 policy->max = policy->cpuinfo.max_freq;
2640         }
2641 }
2642
2643 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2644                                            struct cpufreq_policy_data *policy)
2645 {
2646         int max_freq;
2647
2648         update_turbo_state();
2649         if (hwp_active) {
2650                 intel_pstate_get_hwp_cap(cpu);
2651                 max_freq = global.no_turbo || global.turbo_disabled ?
2652                                 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2653         } else {
2654                 max_freq = intel_pstate_get_max_freq(cpu);
2655         }
2656         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2657
2658         intel_pstate_adjust_policy_max(cpu, policy);
2659 }
2660
2661 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2662 {
2663         intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2664
2665         return 0;
2666 }
2667
2668 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2669 {
2670         struct cpudata *cpu = all_cpu_data[policy->cpu];
2671
2672         pr_debug("CPU %d going offline\n", cpu->cpu);
2673
2674         if (cpu->suspended)
2675                 return 0;
2676
2677         /*
2678          * If the CPU is an SMT thread and it goes offline with the performance
2679          * settings different from the minimum, it will prevent its sibling
2680          * from getting to lower performance levels, so force the minimum
2681          * performance on CPU offline to prevent that from happening.
2682          */
2683         if (hwp_active)
2684                 intel_pstate_hwp_offline(cpu);
2685         else
2686                 intel_pstate_set_min_pstate(cpu);
2687
2688         intel_pstate_exit_perf_limits(policy);
2689
2690         return 0;
2691 }
2692
2693 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2694 {
2695         struct cpudata *cpu = all_cpu_data[policy->cpu];
2696
2697         pr_debug("CPU %d going online\n", cpu->cpu);
2698
2699         intel_pstate_init_acpi_perf_limits(policy);
2700
2701         if (hwp_active) {
2702                 /*
2703                  * Re-enable HWP and clear the "suspended" flag to let "resume"
2704                  * know that it need not do that.
2705                  */
2706                 intel_pstate_hwp_reenable(cpu);
2707                 cpu->suspended = false;
2708         }
2709
2710         return 0;
2711 }
2712
2713 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2714 {
2715         intel_pstate_clear_update_util_hook(policy->cpu);
2716
2717         return intel_cpufreq_cpu_offline(policy);
2718 }
2719
2720 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2721 {
2722         pr_debug("CPU %d exiting\n", policy->cpu);
2723
2724         policy->fast_switch_possible = false;
2725
2726         return 0;
2727 }
2728
2729 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2730 {
2731         struct cpudata *cpu;
2732         int rc;
2733
2734         rc = intel_pstate_init_cpu(policy->cpu);
2735         if (rc)
2736                 return rc;
2737
2738         cpu = all_cpu_data[policy->cpu];
2739
2740         cpu->max_perf_ratio = 0xFF;
2741         cpu->min_perf_ratio = 0;
2742
2743         /* cpuinfo and default policy values */
2744         policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2745         update_turbo_state();
2746         global.turbo_disabled_mf = global.turbo_disabled;
2747         policy->cpuinfo.max_freq = global.turbo_disabled ?
2748                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2749
2750         policy->min = policy->cpuinfo.min_freq;
2751         policy->max = policy->cpuinfo.max_freq;
2752
2753         intel_pstate_init_acpi_perf_limits(policy);
2754
2755         policy->fast_switch_possible = true;
2756
2757         return 0;
2758 }
2759
2760 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2761 {
2762         int ret = __intel_pstate_cpu_init(policy);
2763
2764         if (ret)
2765                 return ret;
2766
2767         /*
2768          * Set the policy to powersave to provide a valid fallback value in case
2769          * the default cpufreq governor is neither powersave nor performance.
2770          */
2771         policy->policy = CPUFREQ_POLICY_POWERSAVE;
2772
2773         if (hwp_active) {
2774                 struct cpudata *cpu = all_cpu_data[policy->cpu];
2775
2776                 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2777         }
2778
2779         return 0;
2780 }
2781
2782 static struct cpufreq_driver intel_pstate = {
2783         .flags          = CPUFREQ_CONST_LOOPS,
2784         .verify         = intel_pstate_verify_policy,
2785         .setpolicy      = intel_pstate_set_policy,
2786         .suspend        = intel_pstate_suspend,
2787         .resume         = intel_pstate_resume,
2788         .init           = intel_pstate_cpu_init,
2789         .exit           = intel_pstate_cpu_exit,
2790         .offline        = intel_pstate_cpu_offline,
2791         .online         = intel_pstate_cpu_online,
2792         .update_limits  = intel_pstate_update_limits,
2793         .name           = "intel_pstate",
2794 };
2795
2796 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2797 {
2798         struct cpudata *cpu = all_cpu_data[policy->cpu];
2799
2800         intel_pstate_verify_cpu_policy(cpu, policy);
2801         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2802
2803         return 0;
2804 }
2805
2806 /* Use of trace in passive mode:
2807  *
2808  * In passive mode the trace core_busy field (also known as the
2809  * performance field, and lablelled as such on the graphs; also known as
2810  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2811  * driver call was via the normal or fast switch path. Various graphs
2812  * output from the intel_pstate_tracer.py utility that include core_busy
2813  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2814  * so we use 10 to indicate the normal path through the driver, and
2815  * 90 to indicate the fast switch path through the driver.
2816  * The scaled_busy field is not used, and is set to 0.
2817  */
2818
2819 #define INTEL_PSTATE_TRACE_TARGET 10
2820 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2821
2822 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2823 {
2824         struct sample *sample;
2825
2826         if (!trace_pstate_sample_enabled())
2827                 return;
2828
2829         if (!intel_pstate_sample(cpu, ktime_get()))
2830                 return;
2831
2832         sample = &cpu->sample;
2833         trace_pstate_sample(trace_type,
2834                 0,
2835                 old_pstate,
2836                 cpu->pstate.current_pstate,
2837                 sample->mperf,
2838                 sample->aperf,
2839                 sample->tsc,
2840                 get_avg_frequency(cpu),
2841                 fp_toint(cpu->iowait_boost * 100));
2842 }
2843
2844 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2845                                      u32 desired, bool fast_switch)
2846 {
2847         u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2848
2849         value &= ~HWP_MIN_PERF(~0L);
2850         value |= HWP_MIN_PERF(min);
2851
2852         value &= ~HWP_MAX_PERF(~0L);
2853         value |= HWP_MAX_PERF(max);
2854
2855         value &= ~HWP_DESIRED_PERF(~0L);
2856         value |= HWP_DESIRED_PERF(desired);
2857
2858         if (value == prev)
2859                 return;
2860
2861         WRITE_ONCE(cpu->hwp_req_cached, value);
2862         if (fast_switch)
2863                 wrmsrl(MSR_HWP_REQUEST, value);
2864         else
2865                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2866 }
2867
2868 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2869                                           u32 target_pstate, bool fast_switch)
2870 {
2871         if (fast_switch)
2872                 wrmsrl(MSR_IA32_PERF_CTL,
2873                        pstate_funcs.get_val(cpu, target_pstate));
2874         else
2875                 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2876                               pstate_funcs.get_val(cpu, target_pstate));
2877 }
2878
2879 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2880                                        int target_pstate, bool fast_switch)
2881 {
2882         struct cpudata *cpu = all_cpu_data[policy->cpu];
2883         int old_pstate = cpu->pstate.current_pstate;
2884
2885         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2886         if (hwp_active) {
2887                 int max_pstate = policy->strict_target ?
2888                                         target_pstate : cpu->max_perf_ratio;
2889
2890                 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2891                                          fast_switch);
2892         } else if (target_pstate != old_pstate) {
2893                 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2894         }
2895
2896         cpu->pstate.current_pstate = target_pstate;
2897
2898         intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2899                             INTEL_PSTATE_TRACE_TARGET, old_pstate);
2900
2901         return target_pstate;
2902 }
2903
2904 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2905                                 unsigned int target_freq,
2906                                 unsigned int relation)
2907 {
2908         struct cpudata *cpu = all_cpu_data[policy->cpu];
2909         struct cpufreq_freqs freqs;
2910         int target_pstate;
2911
2912         update_turbo_state();
2913
2914         freqs.old = policy->cur;
2915         freqs.new = target_freq;
2916
2917         cpufreq_freq_transition_begin(policy, &freqs);
2918
2919         switch (relation) {
2920         case CPUFREQ_RELATION_L:
2921                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2922                 break;
2923         case CPUFREQ_RELATION_H:
2924                 target_pstate = freqs.new / cpu->pstate.scaling;
2925                 break;
2926         default:
2927                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2928                 break;
2929         }
2930
2931         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2932
2933         freqs.new = target_pstate * cpu->pstate.scaling;
2934
2935         cpufreq_freq_transition_end(policy, &freqs, false);
2936
2937         return 0;
2938 }
2939
2940 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2941                                               unsigned int target_freq)
2942 {
2943         struct cpudata *cpu = all_cpu_data[policy->cpu];
2944         int target_pstate;
2945
2946         update_turbo_state();
2947
2948         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2949
2950         target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2951
2952         return target_pstate * cpu->pstate.scaling;
2953 }
2954
2955 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2956                                       unsigned long min_perf,
2957                                       unsigned long target_perf,
2958                                       unsigned long capacity)
2959 {
2960         struct cpudata *cpu = all_cpu_data[cpunum];
2961         u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2962         int old_pstate = cpu->pstate.current_pstate;
2963         int cap_pstate, min_pstate, max_pstate, target_pstate;
2964
2965         update_turbo_state();
2966         cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2967                                              HWP_HIGHEST_PERF(hwp_cap);
2968
2969         /* Optimization: Avoid unnecessary divisions. */
2970
2971         target_pstate = cap_pstate;
2972         if (target_perf < capacity)
2973                 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2974
2975         min_pstate = cap_pstate;
2976         if (min_perf < capacity)
2977                 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2978
2979         if (min_pstate < cpu->pstate.min_pstate)
2980                 min_pstate = cpu->pstate.min_pstate;
2981
2982         if (min_pstate < cpu->min_perf_ratio)
2983                 min_pstate = cpu->min_perf_ratio;
2984
2985         max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2986         if (max_pstate < min_pstate)
2987                 max_pstate = min_pstate;
2988
2989         target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2990
2991         intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2992
2993         cpu->pstate.current_pstate = target_pstate;
2994         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2995 }
2996
2997 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2998 {
2999         struct freq_qos_request *req;
3000         struct cpudata *cpu;
3001         struct device *dev;
3002         int ret, freq;
3003
3004         dev = get_cpu_device(policy->cpu);
3005         if (!dev)
3006                 return -ENODEV;
3007
3008         ret = __intel_pstate_cpu_init(policy);
3009         if (ret)
3010                 return ret;
3011
3012         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3013         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3014         policy->cur = policy->cpuinfo.min_freq;
3015
3016         req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3017         if (!req) {
3018                 ret = -ENOMEM;
3019                 goto pstate_exit;
3020         }
3021
3022         cpu = all_cpu_data[policy->cpu];
3023
3024         if (hwp_active) {
3025                 u64 value;
3026
3027                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3028
3029                 intel_pstate_get_hwp_cap(cpu);
3030
3031                 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3032                 WRITE_ONCE(cpu->hwp_req_cached, value);
3033
3034                 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3035         } else {
3036                 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3037         }
3038
3039         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3040
3041         ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3042                                    freq);
3043         if (ret < 0) {
3044                 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3045                 goto free_req;
3046         }
3047
3048         freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3049
3050         ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3051                                    freq);
3052         if (ret < 0) {
3053                 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3054                 goto remove_min_req;
3055         }
3056
3057         policy->driver_data = req;
3058
3059         return 0;
3060
3061 remove_min_req:
3062         freq_qos_remove_request(req);
3063 free_req:
3064         kfree(req);
3065 pstate_exit:
3066         intel_pstate_exit_perf_limits(policy);
3067
3068         return ret;
3069 }
3070
3071 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3072 {
3073         struct freq_qos_request *req;
3074
3075         req = policy->driver_data;
3076
3077         freq_qos_remove_request(req + 1);
3078         freq_qos_remove_request(req);
3079         kfree(req);
3080
3081         return intel_pstate_cpu_exit(policy);
3082 }
3083
3084 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3085 {
3086         intel_pstate_suspend(policy);
3087
3088         if (hwp_active) {
3089                 struct cpudata *cpu = all_cpu_data[policy->cpu];
3090                 u64 value = READ_ONCE(cpu->hwp_req_cached);
3091
3092                 /*
3093                  * Clear the desired perf field in MSR_HWP_REQUEST in case
3094                  * intel_cpufreq_adjust_perf() is in use and the last value
3095                  * written by it may not be suitable.
3096                  */
3097                 value &= ~HWP_DESIRED_PERF(~0L);
3098                 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3099                 WRITE_ONCE(cpu->hwp_req_cached, value);
3100         }
3101
3102         return 0;
3103 }
3104
3105 static struct cpufreq_driver intel_cpufreq = {
3106         .flags          = CPUFREQ_CONST_LOOPS,
3107         .verify         = intel_cpufreq_verify_policy,
3108         .target         = intel_cpufreq_target,
3109         .fast_switch    = intel_cpufreq_fast_switch,
3110         .init           = intel_cpufreq_cpu_init,
3111         .exit           = intel_cpufreq_cpu_exit,
3112         .offline        = intel_cpufreq_cpu_offline,
3113         .online         = intel_pstate_cpu_online,
3114         .suspend        = intel_cpufreq_suspend,
3115         .resume         = intel_pstate_resume,
3116         .update_limits  = intel_pstate_update_limits,
3117         .name           = "intel_cpufreq",
3118 };
3119
3120 static struct cpufreq_driver *default_driver;
3121
3122 static void intel_pstate_driver_cleanup(void)
3123 {
3124         unsigned int cpu;
3125
3126         cpus_read_lock();
3127         for_each_online_cpu(cpu) {
3128                 if (all_cpu_data[cpu]) {
3129                         if (intel_pstate_driver == &intel_pstate)
3130                                 intel_pstate_clear_update_util_hook(cpu);
3131
3132                         spin_lock(&hwp_notify_lock);
3133                         kfree(all_cpu_data[cpu]);
3134                         WRITE_ONCE(all_cpu_data[cpu], NULL);
3135                         spin_unlock(&hwp_notify_lock);
3136                 }
3137         }
3138         cpus_read_unlock();
3139
3140         intel_pstate_driver = NULL;
3141 }
3142
3143 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3144 {
3145         int ret;
3146
3147         if (driver == &intel_pstate)
3148                 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3149
3150         memset(&global, 0, sizeof(global));
3151         global.max_perf_pct = 100;
3152
3153         intel_pstate_driver = driver;
3154         ret = cpufreq_register_driver(intel_pstate_driver);
3155         if (ret) {
3156                 intel_pstate_driver_cleanup();
3157                 return ret;
3158         }
3159
3160         global.min_perf_pct = min_perf_pct_min();
3161
3162         return 0;
3163 }
3164
3165 static ssize_t intel_pstate_show_status(char *buf)
3166 {
3167         if (!intel_pstate_driver)
3168                 return sprintf(buf, "off\n");
3169
3170         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3171                                         "active" : "passive");
3172 }
3173
3174 static int intel_pstate_update_status(const char *buf, size_t size)
3175 {
3176         if (size == 3 && !strncmp(buf, "off", size)) {
3177                 if (!intel_pstate_driver)
3178                         return -EINVAL;
3179
3180                 if (hwp_active)
3181                         return -EBUSY;
3182
3183                 cpufreq_unregister_driver(intel_pstate_driver);
3184                 intel_pstate_driver_cleanup();
3185                 return 0;
3186         }
3187
3188         if (size == 6 && !strncmp(buf, "active", size)) {
3189                 if (intel_pstate_driver) {
3190                         if (intel_pstate_driver == &intel_pstate)
3191                                 return 0;
3192
3193                         cpufreq_unregister_driver(intel_pstate_driver);
3194                 }
3195
3196                 return intel_pstate_register_driver(&intel_pstate);
3197         }
3198
3199         if (size == 7 && !strncmp(buf, "passive", size)) {
3200                 if (intel_pstate_driver) {
3201                         if (intel_pstate_driver == &intel_cpufreq)
3202                                 return 0;
3203
3204                         cpufreq_unregister_driver(intel_pstate_driver);
3205                         intel_pstate_sysfs_hide_hwp_dynamic_boost();
3206                 }
3207
3208                 return intel_pstate_register_driver(&intel_cpufreq);
3209         }
3210
3211         return -EINVAL;
3212 }
3213
3214 static int no_load __initdata;
3215 static int no_hwp __initdata;
3216 static int hwp_only __initdata;
3217 static unsigned int force_load __initdata;
3218
3219 static int __init intel_pstate_msrs_not_valid(void)
3220 {
3221         if (!pstate_funcs.get_max() ||
3222             !pstate_funcs.get_min() ||
3223             !pstate_funcs.get_turbo())
3224                 return -ENODEV;
3225
3226         return 0;
3227 }
3228
3229 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3230 {
3231         pstate_funcs.get_max   = funcs->get_max;
3232         pstate_funcs.get_max_physical = funcs->get_max_physical;
3233         pstate_funcs.get_min   = funcs->get_min;
3234         pstate_funcs.get_turbo = funcs->get_turbo;
3235         pstate_funcs.get_scaling = funcs->get_scaling;
3236         pstate_funcs.get_val   = funcs->get_val;
3237         pstate_funcs.get_vid   = funcs->get_vid;
3238         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3239 }
3240
3241 #ifdef CONFIG_ACPI
3242
3243 static bool __init intel_pstate_no_acpi_pss(void)
3244 {
3245         int i;
3246
3247         for_each_possible_cpu(i) {
3248                 acpi_status status;
3249                 union acpi_object *pss;
3250                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3251                 struct acpi_processor *pr = per_cpu(processors, i);
3252
3253                 if (!pr)
3254                         continue;
3255
3256                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3257                 if (ACPI_FAILURE(status))
3258                         continue;
3259
3260                 pss = buffer.pointer;
3261                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3262                         kfree(pss);
3263                         return false;
3264                 }
3265
3266                 kfree(pss);
3267         }
3268
3269         pr_debug("ACPI _PSS not found\n");
3270         return true;
3271 }
3272
3273 static bool __init intel_pstate_no_acpi_pcch(void)
3274 {
3275         acpi_status status;
3276         acpi_handle handle;
3277
3278         status = acpi_get_handle(NULL, "\\_SB", &handle);
3279         if (ACPI_FAILURE(status))
3280                 goto not_found;
3281
3282         if (acpi_has_method(handle, "PCCH"))
3283                 return false;
3284
3285 not_found:
3286         pr_debug("ACPI PCCH not found\n");
3287         return true;
3288 }
3289
3290 static bool __init intel_pstate_has_acpi_ppc(void)
3291 {
3292         int i;
3293
3294         for_each_possible_cpu(i) {
3295                 struct acpi_processor *pr = per_cpu(processors, i);
3296
3297                 if (!pr)
3298                         continue;
3299                 if (acpi_has_method(pr->handle, "_PPC"))
3300                         return true;
3301         }
3302         pr_debug("ACPI _PPC not found\n");
3303         return false;
3304 }
3305
3306 enum {
3307         PSS,
3308         PPC,
3309 };
3310
3311 /* Hardware vendor-specific info that has its own power management modes */
3312 static struct acpi_platform_list plat_info[] __initdata = {
3313         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3314         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3315         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3316         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3317         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3318         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3319         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3320         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3321         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328         { } /* End */
3329 };
3330
3331 #define BITMASK_OOB     (BIT(8) | BIT(18))
3332
3333 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3334 {
3335         const struct x86_cpu_id *id;
3336         u64 misc_pwr;
3337         int idx;
3338
3339         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3340         if (id) {
3341                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3342                 if (misc_pwr & BITMASK_OOB) {
3343                         pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3344                         pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3345                         return true;
3346                 }
3347         }
3348
3349         idx = acpi_match_platform_list(plat_info);
3350         if (idx < 0)
3351                 return false;
3352
3353         switch (plat_info[idx].data) {
3354         case PSS:
3355                 if (!intel_pstate_no_acpi_pss())
3356                         return false;
3357
3358                 return intel_pstate_no_acpi_pcch();
3359         case PPC:
3360                 return intel_pstate_has_acpi_ppc() && !force_load;
3361         }
3362
3363         return false;
3364 }
3365
3366 static void intel_pstate_request_control_from_smm(void)
3367 {
3368         /*
3369          * It may be unsafe to request P-states control from SMM if _PPC support
3370          * has not been enabled.
3371          */
3372         if (acpi_ppc)
3373                 acpi_processor_pstate_control();
3374 }
3375 #else /* CONFIG_ACPI not enabled */
3376 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
3377 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
3378 static inline void intel_pstate_request_control_from_smm(void) {}
3379 #endif /* CONFIG_ACPI */
3380
3381 #define INTEL_PSTATE_HWP_BROADWELL      0x01
3382
3383 #define X86_MATCH_HWP(model, hwp_mode)                                  \
3384         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3385                                            X86_FEATURE_HWP, hwp_mode)
3386
3387 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3388         X86_MATCH_HWP(BROADWELL_X,      INTEL_PSTATE_HWP_BROADWELL),
3389         X86_MATCH_HWP(BROADWELL_D,      INTEL_PSTATE_HWP_BROADWELL),
3390         X86_MATCH_HWP(ANY,              0),
3391         {}
3392 };
3393
3394 static bool intel_pstate_hwp_is_enabled(void)
3395 {
3396         u64 value;
3397
3398         rdmsrl(MSR_PM_ENABLE, value);
3399         return !!(value & 0x1);
3400 }
3401
3402 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3403         /*
3404          * Set EPP value as 102, this is the max suggested EPP
3405          * which can result in one core turbo frequency for
3406          * AlderLake Mobile CPUs.
3407          */
3408         X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3409         {}
3410 };
3411
3412 static int __init intel_pstate_init(void)
3413 {
3414         static struct cpudata **_all_cpu_data;
3415         const struct x86_cpu_id *id;
3416         int rc;
3417
3418         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3419                 return -ENODEV;
3420
3421         id = x86_match_cpu(hwp_support_ids);
3422         if (id) {
3423                 bool hwp_forced = intel_pstate_hwp_is_enabled();
3424
3425                 if (hwp_forced)
3426                         pr_info("HWP enabled by BIOS\n");
3427                 else if (no_load)
3428                         return -ENODEV;
3429
3430                 copy_cpu_funcs(&core_funcs);
3431                 /*
3432                  * Avoid enabling HWP for processors without EPP support,
3433                  * because that means incomplete HWP implementation which is a
3434                  * corner case and supporting it is generally problematic.
3435                  *
3436                  * If HWP is enabled already, though, there is no choice but to
3437                  * deal with it.
3438                  */
3439                 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3440                         WRITE_ONCE(hwp_active, 1);
3441                         hwp_mode_bdw = id->driver_data;
3442                         intel_pstate.attr = hwp_cpufreq_attrs;
3443                         intel_cpufreq.attr = hwp_cpufreq_attrs;
3444                         intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3445                         intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3446                         if (!default_driver)
3447                                 default_driver = &intel_pstate;
3448
3449                         if (boot_cpu_has(X86_FEATURE_HYBRID_CPU))
3450                                 intel_pstate_cppc_set_cpu_scaling();
3451
3452                         goto hwp_cpu_matched;
3453                 }
3454                 pr_info("HWP not enabled\n");
3455         } else {
3456                 if (no_load)
3457                         return -ENODEV;
3458
3459                 id = x86_match_cpu(intel_pstate_cpu_ids);
3460                 if (!id) {
3461                         pr_info("CPU model not supported\n");
3462                         return -ENODEV;
3463                 }
3464
3465                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3466         }
3467
3468         if (intel_pstate_msrs_not_valid()) {
3469                 pr_info("Invalid MSRs\n");
3470                 return -ENODEV;
3471         }
3472         /* Without HWP start in the passive mode. */
3473         if (!default_driver)
3474                 default_driver = &intel_cpufreq;
3475
3476 hwp_cpu_matched:
3477         /*
3478          * The Intel pstate driver will be ignored if the platform
3479          * firmware has its own power management modes.
3480          */
3481         if (intel_pstate_platform_pwr_mgmt_exists()) {
3482                 pr_info("P-states controlled by the platform\n");
3483                 return -ENODEV;
3484         }
3485
3486         if (!hwp_active && hwp_only)
3487                 return -ENOTSUPP;
3488
3489         pr_info("Intel P-state driver initializing\n");
3490
3491         _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3492         if (!_all_cpu_data)
3493                 return -ENOMEM;
3494
3495         WRITE_ONCE(all_cpu_data, _all_cpu_data);
3496
3497         intel_pstate_request_control_from_smm();
3498
3499         intel_pstate_sysfs_expose_params();
3500
3501         if (hwp_active) {
3502                 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3503
3504                 if (id)
3505                         epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3506         }
3507
3508         mutex_lock(&intel_pstate_driver_lock);
3509         rc = intel_pstate_register_driver(default_driver);
3510         mutex_unlock(&intel_pstate_driver_lock);
3511         if (rc) {
3512                 intel_pstate_sysfs_remove();
3513                 return rc;
3514         }
3515
3516         if (hwp_active) {
3517                 const struct x86_cpu_id *id;
3518
3519                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3520                 if (id) {
3521                         set_power_ctl_ee_state(false);
3522                         pr_info("Disabling energy efficiency optimization\n");
3523                 }
3524
3525                 pr_info("HWP enabled\n");
3526         } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3527                 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3528         }
3529
3530         return 0;
3531 }
3532 device_initcall(intel_pstate_init);
3533
3534 static int __init intel_pstate_setup(char *str)
3535 {
3536         if (!str)
3537                 return -EINVAL;
3538
3539         if (!strcmp(str, "disable"))
3540                 no_load = 1;
3541         else if (!strcmp(str, "active"))
3542                 default_driver = &intel_pstate;
3543         else if (!strcmp(str, "passive"))
3544                 default_driver = &intel_cpufreq;
3545
3546         if (!strcmp(str, "no_hwp"))
3547                 no_hwp = 1;
3548
3549         if (!strcmp(str, "force"))
3550                 force_load = 1;
3551         if (!strcmp(str, "hwp_only"))
3552                 hwp_only = 1;
3553         if (!strcmp(str, "per_cpu_perf_limits"))
3554                 per_cpu_limits = true;
3555
3556 #ifdef CONFIG_ACPI
3557         if (!strcmp(str, "support_acpi_ppc"))
3558                 acpi_ppc = true;
3559 #endif
3560
3561         return 0;
3562 }
3563 early_param("intel_pstate", intel_pstate_setup);
3564
3565 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3566 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3567 MODULE_LICENSE("GPL");