drivers/cpufreq/intel_pstate.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * intel_pstate.c: Native P state management for Intel processors
   4  *
   5  * (C) Copyright 2012 Intel Corporation
   6  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   7  */
   8
   9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  10
  11 #include <linux/kernel.h>
  12 #include <linux/kernel_stat.h>
  13 #include <linux/module.h>
  14 #include <linux/ktime.h>
  15 #include <linux/hrtimer.h>
  16 #include <linux/tick.h>
  17 #include <linux/slab.h>
  18 #include <linux/sched/cpufreq.h>
  19 #include <linux/list.h>
  20 #include <linux/cpu.h>
  21 #include <linux/cpufreq.h>
  22 #include <linux/sysfs.h>
  23 #include <linux/types.h>
  24 #include <linux/fs.h>
  25 #include <linux/acpi.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/pm_qos.h>
  28 #include <trace/events/power.h>
  29
  30 #include <asm/div64.h>
  31 #include <asm/msr.h>
  32 #include <asm/cpu_device_id.h>
  33 #include <asm/cpufeature.h>
  34 #include <asm/intel-family.h>
  35
  36 #define INTEL_PSTATE_SAMPLING_INTERVAL  (10 * NSEC_PER_MSEC)
  37
  38 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  39 #define INTEL_CPUFREQ_TRANSITION_DELAY          500
  40
  41 #ifdef CONFIG_ACPI
  42 #include <acpi/processor.h>
  43 #include <acpi/cppc_acpi.h>
  44 #endif
  45
  46 #define FRAC_BITS 8
  47 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  48 #define fp_toint(X) ((X) >> FRAC_BITS)
  49
  50 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
  51
  52 #define EXT_BITS 6
  53 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  54 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  55 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  56
  57 static inline int32_t mul_fp(int32_t x, int32_t y)
  58 {
  59         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  60 }
  61
  62 static inline int32_t div_fp(s64 x, s64 y)
  63 {
  64         return div64_s64((int64_t)x << FRAC_BITS, y);
  65 }
  66
  67 static inline int ceiling_fp(int32_t x)
  68 {
  69         int mask, ret;
  70
  71         ret = fp_toint(x);
  72         mask = (1 << FRAC_BITS) - 1;
  73         if (x & mask)
  74                 ret += 1;
  75         return ret;
  76 }
  77
  78 static inline int32_t percent_fp(int percent)
  79 {
  80         return div_fp(percent, 100);
  81 }
  82
  83 static inline u64 mul_ext_fp(u64 x, u64 y)
  84 {
  85         return (x * y) >> EXT_FRAC_BITS;
  86 }
  87
  88 static inline u64 div_ext_fp(u64 x, u64 y)
  89 {
  90         return div64_u64(x << EXT_FRAC_BITS, y);
  91 }
  92
  93 static inline int32_t percent_ext_fp(int percent)
  94 {
  95         return div_ext_fp(percent, 100);
  96 }
  97
  98 /**
  99  * struct sample -      Store performance sample
 100  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
 101  *                      performance during last sample period
 102  * @busy_scaled:        Scaled busy value which is used to calculate next
 103  *                      P state. This can be different than core_avg_perf
 104  *                      to account for cpu idle period
 105  * @aperf:              Difference of actual performance frequency clock count
 106  *                      read from APERF MSR between last and current sample
 107  * @mperf:              Difference of maximum performance frequency clock count
 108  *                      read from MPERF MSR between last and current sample
 109  * @tsc:                Difference of time stamp counter between last and
 110  *                      current sample
 111  * @time:               Current time from scheduler
 112  *
 113  * This structure is used in the cpudata structure to store performance sample
 114  * data for choosing next P State.
 115  */
 116 struct sample {
 117         int32_t core_avg_perf;
 118         int32_t busy_scaled;
 119         u64 aperf;
 120         u64 mperf;
 121         u64 tsc;
 122         u64 time;
 123 };
 124
 125 /**
 126  * struct pstate_data - Store P state data
 127  * @current_pstate:     Current requested P state
 128  * @min_pstate:         Min P state possible for this platform
 129  * @max_pstate:         Max P state possible for this platform
 130  * @max_pstate_physical:This is physical Max P state for a processor
 131  *                      This can be higher than the max_pstate which can
 132  *                      be limited by platform thermal design power limits
 133  * @scaling:            Scaling factor to  convert frequency to cpufreq
 134  *                      frequency units
 135  * @turbo_pstate:       Max Turbo P state possible for this platform
 136  * @max_freq:           @max_pstate frequency in cpufreq units
 137  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 138  *
 139  * Stores the per cpu model P state limits and current P state.
 140  */
 141 struct pstate_data {
 142         int     current_pstate;
 143         int     min_pstate;
 144         int     max_pstate;
 145         int     max_pstate_physical;
 146         int     scaling;
 147         int     turbo_pstate;
 148         unsigned int max_freq;
 149         unsigned int turbo_freq;
 150 };
 151
 152 /**
 153  * struct vid_data -    Stores voltage information data
 154  * @min:                VID data for this platform corresponding to
 155  *                      the lowest P state
 156  * @max:                VID data corresponding to the highest P State.
 157  * @turbo:              VID data for turbo P state
 158  * @ratio:              Ratio of (vid max - vid min) /
 159  *                      (max P state - Min P State)
 160  *
 161  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 162  * This data is used in Atom platforms, where in addition to target P state,
 163  * the voltage data needs to be specified to select next P State.
 164  */
 165 struct vid_data {
 166         int min;
 167         int max;
 168         int turbo;
 169         int32_t ratio;
 170 };
 171
 172 /**
 173  * struct global_params - Global parameters, mostly tunable via sysfs.
 174  * @no_turbo:           Whether or not to use turbo P-states.
 175  * @turbo_disabled:     Whether or not turbo P-states are available at all,
 176  *                      based on the MSR_IA32_MISC_ENABLE value and whether or
 177  *                      not the maximum reported turbo P-state is different from
 178  *                      the maximum reported non-turbo one.
 179  * @turbo_disabled_mf:  The @turbo_disabled value reflected by cpuinfo.max_freq.
 180  * @min_perf_pct:       Minimum capacity limit in percent of the maximum turbo
 181  *                      P-state capacity.
 182  * @max_perf_pct:       Maximum capacity limit in percent of the maximum turbo
 183  *                      P-state capacity.
 184  */
 185 struct global_params {
 186         bool no_turbo;
 187         bool turbo_disabled;
 188         bool turbo_disabled_mf;
 189         int max_perf_pct;
 190         int min_perf_pct;
 191 };
 192
 193 /**
 194  * struct cpudata -     Per CPU instance data storage
 195  * @cpu:                CPU number for this instance data
 196  * @policy:             CPUFreq policy value
 197  * @update_util:        CPUFreq utility callback information
 198  * @update_util_set:    CPUFreq utility callback is set
 199  * @iowait_boost:       iowait-related boost fraction
 200  * @last_update:        Time of the last update.
 201  * @pstate:             Stores P state limits for this CPU
 202  * @vid:                Stores VID limits for this CPU
 203  * @last_sample_time:   Last Sample time
 204  * @aperf_mperf_shift:  APERF vs MPERF counting frequency difference
 205  * @prev_aperf:         Last APERF value read from APERF MSR
 206  * @prev_mperf:         Last MPERF value read from MPERF MSR
 207  * @prev_tsc:           Last timestamp counter (TSC) value
 208  * @prev_cummulative_iowait: IO Wait time difference from last and
 209  *                      current sample
 210  * @sample:             Storage for storing last Sample data
 211  * @min_perf_ratio:     Minimum capacity in terms of PERF or HWP ratios
 212  * @max_perf_ratio:     Maximum capacity in terms of PERF or HWP ratios
 213  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 214  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 215  * @epp_powersave:      Last saved HWP energy performance preference
 216  *                      (EPP) or energy performance bias (EPB),
 217  *                      when policy switched to performance
 218  * @epp_policy:         Last saved policy used to set EPP/EPB
 219  * @epp_default:        Power on default HWP energy performance
 220  *                      preference/bias
 221  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 222  *                      operation
 223  * @hwp_req_cached:     Cached value of the last HWP Request MSR
 224  * @hwp_cap_cached:     Cached value of the last HWP Capabilities MSR
 225  * @last_io_update:     Last time when IO wake flag was set
 226  * @sched_flags:        Store scheduler flags for possible cross CPU update
 227  * @hwp_boost_min:      Last HWP boosted min performance
 228  *
 229  * This structure stores per CPU instance data for all CPUs.
 230  */
 231 struct cpudata {
 232         int cpu;
 233
 234         unsigned int policy;
 235         struct update_util_data update_util;
 236         bool   update_util_set;
 237
 238         struct pstate_data pstate;
 239         struct vid_data vid;
 240
 241         u64     last_update;
 242         u64     last_sample_time;
 243         u64     aperf_mperf_shift;
 244         u64     prev_aperf;
 245         u64     prev_mperf;
 246         u64     prev_tsc;
 247         u64     prev_cummulative_iowait;
 248         struct sample sample;
 249         int32_t min_perf_ratio;
 250         int32_t max_perf_ratio;
 251 #ifdef CONFIG_ACPI
 252         struct acpi_processor_performance acpi_perf_data;
 253         bool valid_pss_table;
 254 #endif
 255         unsigned int iowait_boost;
 256         s16 epp_powersave;
 257         s16 epp_policy;
 258         s16 epp_default;
 259         s16 epp_saved;
 260         u64 hwp_req_cached;
 261         u64 hwp_cap_cached;
 262         u64 last_io_update;
 263         unsigned int sched_flags;
 264         u32 hwp_boost_min;
 265 };
 266
 267 static struct cpudata **all_cpu_data;
 268
 269 /**
 270  * struct pstate_funcs - Per CPU model specific callbacks
 271  * @get_max:            Callback to get maximum non turbo effective P state
 272  * @get_max_physical:   Callback to get maximum non turbo physical P state
 273  * @get_min:            Callback to get minimum P state
 274  * @get_turbo:          Callback to get turbo P state
 275  * @get_scaling:        Callback to get frequency scaling factor
 276  * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
 277  * @get_val:            Callback to convert P state to actual MSR write value
 278  * @get_vid:            Callback to get VID data for Atom platforms
 279  *
 280  * Core and Atom CPU models have different way to get P State limits. This
 281  * structure is used to store those callbacks.
 282  */
 283 struct pstate_funcs {
 284         int (*get_max)(void);
 285         int (*get_max_physical)(void);
 286         int (*get_min)(void);
 287         int (*get_turbo)(void);
 288         int (*get_scaling)(void);
 289         int (*get_aperf_mperf_shift)(void);
 290         u64 (*get_val)(struct cpudata*, int pstate);
 291         void (*get_vid)(struct cpudata *);
 292 };
 293
 294 static struct pstate_funcs pstate_funcs __read_mostly;
 295
 296 static int hwp_active __read_mostly;
 297 static int hwp_mode_bdw __read_mostly;
 298 static bool per_cpu_limits __read_mostly;
 299 static bool hwp_boost __read_mostly;
 300
 301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
 302
 303 #ifdef CONFIG_ACPI
 304 static bool acpi_ppc;
 305 #endif
 306
 307 static struct global_params global;
 308
 309 static DEFINE_MUTEX(intel_pstate_driver_lock);
 310 static DEFINE_MUTEX(intel_pstate_limits_lock);
 311
 312 #ifdef CONFIG_ACPI
 313
 314 static bool intel_pstate_acpi_pm_profile_server(void)
 315 {
 316         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 317             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 318                 return true;
 319
 320         return false;
 321 }
 322
 323 static bool intel_pstate_get_ppc_enable_status(void)
 324 {
 325         if (intel_pstate_acpi_pm_profile_server())
 326                 return true;
 327
 328         return acpi_ppc;
 329 }
 330
 331 #ifdef CONFIG_ACPI_CPPC_LIB
 332
 333 /* The work item is needed to avoid CPU hotplug locking issues */
 334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 335 {
 336         sched_set_itmt_support();
 337 }
 338
 339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 340
 341 static void intel_pstate_set_itmt_prio(int cpu)
 342 {
 343         struct cppc_perf_caps cppc_perf;
 344         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 345         int ret;
 346
 347         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 348         if (ret)
 349                 return;
 350
 351         /*
 352          * The priorities can be set regardless of whether or not
 353          * sched_set_itmt_support(true) has been called and it is valid to
 354          * update them at any time after it has been called.
 355          */
 356         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 357
 358         if (max_highest_perf <= min_highest_perf) {
 359                 if (cppc_perf.highest_perf > max_highest_perf)
 360                         max_highest_perf = cppc_perf.highest_perf;
 361
 362                 if (cppc_perf.highest_perf < min_highest_perf)
 363                         min_highest_perf = cppc_perf.highest_perf;
 364
 365                 if (max_highest_perf > min_highest_perf) {
 366                         /*
 367                          * This code can be run during CPU online under the
 368                          * CPU hotplug locks, so sched_set_itmt_support()
 369                          * cannot be called from here.  Queue up a work item
 370                          * to invoke it.
 371                          */
 372                         schedule_work(&sched_itmt_work);
 373                 }
 374         }
 375 }
 376
 377 static int intel_pstate_get_cppc_guranteed(int cpu)
 378 {
 379         struct cppc_perf_caps cppc_perf;
 380         int ret;
 381
 382         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 383         if (ret)
 384                 return ret;
 385
 386         if (cppc_perf.guaranteed_perf)
 387                 return cppc_perf.guaranteed_perf;
 388
 389         return cppc_perf.nominal_perf;
 390 }
 391
 392 #else /* CONFIG_ACPI_CPPC_LIB */
 393 static void intel_pstate_set_itmt_prio(int cpu)
 394 {
 395 }
 396 #endif /* CONFIG_ACPI_CPPC_LIB */
 397
 398 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 399 {
 400         struct cpudata *cpu;
 401         int ret;
 402         int i;
 403
 404         if (hwp_active) {
 405                 intel_pstate_set_itmt_prio(policy->cpu);
 406                 return;
 407         }
 408
 409         if (!intel_pstate_get_ppc_enable_status())
 410                 return;
 411
 412         cpu = all_cpu_data[policy->cpu];
 413
 414         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 415                                                   policy->cpu);
 416         if (ret)
 417                 return;
 418
 419         /*
 420          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 421          * guarantee that the states returned by it map to the states in our
 422          * list directly.
 423          */
 424         if (cpu->acpi_perf_data.control_register.space_id !=
 425                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 426                 goto err;
 427
 428         /*
 429          * If there is only one entry _PSS, simply ignore _PSS and continue as
 430          * usual without taking _PSS into account
 431          */
 432         if (cpu->acpi_perf_data.state_count < 2)
 433                 goto err;
 434
 435         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 436         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 437                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 438                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 439                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 440                          (u32) cpu->acpi_perf_data.states[i].power,
 441                          (u32) cpu->acpi_perf_data.states[i].control);
 442         }
 443
 444         /*
 445          * The _PSS table doesn't contain whole turbo frequency range.
 446          * This just contains +1 MHZ above the max non turbo frequency,
 447          * with control value corresponding to max turbo ratio. But
 448          * when cpufreq set policy is called, it will call with this
 449          * max frequency, which will cause a reduced performance as
 450          * this driver uses real max turbo frequency as the max
 451          * frequency. So correct this frequency in _PSS table to
 452          * correct max turbo frequency based on the turbo state.
 453          * Also need to convert to MHz as _PSS freq is in MHz.
 454          */
 455         if (!global.turbo_disabled)
 456                 cpu->acpi_perf_data.states[0].core_frequency =
 457                                         policy->cpuinfo.max_freq / 1000;
 458         cpu->valid_pss_table = true;
 459         pr_debug("_PPC limits will be enforced\n");
 460
 461         return;
 462
 463  err:
 464         cpu->valid_pss_table = false;
 465         acpi_processor_unregister_performance(policy->cpu);
 466 }
 467
 468 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 469 {
 470         struct cpudata *cpu;
 471
 472         cpu = all_cpu_data[policy->cpu];
 473         if (!cpu->valid_pss_table)
 474                 return;
 475
 476         acpi_processor_unregister_performance(policy->cpu);
 477 }
 478 #else /* CONFIG_ACPI */
 479 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 480 {
 481 }
 482
 483 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 484 {
 485 }
 486
 487 static inline bool intel_pstate_acpi_pm_profile_server(void)
 488 {
 489         return false;
 490 }
 491 #endif /* CONFIG_ACPI */
 492
 493 #ifndef CONFIG_ACPI_CPPC_LIB
 494 static int intel_pstate_get_cppc_guranteed(int cpu)
 495 {
 496         return -ENOTSUPP;
 497 }
 498 #endif /* CONFIG_ACPI_CPPC_LIB */
 499
 500 static inline void update_turbo_state(void)
 501 {
 502         u64 misc_en;
 503         struct cpudata *cpu;
 504
 505         cpu = all_cpu_data[0];
 506         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 507         global.turbo_disabled =
 508                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 509                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 510 }
 511
 512 static int min_perf_pct_min(void)
 513 {
 514         struct cpudata *cpu = all_cpu_data[0];
 515         int turbo_pstate = cpu->pstate.turbo_pstate;
 516
 517         return turbo_pstate ?
 518                 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
 519 }
 520
 521 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 522 {
 523         u64 epb;
 524         int ret;
 525
 526         if (!boot_cpu_has(X86_FEATURE_EPB))
 527                 return -ENXIO;
 528
 529         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 530         if (ret)
 531                 return (s16)ret;
 532
 533         return (s16)(epb & 0x0f);
 534 }
 535
 536 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 537 {
 538         s16 epp;
 539
 540         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 541                 /*
 542                  * When hwp_req_data is 0, means that caller didn't read
 543                  * MSR_HWP_REQUEST, so need to read and get EPP.
 544                  */
 545                 if (!hwp_req_data) {
 546                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 547                                             &hwp_req_data);
 548                         if (epp)
 549                                 return epp;
 550                 }
 551                 epp = (hwp_req_data >> 24) & 0xff;
 552         } else {
 553                 /* When there is no EPP present, HWP uses EPB settings */
 554                 epp = intel_pstate_get_epb(cpu_data);
 555         }
 556
 557         return epp;
 558 }
 559
 560 static int intel_pstate_set_epb(int cpu, s16 pref)
 561 {
 562         u64 epb;
 563         int ret;
 564
 565         if (!boot_cpu_has(X86_FEATURE_EPB))
 566                 return -ENXIO;
 567
 568         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 569         if (ret)
 570                 return ret;
 571
 572         epb = (epb & ~0x0f) | pref;
 573         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 574
 575         return 0;
 576 }
 577
 578 /*
 579  * EPP/EPB display strings corresponding to EPP index in the
 580  * energy_perf_strings[]
 581  *      index           String
 582  *-------------------------------------
 583  *      0               default
 584  *      1               performance
 585  *      2               balance_performance
 586  *      3               balance_power
 587  *      4               power
 588  */
 589 static const char * const energy_perf_strings[] = {
 590         "default",
 591         "performance",
 592         "balance_performance",
 593         "balance_power",
 594         "power",
 595         NULL
 596 };
 597 static const unsigned int epp_values[] = {
 598         HWP_EPP_PERFORMANCE,
 599         HWP_EPP_BALANCE_PERFORMANCE,
 600         HWP_EPP_BALANCE_POWERSAVE,
 601         HWP_EPP_POWERSAVE
 602 };
 603
 604 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
 605 {
 606         s16 epp;
 607         int index = -EINVAL;
 608
 609         *raw_epp = 0;
 610         epp = intel_pstate_get_epp(cpu_data, 0);
 611         if (epp < 0)
 612                 return epp;
 613
 614         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 615                 if (epp == HWP_EPP_PERFORMANCE)
 616                         return 1;
 617                 if (epp == HWP_EPP_BALANCE_PERFORMANCE)
 618                         return 2;
 619                 if (epp == HWP_EPP_BALANCE_POWERSAVE)
 620                         return 3;
 621                 if (epp == HWP_EPP_POWERSAVE)
 622                         return 4;
 623                 *raw_epp = epp;
 624                 return 0;
 625         } else if (boot_cpu_has(X86_FEATURE_EPB)) {
 626                 /*
 627                  * Range:
 628                  *      0x00-0x03       :       Performance
 629                  *      0x04-0x07       :       Balance performance
 630                  *      0x08-0x0B       :       Balance power
 631                  *      0x0C-0x0F       :       Power
 632                  * The EPB is a 4 bit value, but our ranges restrict the
 633                  * value which can be set. Here only using top two bits
 634                  * effectively.
 635                  */
 636                 index = (epp >> 2) + 1;
 637         }
 638
 639         return index;
 640 }
 641
 642 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 643                                               int pref_index, bool use_raw,
 644                                               u32 raw_epp)
 645 {
 646         int epp = -EINVAL;
 647         int ret;
 648
 649         if (!pref_index)
 650                 epp = cpu_data->epp_default;
 651
 652         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 653                 /*
 654                  * Use the cached HWP Request MSR value, because the register
 655                  * itself may be updated by intel_pstate_hwp_boost_up() or
 656                  * intel_pstate_hwp_boost_down() at any time.
 657                  */
 658                 u64 value = READ_ONCE(cpu_data->hwp_req_cached);
 659
 660                 value &= ~GENMASK_ULL(31, 24);
 661
 662                 if (use_raw)
 663                         epp = raw_epp;
 664                 else if (epp == -EINVAL)
 665                         epp = epp_values[pref_index - 1];
 666
 667                 value |= (u64)epp << 24;
 668                 /*
 669                  * The only other updater of hwp_req_cached in the active mode,
 670                  * intel_pstate_hwp_set(), is called under the same lock as this
 671                  * function, so it cannot run in parallel with the update below.
 672                  */
 673                 WRITE_ONCE(cpu_data->hwp_req_cached, value);
 674                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 675         } else {
 676                 if (epp == -EINVAL)
 677                         epp = (pref_index - 1) << 2;
 678                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 679         }
 680
 681         return ret;
 682 }
 683
 684 static ssize_t show_energy_performance_available_preferences(
 685                                 struct cpufreq_policy *policy, char *buf)
 686 {
 687         int i = 0;
 688         int ret = 0;
 689
 690         while (energy_perf_strings[i] != NULL)
 691                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 692
 693         ret += sprintf(&buf[ret], "\n");
 694
 695         return ret;
 696 }
 697
 698 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 699
 700 static ssize_t store_energy_performance_preference(
 701                 struct cpufreq_policy *policy, const char *buf, size_t count)
 702 {
 703         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 704         char str_preference[21];
 705         bool raw = false;
 706         ssize_t ret;
 707         u32 epp = 0;
 708
 709         ret = sscanf(buf, "%20s", str_preference);
 710         if (ret != 1)
 711                 return -EINVAL;
 712
 713         ret = match_string(energy_perf_strings, -1, str_preference);
 714         if (ret < 0) {
 715                 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
 716                         return ret;
 717
 718                 ret = kstrtouint(buf, 10, &epp);
 719                 if (ret)
 720                         return ret;
 721
 722                 if (epp > 255)
 723                         return -EINVAL;
 724
 725                 raw = true;
 726         }
 727
 728         mutex_lock(&intel_pstate_limits_lock);
 729
 730         ret = intel_pstate_set_energy_pref_index(cpu_data, ret, raw, epp);
 731         if (!ret)
 732                 ret = count;
 733
 734         mutex_unlock(&intel_pstate_limits_lock);
 735
 736         return ret;
 737 }
 738
 739 static ssize_t show_energy_performance_preference(
 740                                 struct cpufreq_policy *policy, char *buf)
 741 {
 742         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 743         int preference, raw_epp;
 744
 745         preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
 746         if (preference < 0)
 747                 return preference;
 748
 749         if (raw_epp)
 750                 return  sprintf(buf, "%d\n", raw_epp);
 751         else
 752                 return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 753 }
 754
 755 cpufreq_freq_attr_rw(energy_performance_preference);
 756
 757 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
 758 {
 759         struct cpudata *cpu;
 760         u64 cap;
 761         int ratio;
 762
 763         ratio = intel_pstate_get_cppc_guranteed(policy->cpu);
 764         if (ratio <= 0) {
 765                 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
 766                 ratio = HWP_GUARANTEED_PERF(cap);
 767         }
 768
 769         cpu = all_cpu_data[policy->cpu];
 770
 771         return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
 772 }
 773
 774 cpufreq_freq_attr_ro(base_frequency);
 775
 776 static struct freq_attr *hwp_cpufreq_attrs[] = {
 777         &energy_performance_preference,
 778         &energy_performance_available_preferences,
 779         &base_frequency,
 780         NULL,
 781 };
 782
 783 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
 784                                      int *current_max)
 785 {
 786         u64 cap;
 787
 788         rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 789         WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
 790         if (global.no_turbo)
 791                 *current_max = HWP_GUARANTEED_PERF(cap);
 792         else
 793                 *current_max = HWP_HIGHEST_PERF(cap);
 794
 795         *phy_max = HWP_HIGHEST_PERF(cap);
 796 }
 797
 798 static void intel_pstate_hwp_set(unsigned int cpu)
 799 {
 800         struct cpudata *cpu_data = all_cpu_data[cpu];
 801         int max, min;
 802         u64 value;
 803         s16 epp;
 804
 805         max = cpu_data->max_perf_ratio;
 806         min = cpu_data->min_perf_ratio;
 807
 808         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
 809                 min = max;
 810
 811         rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 812
 813         value &= ~HWP_MIN_PERF(~0L);
 814         value |= HWP_MIN_PERF(min);
 815
 816         value &= ~HWP_MAX_PERF(~0L);
 817         value |= HWP_MAX_PERF(max);
 818
 819         if (cpu_data->epp_policy == cpu_data->policy)
 820                 goto skip_epp;
 821
 822         cpu_data->epp_policy = cpu_data->policy;
 823
 824         if (cpu_data->epp_saved >= 0) {
 825                 epp = cpu_data->epp_saved;
 826                 cpu_data->epp_saved = -EINVAL;
 827                 goto update_epp;
 828         }
 829
 830         if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 831                 epp = intel_pstate_get_epp(cpu_data, value);
 832                 cpu_data->epp_powersave = epp;
 833                 /* If EPP read was failed, then don't try to write */
 834                 if (epp < 0)
 835                         goto skip_epp;
 836
 837                 epp = 0;
 838         } else {
 839                 /* skip setting EPP, when saved value is invalid */
 840                 if (cpu_data->epp_powersave < 0)
 841                         goto skip_epp;
 842
 843                 /*
 844                  * No need to restore EPP when it is not zero. This
 845                  * means:
 846                  *  - Policy is not changed
 847                  *  - user has manually changed
 848                  *  - Error reading EPB
 849                  */
 850                 epp = intel_pstate_get_epp(cpu_data, value);
 851                 if (epp)
 852                         goto skip_epp;
 853
 854                 epp = cpu_data->epp_powersave;
 855         }
 856 update_epp:
 857         if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
 858                 value &= ~GENMASK_ULL(31, 24);
 859                 value |= (u64)epp << 24;
 860         } else {
 861                 intel_pstate_set_epb(cpu, epp);
 862         }
 863 skip_epp:
 864         WRITE_ONCE(cpu_data->hwp_req_cached, value);
 865         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 866 }
 867
 868 static void intel_pstate_hwp_force_min_perf(int cpu)
 869 {
 870         u64 value;
 871         int min_perf;
 872
 873         value = all_cpu_data[cpu]->hwp_req_cached;
 874         value &= ~GENMASK_ULL(31, 0);
 875         min_perf = HWP_LOWEST_PERF(all_cpu_data[cpu]->hwp_cap_cached);
 876
 877         /* Set hwp_max = hwp_min */
 878         value |= HWP_MAX_PERF(min_perf);
 879         value |= HWP_MIN_PERF(min_perf);
 880
 881         /* Set EPP to min */
 882         if (boot_cpu_has(X86_FEATURE_HWP_EPP))
 883                 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
 884
 885         wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 886 }
 887
 888 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 889 {
 890         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 891
 892         if (!hwp_active)
 893                 return 0;
 894
 895         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 896
 897         return 0;
 898 }
 899
 900 #define POWER_CTL_EE_ENABLE     1
 901 #define POWER_CTL_EE_DISABLE    2
 902
 903 static int power_ctl_ee_state;
 904
 905 static void set_power_ctl_ee_state(bool input)
 906 {
 907         u64 power_ctl;
 908
 909         mutex_lock(&intel_pstate_driver_lock);
 910         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
 911         if (input) {
 912                 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
 913                 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
 914         } else {
 915                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
 916                 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
 917         }
 918         wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
 919         mutex_unlock(&intel_pstate_driver_lock);
 920 }
 921
 922 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
 923
 924 static int intel_pstate_resume(struct cpufreq_policy *policy)
 925 {
 926
 927         /* Only restore if the system default is changed */
 928         if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
 929                 set_power_ctl_ee_state(true);
 930         else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
 931                 set_power_ctl_ee_state(false);
 932
 933         if (!hwp_active)
 934                 return 0;
 935
 936         mutex_lock(&intel_pstate_limits_lock);
 937
 938         if (policy->cpu == 0)
 939                 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
 940
 941         all_cpu_data[policy->cpu]->epp_policy = 0;
 942         intel_pstate_hwp_set(policy->cpu);
 943
 944         mutex_unlock(&intel_pstate_limits_lock);
 945
 946         return 0;
 947 }
 948
 949 static void intel_pstate_update_policies(void)
 950 {
 951         int cpu;
 952
 953         for_each_possible_cpu(cpu)
 954                 cpufreq_update_policy(cpu);
 955 }
 956
 957 static void intel_pstate_update_max_freq(unsigned int cpu)
 958 {
 959         struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
 960         struct cpudata *cpudata;
 961
 962         if (!policy)
 963                 return;
 964
 965         cpudata = all_cpu_data[cpu];
 966         policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
 967                         cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
 968
 969         refresh_frequency_limits(policy);
 970
 971         cpufreq_cpu_release(policy);
 972 }
 973
 974 static void intel_pstate_update_limits(unsigned int cpu)
 975 {
 976         mutex_lock(&intel_pstate_driver_lock);
 977
 978         update_turbo_state();
 979         /*
 980          * If turbo has been turned on or off globally, policy limits for
 981          * all CPUs need to be updated to reflect that.
 982          */
 983         if (global.turbo_disabled_mf != global.turbo_disabled) {
 984                 global.turbo_disabled_mf = global.turbo_disabled;
 985                 arch_set_max_freq_ratio(global.turbo_disabled);
 986                 for_each_possible_cpu(cpu)
 987                         intel_pstate_update_max_freq(cpu);
 988         } else {
 989                 cpufreq_update_policy(cpu);
 990         }
 991
 992         mutex_unlock(&intel_pstate_driver_lock);
 993 }
 994
 995 /************************** sysfs begin ************************/
 996 #define show_one(file_name, object)                                     \
 997         static ssize_t show_##file_name                                 \
 998         (struct kobject *kobj, struct kobj_attribute *attr, char *buf)  \
 999         {                                                               \
1000                 return sprintf(buf, "%u\n", global.object);             \
1001         }
1002
1003 static ssize_t intel_pstate_show_status(char *buf);
1004 static int intel_pstate_update_status(const char *buf, size_t size);
1005
1006 static ssize_t show_status(struct kobject *kobj,
1007                            struct kobj_attribute *attr, char *buf)
1008 {
1009         ssize_t ret;
1010
1011         mutex_lock(&intel_pstate_driver_lock);
1012         ret = intel_pstate_show_status(buf);
1013         mutex_unlock(&intel_pstate_driver_lock);
1014
1015         return ret;
1016 }
1017
1018 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1019                             const char *buf, size_t count)
1020 {
1021         char *p = memchr(buf, '\n', count);
1022         int ret;
1023
1024         mutex_lock(&intel_pstate_driver_lock);
1025         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1026         mutex_unlock(&intel_pstate_driver_lock);
1027
1028         return ret < 0 ? ret : count;
1029 }
1030
1031 static ssize_t show_turbo_pct(struct kobject *kobj,
1032                                 struct kobj_attribute *attr, char *buf)
1033 {
1034         struct cpudata *cpu;
1035         int total, no_turbo, turbo_pct;
1036         uint32_t turbo_fp;
1037
1038         mutex_lock(&intel_pstate_driver_lock);
1039
1040         if (!intel_pstate_driver) {
1041                 mutex_unlock(&intel_pstate_driver_lock);
1042                 return -EAGAIN;
1043         }
1044
1045         cpu = all_cpu_data[0];
1046
1047         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1048         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1049         turbo_fp = div_fp(no_turbo, total);
1050         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1051
1052         mutex_unlock(&intel_pstate_driver_lock);
1053
1054         return sprintf(buf, "%u\n", turbo_pct);
1055 }
1056
1057 static ssize_t show_num_pstates(struct kobject *kobj,
1058                                 struct kobj_attribute *attr, char *buf)
1059 {
1060         struct cpudata *cpu;
1061         int total;
1062
1063         mutex_lock(&intel_pstate_driver_lock);
1064
1065         if (!intel_pstate_driver) {
1066                 mutex_unlock(&intel_pstate_driver_lock);
1067                 return -EAGAIN;
1068         }
1069
1070         cpu = all_cpu_data[0];
1071         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1072
1073         mutex_unlock(&intel_pstate_driver_lock);
1074
1075         return sprintf(buf, "%u\n", total);
1076 }
1077
1078 static ssize_t show_no_turbo(struct kobject *kobj,
1079                              struct kobj_attribute *attr, char *buf)
1080 {
1081         ssize_t ret;
1082
1083         mutex_lock(&intel_pstate_driver_lock);
1084
1085         if (!intel_pstate_driver) {
1086                 mutex_unlock(&intel_pstate_driver_lock);
1087                 return -EAGAIN;
1088         }
1089
1090         update_turbo_state();
1091         if (global.turbo_disabled)
1092                 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1093         else
1094                 ret = sprintf(buf, "%u\n", global.no_turbo);
1095
1096         mutex_unlock(&intel_pstate_driver_lock);
1097
1098         return ret;
1099 }
1100
1101 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1102                               const char *buf, size_t count)
1103 {
1104         unsigned int input;
1105         int ret;
1106
1107         ret = sscanf(buf, "%u", &input);
1108         if (ret != 1)
1109                 return -EINVAL;
1110
1111         mutex_lock(&intel_pstate_driver_lock);
1112
1113         if (!intel_pstate_driver) {
1114                 mutex_unlock(&intel_pstate_driver_lock);
1115                 return -EAGAIN;
1116         }
1117
1118         mutex_lock(&intel_pstate_limits_lock);
1119
1120         update_turbo_state();
1121         if (global.turbo_disabled) {
1122                 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1123                 mutex_unlock(&intel_pstate_limits_lock);
1124                 mutex_unlock(&intel_pstate_driver_lock);
1125                 return -EPERM;
1126         }
1127
1128         global.no_turbo = clamp_t(int, input, 0, 1);
1129
1130         if (global.no_turbo) {
1131                 struct cpudata *cpu = all_cpu_data[0];
1132                 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1133
1134                 /* Squash the global minimum into the permitted range. */
1135                 if (global.min_perf_pct > pct)
1136                         global.min_perf_pct = pct;
1137         }
1138
1139         mutex_unlock(&intel_pstate_limits_lock);
1140
1141         intel_pstate_update_policies();
1142
1143         mutex_unlock(&intel_pstate_driver_lock);
1144
1145         return count;
1146 }
1147
1148 static struct cpufreq_driver intel_pstate;
1149
1150 static void update_qos_request(enum freq_qos_req_type type)
1151 {
1152         int max_state, turbo_max, freq, i, perf_pct;
1153         struct freq_qos_request *req;
1154         struct cpufreq_policy *policy;
1155
1156         for_each_possible_cpu(i) {
1157                 struct cpudata *cpu = all_cpu_data[i];
1158
1159                 policy = cpufreq_cpu_get(i);
1160                 if (!policy)
1161                         continue;
1162
1163                 req = policy->driver_data;
1164                 cpufreq_cpu_put(policy);
1165
1166                 if (!req)
1167                         continue;
1168
1169                 if (hwp_active)
1170                         intel_pstate_get_hwp_max(i, &turbo_max, &max_state);
1171                 else
1172                         turbo_max = cpu->pstate.turbo_pstate;
1173
1174                 if (type == FREQ_QOS_MIN) {
1175                         perf_pct = global.min_perf_pct;
1176                 } else {
1177                         req++;
1178                         perf_pct = global.max_perf_pct;
1179                 }
1180
1181                 freq = DIV_ROUND_UP(turbo_max * perf_pct, 100);
1182                 freq *= cpu->pstate.scaling;
1183
1184                 if (freq_qos_update_request(req, freq) < 0)
1185                         pr_warn("Failed to update freq constraint: CPU%d\n", i);
1186         }
1187 }
1188
1189 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1190                                   const char *buf, size_t count)
1191 {
1192         unsigned int input;
1193         int ret;
1194
1195         ret = sscanf(buf, "%u", &input);
1196         if (ret != 1)
1197                 return -EINVAL;
1198
1199         mutex_lock(&intel_pstate_driver_lock);
1200
1201         if (!intel_pstate_driver) {
1202                 mutex_unlock(&intel_pstate_driver_lock);
1203                 return -EAGAIN;
1204         }
1205
1206         mutex_lock(&intel_pstate_limits_lock);
1207
1208         global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1209
1210         mutex_unlock(&intel_pstate_limits_lock);
1211
1212         if (intel_pstate_driver == &intel_pstate)
1213                 intel_pstate_update_policies();
1214         else
1215                 update_qos_request(FREQ_QOS_MAX);
1216
1217         mutex_unlock(&intel_pstate_driver_lock);
1218
1219         return count;
1220 }
1221
1222 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1223                                   const char *buf, size_t count)
1224 {
1225         unsigned int input;
1226         int ret;
1227
1228         ret = sscanf(buf, "%u", &input);
1229         if (ret != 1)
1230                 return -EINVAL;
1231
1232         mutex_lock(&intel_pstate_driver_lock);
1233
1234         if (!intel_pstate_driver) {
1235                 mutex_unlock(&intel_pstate_driver_lock);
1236                 return -EAGAIN;
1237         }
1238
1239         mutex_lock(&intel_pstate_limits_lock);
1240
1241         global.min_perf_pct = clamp_t(int, input,
1242                                       min_perf_pct_min(), global.max_perf_pct);
1243
1244         mutex_unlock(&intel_pstate_limits_lock);
1245
1246         if (intel_pstate_driver == &intel_pstate)
1247                 intel_pstate_update_policies();
1248         else
1249                 update_qos_request(FREQ_QOS_MIN);
1250
1251         mutex_unlock(&intel_pstate_driver_lock);
1252
1253         return count;
1254 }
1255
1256 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1257                                 struct kobj_attribute *attr, char *buf)
1258 {
1259         return sprintf(buf, "%u\n", hwp_boost);
1260 }
1261
1262 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1263                                        struct kobj_attribute *b,
1264                                        const char *buf, size_t count)
1265 {
1266         unsigned int input;
1267         int ret;
1268
1269         ret = kstrtouint(buf, 10, &input);
1270         if (ret)
1271                 return ret;
1272
1273         mutex_lock(&intel_pstate_driver_lock);
1274         hwp_boost = !!input;
1275         intel_pstate_update_policies();
1276         mutex_unlock(&intel_pstate_driver_lock);
1277
1278         return count;
1279 }
1280
1281 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1282                                       char *buf)
1283 {
1284         u64 power_ctl;
1285         int enable;
1286
1287         rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1288         enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1289         return sprintf(buf, "%d\n", !enable);
1290 }
1291
1292 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1293                                        const char *buf, size_t count)
1294 {
1295         bool input;
1296         int ret;
1297
1298         ret = kstrtobool(buf, &input);
1299         if (ret)
1300                 return ret;
1301
1302         set_power_ctl_ee_state(input);
1303
1304         return count;
1305 }
1306
1307 show_one(max_perf_pct, max_perf_pct);
1308 show_one(min_perf_pct, min_perf_pct);
1309
1310 define_one_global_rw(status);
1311 define_one_global_rw(no_turbo);
1312 define_one_global_rw(max_perf_pct);
1313 define_one_global_rw(min_perf_pct);
1314 define_one_global_ro(turbo_pct);
1315 define_one_global_ro(num_pstates);
1316 define_one_global_rw(hwp_dynamic_boost);
1317 define_one_global_rw(energy_efficiency);
1318
1319 static struct attribute *intel_pstate_attributes[] = {
1320         &status.attr,
1321         &no_turbo.attr,
1322         &turbo_pct.attr,
1323         &num_pstates.attr,
1324         NULL
1325 };
1326
1327 static const struct attribute_group intel_pstate_attr_group = {
1328         .attrs = intel_pstate_attributes,
1329 };
1330
1331 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1332
1333 static void __init intel_pstate_sysfs_expose_params(void)
1334 {
1335         struct kobject *intel_pstate_kobject;
1336         int rc;
1337
1338         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1339                                                 &cpu_subsys.dev_root->kobj);
1340         if (WARN_ON(!intel_pstate_kobject))
1341                 return;
1342
1343         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1344         if (WARN_ON(rc))
1345                 return;
1346
1347         /*
1348          * If per cpu limits are enforced there are no global limits, so
1349          * return without creating max/min_perf_pct attributes
1350          */
1351         if (per_cpu_limits)
1352                 return;
1353
1354         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1355         WARN_ON(rc);
1356
1357         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1358         WARN_ON(rc);
1359
1360         if (hwp_active) {
1361                 rc = sysfs_create_file(intel_pstate_kobject,
1362                                        &hwp_dynamic_boost.attr);
1363                 WARN_ON(rc);
1364         }
1365
1366         if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1367                 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1368                 WARN_ON(rc);
1369         }
1370 }
1371 /************************** sysfs end ************************/
1372
1373 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1374 {
1375         /* First disable HWP notification interrupt as we don't process them */
1376         if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1377                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1378
1379         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1380         cpudata->epp_policy = 0;
1381         if (cpudata->epp_default == -EINVAL)
1382                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1383 }
1384
1385 static int atom_get_min_pstate(void)
1386 {
1387         u64 value;
1388
1389         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1390         return (value >> 8) & 0x7F;
1391 }
1392
1393 static int atom_get_max_pstate(void)
1394 {
1395         u64 value;
1396
1397         rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1398         return (value >> 16) & 0x7F;
1399 }
1400
1401 static int atom_get_turbo_pstate(void)
1402 {
1403         u64 value;
1404
1405         rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1406         return value & 0x7F;
1407 }
1408
1409 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1410 {
1411         u64 val;
1412         int32_t vid_fp;
1413         u32 vid;
1414
1415         val = (u64)pstate << 8;
1416         if (global.no_turbo && !global.turbo_disabled)
1417                 val |= (u64)1 << 32;
1418
1419         vid_fp = cpudata->vid.min + mul_fp(
1420                 int_tofp(pstate - cpudata->pstate.min_pstate),
1421                 cpudata->vid.ratio);
1422
1423         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1424         vid = ceiling_fp(vid_fp);
1425
1426         if (pstate > cpudata->pstate.max_pstate)
1427                 vid = cpudata->vid.turbo;
1428
1429         return val | vid;
1430 }
1431
1432 static int silvermont_get_scaling(void)
1433 {
1434         u64 value;
1435         int i;
1436         /* Defined in Table 35-6 from SDM (Sept 2015) */
1437         static int silvermont_freq_table[] = {
1438                 83300, 100000, 133300, 116700, 80000};
1439
1440         rdmsrl(MSR_FSB_FREQ, value);
1441         i = value & 0x7;
1442         WARN_ON(i > 4);
1443
1444         return silvermont_freq_table[i];
1445 }
1446
1447 static int airmont_get_scaling(void)
1448 {
1449         u64 value;
1450         int i;
1451         /* Defined in Table 35-10 from SDM (Sept 2015) */
1452         static int airmont_freq_table[] = {
1453                 83300, 100000, 133300, 116700, 80000,
1454                 93300, 90000, 88900, 87500};
1455
1456         rdmsrl(MSR_FSB_FREQ, value);
1457         i = value & 0xF;
1458         WARN_ON(i > 8);
1459
1460         return airmont_freq_table[i];
1461 }
1462
1463 static void atom_get_vid(struct cpudata *cpudata)
1464 {
1465         u64 value;
1466
1467         rdmsrl(MSR_ATOM_CORE_VIDS, value);
1468         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1469         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1470         cpudata->vid.ratio = div_fp(
1471                 cpudata->vid.max - cpudata->vid.min,
1472                 int_tofp(cpudata->pstate.max_pstate -
1473                         cpudata->pstate.min_pstate));
1474
1475         rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1476         cpudata->vid.turbo = value & 0x7f;
1477 }
1478
1479 static int core_get_min_pstate(void)
1480 {
1481         u64 value;
1482
1483         rdmsrl(MSR_PLATFORM_INFO, value);
1484         return (value >> 40) & 0xFF;
1485 }
1486
1487 static int core_get_max_pstate_physical(void)
1488 {
1489         u64 value;
1490
1491         rdmsrl(MSR_PLATFORM_INFO, value);
1492         return (value >> 8) & 0xFF;
1493 }
1494
1495 static int core_get_tdp_ratio(u64 plat_info)
1496 {
1497         /* Check how many TDP levels present */
1498         if (plat_info & 0x600000000) {
1499                 u64 tdp_ctrl;
1500                 u64 tdp_ratio;
1501                 int tdp_msr;
1502                 int err;
1503
1504                 /* Get the TDP level (0, 1, 2) to get ratios */
1505                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1506                 if (err)
1507                         return err;
1508
1509                 /* TDP MSR are continuous starting at 0x648 */
1510                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1511                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1512                 if (err)
1513                         return err;
1514
1515                 /* For level 1 and 2, bits[23:16] contain the ratio */
1516                 if (tdp_ctrl & 0x03)
1517                         tdp_ratio >>= 16;
1518
1519                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1520                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1521
1522                 return (int)tdp_ratio;
1523         }
1524
1525         return -ENXIO;
1526 }
1527
1528 static int core_get_max_pstate(void)
1529 {
1530         u64 tar;
1531         u64 plat_info;
1532         int max_pstate;
1533         int tdp_ratio;
1534         int err;
1535
1536         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1537         max_pstate = (plat_info >> 8) & 0xFF;
1538
1539         tdp_ratio = core_get_tdp_ratio(plat_info);
1540         if (tdp_ratio <= 0)
1541                 return max_pstate;
1542
1543         if (hwp_active) {
1544                 /* Turbo activation ratio is not used on HWP platforms */
1545                 return tdp_ratio;
1546         }
1547
1548         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1549         if (!err) {
1550                 int tar_levels;
1551
1552                 /* Do some sanity checking for safety */
1553                 tar_levels = tar & 0xff;
1554                 if (tdp_ratio - 1 == tar_levels) {
1555                         max_pstate = tar_levels;
1556                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1557                 }
1558         }
1559
1560         return max_pstate;
1561 }
1562
1563 static int core_get_turbo_pstate(void)
1564 {
1565         u64 value;
1566         int nont, ret;
1567
1568         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1569         nont = core_get_max_pstate();
1570         ret = (value) & 255;
1571         if (ret <= nont)
1572                 ret = nont;
1573         return ret;
1574 }
1575
1576 static inline int core_get_scaling(void)
1577 {
1578         return 100000;
1579 }
1580
1581 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1582 {
1583         u64 val;
1584
1585         val = (u64)pstate << 8;
1586         if (global.no_turbo && !global.turbo_disabled)
1587                 val |= (u64)1 << 32;
1588
1589         return val;
1590 }
1591
1592 static int knl_get_aperf_mperf_shift(void)
1593 {
1594         return 10;
1595 }
1596
1597 static int knl_get_turbo_pstate(void)
1598 {
1599         u64 value;
1600         int nont, ret;
1601
1602         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1603         nont = core_get_max_pstate();
1604         ret = (((value) >> 8) & 0xFF);
1605         if (ret <= nont)
1606                 ret = nont;
1607         return ret;
1608 }
1609
1610 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1611 {
1612         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1613         cpu->pstate.current_pstate = pstate;
1614         /*
1615          * Generally, there is no guarantee that this code will always run on
1616          * the CPU being updated, so force the register update to run on the
1617          * right CPU.
1618          */
1619         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1620                       pstate_funcs.get_val(cpu, pstate));
1621 }
1622
1623 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1624 {
1625         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1626 }
1627
1628 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1629 {
1630         int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1631
1632         update_turbo_state();
1633         intel_pstate_set_pstate(cpu, pstate);
1634 }
1635
1636 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1637 {
1638         cpu->pstate.min_pstate = pstate_funcs.get_min();
1639         cpu->pstate.max_pstate = pstate_funcs.get_max();
1640         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1641         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1642         cpu->pstate.scaling = pstate_funcs.get_scaling();
1643         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1644
1645         if (hwp_active && !hwp_mode_bdw) {
1646                 unsigned int phy_max, current_max;
1647
1648                 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, &current_max);
1649                 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1650                 cpu->pstate.turbo_pstate = phy_max;
1651         } else {
1652                 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1653         }
1654
1655         if (pstate_funcs.get_aperf_mperf_shift)
1656                 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1657
1658         if (pstate_funcs.get_vid)
1659                 pstate_funcs.get_vid(cpu);
1660
1661         intel_pstate_set_min_pstate(cpu);
1662 }
1663
1664 /*
1665  * Long hold time will keep high perf limits for long time,
1666  * which negatively impacts perf/watt for some workloads,
1667  * like specpower. 3ms is based on experiements on some
1668  * workoads.
1669  */
1670 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1671
1672 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1673 {
1674         u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1675         u32 max_limit = (hwp_req & 0xff00) >> 8;
1676         u32 min_limit = (hwp_req & 0xff);
1677         u32 boost_level1;
1678
1679         /*
1680          * Cases to consider (User changes via sysfs or boot time):
1681          * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1682          *      No boost, return.
1683          * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1684          *     Should result in one level boost only for P0.
1685          * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1686          *     Should result in two level boost:
1687          *         (min + p1)/2 and P1.
1688          * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1689          *     Should result in three level boost:
1690          *        (min + p1)/2, P1 and P0.
1691          */
1692
1693         /* If max and min are equal or already at max, nothing to boost */
1694         if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1695                 return;
1696
1697         if (!cpu->hwp_boost_min)
1698                 cpu->hwp_boost_min = min_limit;
1699
1700         /* level at half way mark between min and guranteed */
1701         boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1702
1703         if (cpu->hwp_boost_min < boost_level1)
1704                 cpu->hwp_boost_min = boost_level1;
1705         else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1706                 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1707         else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1708                  max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1709                 cpu->hwp_boost_min = max_limit;
1710         else
1711                 return;
1712
1713         hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1714         wrmsrl(MSR_HWP_REQUEST, hwp_req);
1715         cpu->last_update = cpu->sample.time;
1716 }
1717
1718 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1719 {
1720         if (cpu->hwp_boost_min) {
1721                 bool expired;
1722
1723                 /* Check if we are idle for hold time to boost down */
1724                 expired = time_after64(cpu->sample.time, cpu->last_update +
1725                                        hwp_boost_hold_time_ns);
1726                 if (expired) {
1727                         wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1728                         cpu->hwp_boost_min = 0;
1729                 }
1730         }
1731         cpu->last_update = cpu->sample.time;
1732 }
1733
1734 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1735                                                       u64 time)
1736 {
1737         cpu->sample.time = time;
1738
1739         if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1740                 bool do_io = false;
1741
1742                 cpu->sched_flags = 0;
1743                 /*
1744                  * Set iowait_boost flag and update time. Since IO WAIT flag
1745                  * is set all the time, we can't just conclude that there is
1746                  * some IO bound activity is scheduled on this CPU with just
1747                  * one occurrence. If we receive at least two in two
1748                  * consecutive ticks, then we treat as boost candidate.
1749                  */
1750                 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1751                         do_io = true;
1752
1753                 cpu->last_io_update = time;
1754
1755                 if (do_io)
1756                         intel_pstate_hwp_boost_up(cpu);
1757
1758         } else {
1759                 intel_pstate_hwp_boost_down(cpu);
1760         }
1761 }
1762
1763 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1764                                                 u64 time, unsigned int flags)
1765 {
1766         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1767
1768         cpu->sched_flags |= flags;
1769
1770         if (smp_processor_id() == cpu->cpu)
1771                 intel_pstate_update_util_hwp_local(cpu, time);
1772 }
1773
1774 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1775 {
1776         struct sample *sample = &cpu->sample;
1777
1778         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1779 }
1780
1781 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1782 {
1783         u64 aperf, mperf;
1784         unsigned long flags;
1785         u64 tsc;
1786
1787         local_irq_save(flags);
1788         rdmsrl(MSR_IA32_APERF, aperf);
1789         rdmsrl(MSR_IA32_MPERF, mperf);
1790         tsc = rdtsc();
1791         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1792                 local_irq_restore(flags);
1793                 return false;
1794         }
1795         local_irq_restore(flags);
1796
1797         cpu->last_sample_time = cpu->sample.time;
1798         cpu->sample.time = time;
1799         cpu->sample.aperf = aperf;
1800         cpu->sample.mperf = mperf;
1801         cpu->sample.tsc =  tsc;
1802         cpu->sample.aperf -= cpu->prev_aperf;
1803         cpu->sample.mperf -= cpu->prev_mperf;
1804         cpu->sample.tsc -= cpu->prev_tsc;
1805
1806         cpu->prev_aperf = aperf;
1807         cpu->prev_mperf = mperf;
1808         cpu->prev_tsc = tsc;
1809         /*
1810          * First time this function is invoked in a given cycle, all of the
1811          * previous sample data fields are equal to zero or stale and they must
1812          * be populated with meaningful numbers for things to work, so assume
1813          * that sample.time will always be reset before setting the utilization
1814          * update hook and make the caller skip the sample then.
1815          */
1816         if (cpu->last_sample_time) {
1817                 intel_pstate_calc_avg_perf(cpu);
1818                 return true;
1819         }
1820         return false;
1821 }
1822
1823 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1824 {
1825         return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1826 }
1827
1828 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1829 {
1830         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1831                           cpu->sample.core_avg_perf);
1832 }
1833
1834 static inline int32_t get_target_pstate(struct cpudata *cpu)
1835 {
1836         struct sample *sample = &cpu->sample;
1837         int32_t busy_frac;
1838         int target, avg_pstate;
1839
1840         busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1841                            sample->tsc);
1842
1843         if (busy_frac < cpu->iowait_boost)
1844                 busy_frac = cpu->iowait_boost;
1845
1846         sample->busy_scaled = busy_frac * 100;
1847
1848         target = global.no_turbo || global.turbo_disabled ?
1849                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1850         target += target >> 2;
1851         target = mul_fp(target, busy_frac);
1852         if (target < cpu->pstate.min_pstate)
1853                 target = cpu->pstate.min_pstate;
1854
1855         /*
1856          * If the average P-state during the previous cycle was higher than the
1857          * current target, add 50% of the difference to the target to reduce
1858          * possible performance oscillations and offset possible performance
1859          * loss related to moving the workload from one CPU to another within
1860          * a package/module.
1861          */
1862         avg_pstate = get_avg_pstate(cpu);
1863         if (avg_pstate > target)
1864                 target += (avg_pstate - target) >> 1;
1865
1866         return target;
1867 }
1868
1869 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1870 {
1871         int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1872         int max_pstate = max(min_pstate, cpu->max_perf_ratio);
1873
1874         return clamp_t(int, pstate, min_pstate, max_pstate);
1875 }
1876
1877 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1878 {
1879         if (pstate == cpu->pstate.current_pstate)
1880                 return;
1881
1882         cpu->pstate.current_pstate = pstate;
1883         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1884 }
1885
1886 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1887 {
1888         int from = cpu->pstate.current_pstate;
1889         struct sample *sample;
1890         int target_pstate;
1891
1892         update_turbo_state();
1893
1894         target_pstate = get_target_pstate(cpu);
1895         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1896         trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1897         intel_pstate_update_pstate(cpu, target_pstate);
1898
1899         sample = &cpu->sample;
1900         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1901                 fp_toint(sample->busy_scaled),
1902                 from,
1903                 cpu->pstate.current_pstate,
1904                 sample->mperf,
1905                 sample->aperf,
1906                 sample->tsc,
1907                 get_avg_frequency(cpu),
1908                 fp_toint(cpu->iowait_boost * 100));
1909 }
1910
1911 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1912                                      unsigned int flags)
1913 {
1914         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1915         u64 delta_ns;
1916
1917         /* Don't allow remote callbacks */
1918         if (smp_processor_id() != cpu->cpu)
1919                 return;
1920
1921         delta_ns = time - cpu->last_update;
1922         if (flags & SCHED_CPUFREQ_IOWAIT) {
1923                 /* Start over if the CPU may have been idle. */
1924                 if (delta_ns > TICK_NSEC) {
1925                         cpu->iowait_boost = ONE_EIGHTH_FP;
1926                 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
1927                         cpu->iowait_boost <<= 1;
1928                         if (cpu->iowait_boost > int_tofp(1))
1929                                 cpu->iowait_boost = int_tofp(1);
1930                 } else {
1931                         cpu->iowait_boost = ONE_EIGHTH_FP;
1932                 }
1933         } else if (cpu->iowait_boost) {
1934                 /* Clear iowait_boost if the CPU may have been idle. */
1935                 if (delta_ns > TICK_NSEC)
1936                         cpu->iowait_boost = 0;
1937                 else
1938                         cpu->iowait_boost >>= 1;
1939         }
1940         cpu->last_update = time;
1941         delta_ns = time - cpu->sample.time;
1942         if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1943                 return;
1944
1945         if (intel_pstate_sample(cpu, time))
1946                 intel_pstate_adjust_pstate(cpu);
1947 }
1948
1949 static struct pstate_funcs core_funcs = {
1950         .get_max = core_get_max_pstate,
1951         .get_max_physical = core_get_max_pstate_physical,
1952         .get_min = core_get_min_pstate,
1953         .get_turbo = core_get_turbo_pstate,
1954         .get_scaling = core_get_scaling,
1955         .get_val = core_get_val,
1956 };
1957
1958 static const struct pstate_funcs silvermont_funcs = {
1959         .get_max = atom_get_max_pstate,
1960         .get_max_physical = atom_get_max_pstate,
1961         .get_min = atom_get_min_pstate,
1962         .get_turbo = atom_get_turbo_pstate,
1963         .get_val = atom_get_val,
1964         .get_scaling = silvermont_get_scaling,
1965         .get_vid = atom_get_vid,
1966 };
1967
1968 static const struct pstate_funcs airmont_funcs = {
1969         .get_max = atom_get_max_pstate,
1970         .get_max_physical = atom_get_max_pstate,
1971         .get_min = atom_get_min_pstate,
1972         .get_turbo = atom_get_turbo_pstate,
1973         .get_val = atom_get_val,
1974         .get_scaling = airmont_get_scaling,
1975         .get_vid = atom_get_vid,
1976 };
1977
1978 static const struct pstate_funcs knl_funcs = {
1979         .get_max = core_get_max_pstate,
1980         .get_max_physical = core_get_max_pstate_physical,
1981         .get_min = core_get_min_pstate,
1982         .get_turbo = knl_get_turbo_pstate,
1983         .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1984         .get_scaling = core_get_scaling,
1985         .get_val = core_get_val,
1986 };
1987
1988 #define X86_MATCH(model, policy)                                         \
1989         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
1990                                            X86_FEATURE_APERFMPERF, &policy)
1991
1992 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1993         X86_MATCH(SANDYBRIDGE,          core_funcs),
1994         X86_MATCH(SANDYBRIDGE_X,        core_funcs),
1995         X86_MATCH(ATOM_SILVERMONT,      silvermont_funcs),
1996         X86_MATCH(IVYBRIDGE,            core_funcs),
1997         X86_MATCH(HASWELL,              core_funcs),
1998         X86_MATCH(BROADWELL,            core_funcs),
1999         X86_MATCH(IVYBRIDGE_X,          core_funcs),
2000         X86_MATCH(HASWELL_X,            core_funcs),
2001         X86_MATCH(HASWELL_L,            core_funcs),
2002         X86_MATCH(HASWELL_G,            core_funcs),
2003         X86_MATCH(BROADWELL_G,          core_funcs),
2004         X86_MATCH(ATOM_AIRMONT,         airmont_funcs),
2005         X86_MATCH(SKYLAKE_L,            core_funcs),
2006         X86_MATCH(BROADWELL_X,          core_funcs),
2007         X86_MATCH(SKYLAKE,              core_funcs),
2008         X86_MATCH(BROADWELL_D,          core_funcs),
2009         X86_MATCH(XEON_PHI_KNL,         knl_funcs),
2010         X86_MATCH(XEON_PHI_KNM,         knl_funcs),
2011         X86_MATCH(ATOM_GOLDMONT,        core_funcs),
2012         X86_MATCH(ATOM_GOLDMONT_PLUS,   core_funcs),
2013         X86_MATCH(SKYLAKE_X,            core_funcs),
2014         {}
2015 };
2016 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2017
2018 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2019         X86_MATCH(BROADWELL_D,          core_funcs),
2020         X86_MATCH(BROADWELL_X,          core_funcs),
2021         X86_MATCH(SKYLAKE_X,            core_funcs),
2022         {}
2023 };
2024
2025 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2026         X86_MATCH(KABYLAKE,             core_funcs),
2027         {}
2028 };
2029
2030 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
2031         X86_MATCH(SKYLAKE_X,            core_funcs),
2032         X86_MATCH(SKYLAKE,              core_funcs),
2033         {}
2034 };
2035
2036 static int intel_pstate_init_cpu(unsigned int cpunum)
2037 {
2038         struct cpudata *cpu;
2039
2040         cpu = all_cpu_data[cpunum];
2041
2042         if (!cpu) {
2043                 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2044                 if (!cpu)
2045                         return -ENOMEM;
2046
2047                 all_cpu_data[cpunum] = cpu;
2048
2049                 cpu->epp_default = -EINVAL;
2050                 cpu->epp_powersave = -EINVAL;
2051                 cpu->epp_saved = -EINVAL;
2052         }
2053
2054         cpu = all_cpu_data[cpunum];
2055
2056         cpu->cpu = cpunum;
2057
2058         if (hwp_active) {
2059                 const struct x86_cpu_id *id;
2060
2061                 intel_pstate_hwp_enable(cpu);
2062
2063                 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
2064                 if (id && intel_pstate_acpi_pm_profile_server())
2065                         hwp_boost = true;
2066         }
2067
2068         intel_pstate_get_cpu_pstates(cpu);
2069
2070         pr_debug("controlling: cpu %d\n", cpunum);
2071
2072         return 0;
2073 }
2074
2075 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2076 {
2077         struct cpudata *cpu = all_cpu_data[cpu_num];
2078
2079         if (hwp_active && !hwp_boost)
2080                 return;
2081
2082         if (cpu->update_util_set)
2083                 return;
2084
2085         /* Prevent intel_pstate_update_util() from using stale data. */
2086         cpu->sample.time = 0;
2087         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2088                                      (hwp_active ?
2089                                       intel_pstate_update_util_hwp :
2090                                       intel_pstate_update_util));
2091         cpu->update_util_set = true;
2092 }
2093
2094 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2095 {
2096         struct cpudata *cpu_data = all_cpu_data[cpu];
2097
2098         if (!cpu_data->update_util_set)
2099                 return;
2100
2101         cpufreq_remove_update_util_hook(cpu);
2102         cpu_data->update_util_set = false;
2103         synchronize_rcu();
2104 }
2105
2106 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2107 {
2108         return global.turbo_disabled || global.no_turbo ?
2109                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2110 }
2111
2112 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2113                                             unsigned int policy_min,
2114                                             unsigned int policy_max)
2115 {
2116         int max_freq = intel_pstate_get_max_freq(cpu);
2117         int32_t max_policy_perf, min_policy_perf;
2118         int max_state, turbo_max;
2119
2120         /*
2121          * HWP needs some special consideration, because on BDX the
2122          * HWP_REQUEST uses abstract value to represent performance
2123          * rather than pure ratios.
2124          */
2125         if (hwp_active) {
2126                 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
2127         } else {
2128                 max_state = global.no_turbo || global.turbo_disabled ?
2129                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2130                 turbo_max = cpu->pstate.turbo_pstate;
2131         }
2132
2133         max_policy_perf = max_state * policy_max / max_freq;
2134         if (policy_max == policy_min) {
2135                 min_policy_perf = max_policy_perf;
2136         } else {
2137                 min_policy_perf = max_state * policy_min / max_freq;
2138                 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2139                                           0, max_policy_perf);
2140         }
2141
2142         pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
2143                  cpu->cpu, max_state, min_policy_perf, max_policy_perf);
2144
2145         /* Normalize user input to [min_perf, max_perf] */
2146         if (per_cpu_limits) {
2147                 cpu->min_perf_ratio = min_policy_perf;
2148                 cpu->max_perf_ratio = max_policy_perf;
2149         } else {
2150                 int32_t global_min, global_max;
2151
2152                 /* Global limits are in percent of the maximum turbo P-state. */
2153                 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2154                 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2155                 global_min = clamp_t(int32_t, global_min, 0, global_max);
2156
2157                 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2158                          global_min, global_max);
2159
2160                 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2161                 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2162                 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2163                 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2164
2165                 /* Make sure min_perf <= max_perf */
2166                 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2167                                           cpu->max_perf_ratio);
2168
2169         }
2170         pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2171                  cpu->max_perf_ratio,
2172                  cpu->min_perf_ratio);
2173 }
2174
2175 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2176 {
2177         struct cpudata *cpu;
2178
2179         if (!policy->cpuinfo.max_freq)
2180                 return -ENODEV;
2181
2182         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2183                  policy->cpuinfo.max_freq, policy->max);
2184
2185         cpu = all_cpu_data[policy->cpu];
2186         cpu->policy = policy->policy;
2187
2188         mutex_lock(&intel_pstate_limits_lock);
2189
2190         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2191
2192         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2193                 /*
2194                  * NOHZ_FULL CPUs need this as the governor callback may not
2195                  * be invoked on them.
2196                  */
2197                 intel_pstate_clear_update_util_hook(policy->cpu);
2198                 intel_pstate_max_within_limits(cpu);
2199         } else {
2200                 intel_pstate_set_update_util_hook(policy->cpu);
2201         }
2202
2203         if (hwp_active) {
2204                 /*
2205                  * When hwp_boost was active before and dynamically it
2206                  * was turned off, in that case we need to clear the
2207                  * update util hook.
2208                  */
2209                 if (!hwp_boost)
2210                         intel_pstate_clear_update_util_hook(policy->cpu);
2211                 intel_pstate_hwp_set(policy->cpu);
2212         }
2213
2214         mutex_unlock(&intel_pstate_limits_lock);
2215
2216         return 0;
2217 }
2218
2219 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2220                                            struct cpufreq_policy_data *policy)
2221 {
2222         if (!hwp_active &&
2223             cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2224             policy->max < policy->cpuinfo.max_freq &&
2225             policy->max > cpu->pstate.max_freq) {
2226                 pr_debug("policy->max > max non turbo frequency\n");
2227                 policy->max = policy->cpuinfo.max_freq;
2228         }
2229 }
2230
2231 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2232                                            struct cpufreq_policy_data *policy)
2233 {
2234         update_turbo_state();
2235         cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2236                                      intel_pstate_get_max_freq(cpu));
2237
2238         intel_pstate_adjust_policy_max(cpu, policy);
2239 }
2240
2241 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2242 {
2243         intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2244
2245         return 0;
2246 }
2247
2248 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2249 {
2250         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2251 }
2252
2253 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2254 {
2255         pr_debug("CPU %d exiting\n", policy->cpu);
2256
2257         intel_pstate_clear_update_util_hook(policy->cpu);
2258         if (hwp_active) {
2259                 intel_pstate_hwp_save_state(policy);
2260                 intel_pstate_hwp_force_min_perf(policy->cpu);
2261         } else {
2262                 intel_cpufreq_stop_cpu(policy);
2263         }
2264 }
2265
2266 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2267 {
2268         intel_pstate_exit_perf_limits(policy);
2269
2270         policy->fast_switch_possible = false;
2271
2272         return 0;
2273 }
2274
2275 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2276 {
2277         struct cpudata *cpu;
2278         int rc;
2279
2280         rc = intel_pstate_init_cpu(policy->cpu);
2281         if (rc)
2282                 return rc;
2283
2284         cpu = all_cpu_data[policy->cpu];
2285
2286         cpu->max_perf_ratio = 0xFF;
2287         cpu->min_perf_ratio = 0;
2288
2289         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2290         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2291
2292         /* cpuinfo and default policy values */
2293         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2294         update_turbo_state();
2295         global.turbo_disabled_mf = global.turbo_disabled;
2296         policy->cpuinfo.max_freq = global.turbo_disabled ?
2297                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2298         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2299
2300         if (hwp_active) {
2301                 unsigned int max_freq;
2302
2303                 max_freq = global.turbo_disabled ?
2304                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2305                 if (max_freq < policy->cpuinfo.max_freq)
2306                         policy->cpuinfo.max_freq = max_freq;
2307         }
2308
2309         intel_pstate_init_acpi_perf_limits(policy);
2310
2311         policy->fast_switch_possible = true;
2312
2313         return 0;
2314 }
2315
2316 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2317 {
2318         int ret = __intel_pstate_cpu_init(policy);
2319
2320         if (ret)
2321                 return ret;
2322
2323         /*
2324          * Set the policy to powersave to provide a valid fallback value in case
2325          * the default cpufreq governor is neither powersave nor performance.
2326          */
2327         policy->policy = CPUFREQ_POLICY_POWERSAVE;
2328
2329         return 0;
2330 }
2331
2332 static struct cpufreq_driver intel_pstate = {
2333         .flags          = CPUFREQ_CONST_LOOPS,
2334         .verify         = intel_pstate_verify_policy,
2335         .setpolicy      = intel_pstate_set_policy,
2336         .suspend        = intel_pstate_hwp_save_state,
2337         .resume         = intel_pstate_resume,
2338         .init           = intel_pstate_cpu_init,
2339         .exit           = intel_pstate_cpu_exit,
2340         .stop_cpu       = intel_pstate_stop_cpu,
2341         .update_limits  = intel_pstate_update_limits,
2342         .name           = "intel_pstate",
2343 };
2344
2345 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2346 {
2347         struct cpudata *cpu = all_cpu_data[policy->cpu];
2348
2349         intel_pstate_verify_cpu_policy(cpu, policy);
2350         intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2351
2352         return 0;
2353 }
2354
2355 /* Use of trace in passive mode:
2356  *
2357  * In passive mode the trace core_busy field (also known as the
2358  * performance field, and lablelled as such on the graphs; also known as
2359  * core_avg_perf) is not needed and so is re-assigned to indicate if the
2360  * driver call was via the normal or fast switch path. Various graphs
2361  * output from the intel_pstate_tracer.py utility that include core_busy
2362  * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2363  * so we use 10 to indicate the the normal path through the driver, and
2364  * 90 to indicate the fast switch path through the driver.
2365  * The scaled_busy field is not used, and is set to 0.
2366  */
2367
2368 #define INTEL_PSTATE_TRACE_TARGET 10
2369 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2370
2371 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2372 {
2373         struct sample *sample;
2374
2375         if (!trace_pstate_sample_enabled())
2376                 return;
2377
2378         if (!intel_pstate_sample(cpu, ktime_get()))
2379                 return;
2380
2381         sample = &cpu->sample;
2382         trace_pstate_sample(trace_type,
2383                 0,
2384                 old_pstate,
2385                 cpu->pstate.current_pstate,
2386                 sample->mperf,
2387                 sample->aperf,
2388                 sample->tsc,
2389                 get_avg_frequency(cpu),
2390                 fp_toint(cpu->iowait_boost * 100));
2391 }
2392
2393 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2394                                 unsigned int target_freq,
2395                                 unsigned int relation)
2396 {
2397         struct cpudata *cpu = all_cpu_data[policy->cpu];
2398         struct cpufreq_freqs freqs;
2399         int target_pstate, old_pstate;
2400
2401         update_turbo_state();
2402
2403         freqs.old = policy->cur;
2404         freqs.new = target_freq;
2405
2406         cpufreq_freq_transition_begin(policy, &freqs);
2407         switch (relation) {
2408         case CPUFREQ_RELATION_L:
2409                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2410                 break;
2411         case CPUFREQ_RELATION_H:
2412                 target_pstate = freqs.new / cpu->pstate.scaling;
2413                 break;
2414         default:
2415                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2416                 break;
2417         }
2418         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2419         old_pstate = cpu->pstate.current_pstate;
2420         if (target_pstate != cpu->pstate.current_pstate) {
2421                 cpu->pstate.current_pstate = target_pstate;
2422                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2423                               pstate_funcs.get_val(cpu, target_pstate));
2424         }
2425         freqs.new = target_pstate * cpu->pstate.scaling;
2426         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2427         cpufreq_freq_transition_end(policy, &freqs, false);
2428
2429         return 0;
2430 }
2431
2432 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2433                                               unsigned int target_freq)
2434 {
2435         struct cpudata *cpu = all_cpu_data[policy->cpu];
2436         int target_pstate, old_pstate;
2437
2438         update_turbo_state();
2439
2440         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2441         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2442         old_pstate = cpu->pstate.current_pstate;
2443         intel_pstate_update_pstate(cpu, target_pstate);
2444         intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2445         return target_pstate * cpu->pstate.scaling;
2446 }
2447
2448 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2449 {
2450         int max_state, turbo_max, min_freq, max_freq, ret;
2451         struct freq_qos_request *req;
2452         struct cpudata *cpu;
2453         struct device *dev;
2454
2455         dev = get_cpu_device(policy->cpu);
2456         if (!dev)
2457                 return -ENODEV;
2458
2459         ret = __intel_pstate_cpu_init(policy);
2460         if (ret)
2461                 return ret;
2462
2463         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2464         policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2465         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2466         policy->cur = policy->cpuinfo.min_freq;
2467
2468         req = kcalloc(2, sizeof(*req), GFP_KERNEL);
2469         if (!req) {
2470                 ret = -ENOMEM;
2471                 goto pstate_exit;
2472         }
2473
2474         cpu = all_cpu_data[policy->cpu];
2475
2476         if (hwp_active)
2477                 intel_pstate_get_hwp_max(policy->cpu, &turbo_max, &max_state);
2478         else
2479                 turbo_max = cpu->pstate.turbo_pstate;
2480
2481         min_freq = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2482         min_freq *= cpu->pstate.scaling;
2483         max_freq = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2484         max_freq *= cpu->pstate.scaling;
2485
2486         ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
2487                                    min_freq);
2488         if (ret < 0) {
2489                 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
2490                 goto free_req;
2491         }
2492
2493         ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
2494                                    max_freq);
2495         if (ret < 0) {
2496                 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
2497                 goto remove_min_req;
2498         }
2499
2500         policy->driver_data = req;
2501
2502         return 0;
2503
2504 remove_min_req:
2505         freq_qos_remove_request(req);
2506 free_req:
2507         kfree(req);
2508 pstate_exit:
2509         intel_pstate_exit_perf_limits(policy);
2510
2511         return ret;
2512 }
2513
2514 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
2515 {
2516         struct freq_qos_request *req;
2517
2518         req = policy->driver_data;
2519
2520         freq_qos_remove_request(req + 1);
2521         freq_qos_remove_request(req);
2522         kfree(req);
2523
2524         return intel_pstate_cpu_exit(policy);
2525 }
2526
2527 static struct cpufreq_driver intel_cpufreq = {
2528         .flags          = CPUFREQ_CONST_LOOPS,
2529         .verify         = intel_cpufreq_verify_policy,
2530         .target         = intel_cpufreq_target,
2531         .fast_switch    = intel_cpufreq_fast_switch,
2532         .init           = intel_cpufreq_cpu_init,
2533         .exit           = intel_cpufreq_cpu_exit,
2534         .stop_cpu       = intel_cpufreq_stop_cpu,
2535         .update_limits  = intel_pstate_update_limits,
2536         .name           = "intel_cpufreq",
2537 };
2538
2539 static struct cpufreq_driver *default_driver;
2540
2541 static void intel_pstate_driver_cleanup(void)
2542 {
2543         unsigned int cpu;
2544
2545         get_online_cpus();
2546         for_each_online_cpu(cpu) {
2547                 if (all_cpu_data[cpu]) {
2548                         if (intel_pstate_driver == &intel_pstate)
2549                                 intel_pstate_clear_update_util_hook(cpu);
2550
2551                         kfree(all_cpu_data[cpu]);
2552                         all_cpu_data[cpu] = NULL;
2553                 }
2554         }
2555         put_online_cpus();
2556         intel_pstate_driver = NULL;
2557 }
2558
2559 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2560 {
2561         int ret;
2562
2563         memset(&global, 0, sizeof(global));
2564         global.max_perf_pct = 100;
2565
2566         intel_pstate_driver = driver;
2567         ret = cpufreq_register_driver(intel_pstate_driver);
2568         if (ret) {
2569                 intel_pstate_driver_cleanup();
2570                 return ret;
2571         }
2572
2573         global.min_perf_pct = min_perf_pct_min();
2574
2575         return 0;
2576 }
2577
2578 static int intel_pstate_unregister_driver(void)
2579 {
2580         if (hwp_active)
2581                 return -EBUSY;
2582
2583         cpufreq_unregister_driver(intel_pstate_driver);
2584         intel_pstate_driver_cleanup();
2585
2586         return 0;
2587 }
2588
2589 static ssize_t intel_pstate_show_status(char *buf)
2590 {
2591         if (!intel_pstate_driver)
2592                 return sprintf(buf, "off\n");
2593
2594         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2595                                         "active" : "passive");
2596 }
2597
2598 static int intel_pstate_update_status(const char *buf, size_t size)
2599 {
2600         int ret;
2601
2602         if (size == 3 && !strncmp(buf, "off", size))
2603                 return intel_pstate_driver ?
2604                         intel_pstate_unregister_driver() : -EINVAL;
2605
2606         if (size == 6 && !strncmp(buf, "active", size)) {
2607                 if (intel_pstate_driver) {
2608                         if (intel_pstate_driver == &intel_pstate)
2609                                 return 0;
2610
2611                         ret = intel_pstate_unregister_driver();
2612                         if (ret)
2613                                 return ret;
2614                 }
2615
2616                 return intel_pstate_register_driver(&intel_pstate);
2617         }
2618
2619         if (size == 7 && !strncmp(buf, "passive", size)) {
2620                 if (intel_pstate_driver) {
2621                         if (intel_pstate_driver == &intel_cpufreq)
2622                                 return 0;
2623
2624                         ret = intel_pstate_unregister_driver();
2625                         if (ret)
2626                                 return ret;
2627                 }
2628
2629                 return intel_pstate_register_driver(&intel_cpufreq);
2630         }
2631
2632         return -EINVAL;
2633 }
2634
2635 static int no_load __initdata;
2636 static int no_hwp __initdata;
2637 static int hwp_only __initdata;
2638 static unsigned int force_load __initdata;
2639
2640 static int __init intel_pstate_msrs_not_valid(void)
2641 {
2642         if (!pstate_funcs.get_max() ||
2643             !pstate_funcs.get_min() ||
2644             !pstate_funcs.get_turbo())
2645                 return -ENODEV;
2646
2647         return 0;
2648 }
2649
2650 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2651 {
2652         pstate_funcs.get_max   = funcs->get_max;
2653         pstate_funcs.get_max_physical = funcs->get_max_physical;
2654         pstate_funcs.get_min   = funcs->get_min;
2655         pstate_funcs.get_turbo = funcs->get_turbo;
2656         pstate_funcs.get_scaling = funcs->get_scaling;
2657         pstate_funcs.get_val   = funcs->get_val;
2658         pstate_funcs.get_vid   = funcs->get_vid;
2659         pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2660 }
2661
2662 #ifdef CONFIG_ACPI
2663
2664 static bool __init intel_pstate_no_acpi_pss(void)
2665 {
2666         int i;
2667
2668         for_each_possible_cpu(i) {
2669                 acpi_status status;
2670                 union acpi_object *pss;
2671                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2672                 struct acpi_processor *pr = per_cpu(processors, i);
2673
2674                 if (!pr)
2675                         continue;
2676
2677                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2678                 if (ACPI_FAILURE(status))
2679                         continue;
2680
2681                 pss = buffer.pointer;
2682                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2683                         kfree(pss);
2684                         return false;
2685                 }
2686
2687                 kfree(pss);
2688         }
2689
2690         pr_debug("ACPI _PSS not found\n");
2691         return true;
2692 }
2693
2694 static bool __init intel_pstate_no_acpi_pcch(void)
2695 {
2696         acpi_status status;
2697         acpi_handle handle;
2698
2699         status = acpi_get_handle(NULL, "\\_SB", &handle);
2700         if (ACPI_FAILURE(status))
2701                 goto not_found;
2702
2703         if (acpi_has_method(handle, "PCCH"))
2704                 return false;
2705
2706 not_found:
2707         pr_debug("ACPI PCCH not found\n");
2708         return true;
2709 }
2710
2711 static bool __init intel_pstate_has_acpi_ppc(void)
2712 {
2713         int i;
2714
2715         for_each_possible_cpu(i) {
2716                 struct acpi_processor *pr = per_cpu(processors, i);
2717
2718                 if (!pr)
2719                         continue;
2720                 if (acpi_has_method(pr->handle, "_PPC"))
2721                         return true;
2722         }
2723         pr_debug("ACPI _PPC not found\n");
2724         return false;
2725 }
2726
2727 enum {
2728         PSS,
2729         PPC,
2730 };
2731
2732 /* Hardware vendor-specific info that has its own power management modes */
2733 static struct acpi_platform_list plat_info[] __initdata = {
2734         {"HP    ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
2735         {"ORACLE", "X4-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2736         {"ORACLE", "X4-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2737         {"ORACLE", "X4-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2738         {"ORACLE", "X3-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2739         {"ORACLE", "X3-2L   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2740         {"ORACLE", "X3-2B   ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2741         {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2742         {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2743         {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2744         {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2745         {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2746         {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2747         {"ORACLE", "X6-2    ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2748         {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
2749         { } /* End */
2750 };
2751
2752 #define BITMASK_OOB     (BIT(8) | BIT(18))
2753
2754 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2755 {
2756         const struct x86_cpu_id *id;
2757         u64 misc_pwr;
2758         int idx;
2759
2760         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2761         if (id) {
2762                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2763                 if (misc_pwr & BITMASK_OOB) {
2764                         pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
2765                         pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
2766                         return true;
2767                 }
2768         }
2769
2770         idx = acpi_match_platform_list(plat_info);
2771         if (idx < 0)
2772                 return false;
2773
2774         switch (plat_info[idx].data) {
2775         case PSS:
2776                 if (!intel_pstate_no_acpi_pss())
2777                         return false;
2778
2779                 return intel_pstate_no_acpi_pcch();
2780         case PPC:
2781                 return intel_pstate_has_acpi_ppc() && !force_load;
2782         }
2783
2784         return false;
2785 }
2786
2787 static void intel_pstate_request_control_from_smm(void)
2788 {
2789         /*
2790          * It may be unsafe to request P-states control from SMM if _PPC support
2791          * has not been enabled.
2792          */
2793         if (acpi_ppc)
2794                 acpi_processor_pstate_control();
2795 }
2796 #else /* CONFIG_ACPI not enabled */
2797 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2798 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2799 static inline void intel_pstate_request_control_from_smm(void) {}
2800 #endif /* CONFIG_ACPI */
2801
2802 #define INTEL_PSTATE_HWP_BROADWELL      0x01
2803
2804 #define X86_MATCH_HWP(model, hwp_mode)                                  \
2805         X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2806                                            X86_FEATURE_HWP, hwp_mode)
2807
2808 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2809         X86_MATCH_HWP(BROADWELL_X,      INTEL_PSTATE_HWP_BROADWELL),
2810         X86_MATCH_HWP(BROADWELL_D,      INTEL_PSTATE_HWP_BROADWELL),
2811         X86_MATCH_HWP(ANY,              0),
2812         {}
2813 };
2814
2815 static int __init intel_pstate_init(void)
2816 {
2817         const struct x86_cpu_id *id;
2818         int rc;
2819
2820         if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2821                 return -ENODEV;
2822
2823         if (no_load)
2824                 return -ENODEV;
2825
2826         id = x86_match_cpu(hwp_support_ids);
2827         if (id) {
2828                 copy_cpu_funcs(&core_funcs);
2829                 /*
2830                  * Avoid enabling HWP for processors without EPP support,
2831                  * because that means incomplete HWP implementation which is a
2832                  * corner case and supporting it is generally problematic.
2833                  */
2834                 if (!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) {
2835                         hwp_active++;
2836                         hwp_mode_bdw = id->driver_data;
2837                         intel_pstate.attr = hwp_cpufreq_attrs;
2838                         default_driver = &intel_pstate;
2839                         goto hwp_cpu_matched;
2840                 }
2841         } else {
2842                 id = x86_match_cpu(intel_pstate_cpu_ids);
2843                 if (!id) {
2844                         pr_info("CPU model not supported\n");
2845                         return -ENODEV;
2846                 }
2847
2848                 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2849         }
2850
2851         if (intel_pstate_msrs_not_valid()) {
2852                 pr_info("Invalid MSRs\n");
2853                 return -ENODEV;
2854         }
2855         /* Without HWP start in the passive mode. */
2856         if (!default_driver)
2857                 default_driver = &intel_cpufreq;
2858
2859 hwp_cpu_matched:
2860         /*
2861          * The Intel pstate driver will be ignored if the platform
2862          * firmware has its own power management modes.
2863          */
2864         if (intel_pstate_platform_pwr_mgmt_exists()) {
2865                 pr_info("P-states controlled by the platform\n");
2866                 return -ENODEV;
2867         }
2868
2869         if (!hwp_active && hwp_only)
2870                 return -ENOTSUPP;
2871
2872         pr_info("Intel P-state driver initializing\n");
2873
2874         all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2875         if (!all_cpu_data)
2876                 return -ENOMEM;
2877
2878         intel_pstate_request_control_from_smm();
2879
2880         intel_pstate_sysfs_expose_params();
2881
2882         mutex_lock(&intel_pstate_driver_lock);
2883         rc = intel_pstate_register_driver(default_driver);
2884         mutex_unlock(&intel_pstate_driver_lock);
2885         if (rc)
2886                 return rc;
2887
2888         if (hwp_active) {
2889                 const struct x86_cpu_id *id;
2890
2891                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2892                 if (id) {
2893                         set_power_ctl_ee_state(false);
2894                         pr_info("Disabling energy efficiency optimization\n");
2895                 }
2896
2897                 pr_info("HWP enabled\n");
2898         }
2899
2900         return 0;
2901 }
2902 device_initcall(intel_pstate_init);
2903
2904 static int __init intel_pstate_setup(char *str)
2905 {
2906         if (!str)
2907                 return -EINVAL;
2908
2909         if (!strcmp(str, "disable")) {
2910                 no_load = 1;
2911         } else if (!strcmp(str, "active")) {
2912                 default_driver = &intel_pstate;
2913         } else if (!strcmp(str, "passive")) {
2914                 default_driver = &intel_cpufreq;
2915                 no_hwp = 1;
2916         }
2917         if (!strcmp(str, "no_hwp")) {
2918                 pr_info("HWP disabled\n");
2919                 no_hwp = 1;
2920         }
2921         if (!strcmp(str, "force"))
2922                 force_load = 1;
2923         if (!strcmp(str, "hwp_only"))
2924                 hwp_only = 1;
2925         if (!strcmp(str, "per_cpu_perf_limits"))
2926                 per_cpu_limits = true;
2927
2928 #ifdef CONFIG_ACPI
2929         if (!strcmp(str, "support_acpi_ppc"))
2930                 acpi_ppc = true;
2931 #endif
2932
2933         return 0;
2934 }
2935 early_param("intel_pstate", intel_pstate_setup);
2936
2937 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2938 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2939 MODULE_LICENSE("GPL");