drivers/cpufreq/intel_pstate.c

   1 /*
   2  * intel_pstate.c: Native P state management for Intel processors
   3  *
   4  * (C) Copyright 2012 Intel Corporation
   5  * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; version 2
  10  * of the License.
  11  */
  12
  13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  14
  15 #include <linux/kernel.h>
  16 #include <linux/kernel_stat.h>
  17 #include <linux/module.h>
  18 #include <linux/ktime.h>
  19 #include <linux/hrtimer.h>
  20 #include <linux/tick.h>
  21 #include <linux/slab.h>
  22 #include <linux/sched.h>
  23 #include <linux/list.h>
  24 #include <linux/cpu.h>
  25 #include <linux/cpufreq.h>
  26 #include <linux/sysfs.h>
  27 #include <linux/types.h>
  28 #include <linux/fs.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/acpi.h>
  31 #include <linux/vmalloc.h>
  32 #include <trace/events/power.h>
  33
  34 #include <asm/div64.h>
  35 #include <asm/msr.h>
  36 #include <asm/cpu_device_id.h>
  37 #include <asm/cpufeature.h>
  38 #include <asm/intel-family.h>
  39
  40 #define INTEL_CPUFREQ_TRANSITION_LATENCY        20000
  41
  42 #define ATOM_RATIOS             0x66a
  43 #define ATOM_VIDS               0x66b
  44 #define ATOM_TURBO_RATIOS       0x66c
  45 #define ATOM_TURBO_VIDS         0x66d
  46
  47 #ifdef CONFIG_ACPI
  48 #include <acpi/processor.h>
  49 #include <acpi/cppc_acpi.h>
  50 #endif
  51
  52 #define FRAC_BITS 8
  53 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
  54 #define fp_toint(X) ((X) >> FRAC_BITS)
  55
  56 #define EXT_BITS 6
  57 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
  58 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
  59 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
  60
  61 static inline int32_t mul_fp(int32_t x, int32_t y)
  62 {
  63         return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
  64 }
  65
  66 static inline int32_t div_fp(s64 x, s64 y)
  67 {
  68         return div64_s64((int64_t)x << FRAC_BITS, y);
  69 }
  70
  71 static inline int ceiling_fp(int32_t x)
  72 {
  73         int mask, ret;
  74
  75         ret = fp_toint(x);
  76         mask = (1 << FRAC_BITS) - 1;
  77         if (x & mask)
  78                 ret += 1;
  79         return ret;
  80 }
  81
  82 static inline u64 mul_ext_fp(u64 x, u64 y)
  83 {
  84         return (x * y) >> EXT_FRAC_BITS;
  85 }
  86
  87 static inline u64 div_ext_fp(u64 x, u64 y)
  88 {
  89         return div64_u64(x << EXT_FRAC_BITS, y);
  90 }
  91
  92 /**
  93  * struct sample -      Store performance sample
  94  * @core_avg_perf:      Ratio of APERF/MPERF which is the actual average
  95  *                      performance during last sample period
  96  * @busy_scaled:        Scaled busy value which is used to calculate next
  97  *                      P state. This can be different than core_avg_perf
  98  *                      to account for cpu idle period
  99  * @aperf:              Difference of actual performance frequency clock count
 100  *                      read from APERF MSR between last and current sample
 101  * @mperf:              Difference of maximum performance frequency clock count
 102  *                      read from MPERF MSR between last and current sample
 103  * @tsc:                Difference of time stamp counter between last and
 104  *                      current sample
 105  * @time:               Current time from scheduler
 106  *
 107  * This structure is used in the cpudata structure to store performance sample
 108  * data for choosing next P State.
 109  */
 110 struct sample {
 111         int32_t core_avg_perf;
 112         int32_t busy_scaled;
 113         u64 aperf;
 114         u64 mperf;
 115         u64 tsc;
 116         u64 time;
 117 };
 118
 119 /**
 120  * struct pstate_data - Store P state data
 121  * @current_pstate:     Current requested P state
 122  * @min_pstate:         Min P state possible for this platform
 123  * @max_pstate:         Max P state possible for this platform
 124  * @max_pstate_physical:This is physical Max P state for a processor
 125  *                      This can be higher than the max_pstate which can
 126  *                      be limited by platform thermal design power limits
 127  * @scaling:            Scaling factor to  convert frequency to cpufreq
 128  *                      frequency units
 129  * @turbo_pstate:       Max Turbo P state possible for this platform
 130  * @max_freq:           @max_pstate frequency in cpufreq units
 131  * @turbo_freq:         @turbo_pstate frequency in cpufreq units
 132  *
 133  * Stores the per cpu model P state limits and current P state.
 134  */
 135 struct pstate_data {
 136         int     current_pstate;
 137         int     min_pstate;
 138         int     max_pstate;
 139         int     max_pstate_physical;
 140         int     scaling;
 141         int     turbo_pstate;
 142         unsigned int max_freq;
 143         unsigned int turbo_freq;
 144 };
 145
 146 /**
 147  * struct vid_data -    Stores voltage information data
 148  * @min:                VID data for this platform corresponding to
 149  *                      the lowest P state
 150  * @max:                VID data corresponding to the highest P State.
 151  * @turbo:              VID data for turbo P state
 152  * @ratio:              Ratio of (vid max - vid min) /
 153  *                      (max P state - Min P State)
 154  *
 155  * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
 156  * This data is used in Atom platforms, where in addition to target P state,
 157  * the voltage data needs to be specified to select next P State.
 158  */
 159 struct vid_data {
 160         int min;
 161         int max;
 162         int turbo;
 163         int32_t ratio;
 164 };
 165
 166 /**
 167  * struct _pid -        Stores PID data
 168  * @setpoint:           Target set point for busyness or performance
 169  * @integral:           Storage for accumulated error values
 170  * @p_gain:             PID proportional gain
 171  * @i_gain:             PID integral gain
 172  * @d_gain:             PID derivative gain
 173  * @deadband:           PID deadband
 174  * @last_err:           Last error storage for integral part of PID calculation
 175  *
 176  * Stores PID coefficients and last error for PID controller.
 177  */
 178 struct _pid {
 179         int setpoint;
 180         int32_t integral;
 181         int32_t p_gain;
 182         int32_t i_gain;
 183         int32_t d_gain;
 184         int deadband;
 185         int32_t last_err;
 186 };
 187
 188 /**
 189  * struct perf_limits - Store user and policy limits
 190  * @no_turbo:           User requested turbo state from intel_pstate sysfs
 191  * @turbo_disabled:     Platform turbo status either from msr
 192  *                      MSR_IA32_MISC_ENABLE or when maximum available pstate
 193  *                      matches the maximum turbo pstate
 194  * @max_perf_pct:       Effective maximum performance limit in percentage, this
 195  *                      is minimum of either limits enforced by cpufreq policy
 196  *                      or limits from user set limits via intel_pstate sysfs
 197  * @min_perf_pct:       Effective minimum performance limit in percentage, this
 198  *                      is maximum of either limits enforced by cpufreq policy
 199  *                      or limits from user set limits via intel_pstate sysfs
 200  * @max_perf:           This is a scaled value between 0 to 255 for max_perf_pct
 201  *                      This value is used to limit max pstate
 202  * @min_perf:           This is a scaled value between 0 to 255 for min_perf_pct
 203  *                      This value is used to limit min pstate
 204  * @max_policy_pct:     The maximum performance in percentage enforced by
 205  *                      cpufreq setpolicy interface
 206  * @max_sysfs_pct:      The maximum performance in percentage enforced by
 207  *                      intel pstate sysfs interface, unused when per cpu
 208  *                      controls are enforced
 209  * @min_policy_pct:     The minimum performance in percentage enforced by
 210  *                      cpufreq setpolicy interface
 211  * @min_sysfs_pct:      The minimum performance in percentage enforced by
 212  *                      intel pstate sysfs interface, unused when per cpu
 213  *                      controls are enforced
 214  *
 215  * Storage for user and policy defined limits.
 216  */
 217 struct perf_limits {
 218         int no_turbo;
 219         int turbo_disabled;
 220         int max_perf_pct;
 221         int min_perf_pct;
 222         int32_t max_perf;
 223         int32_t min_perf;
 224         int max_policy_pct;
 225         int max_sysfs_pct;
 226         int min_policy_pct;
 227         int min_sysfs_pct;
 228 };
 229
 230 /**
 231  * struct cpudata -     Per CPU instance data storage
 232  * @cpu:                CPU number for this instance data
 233  * @policy:             CPUFreq policy value
 234  * @update_util:        CPUFreq utility callback information
 235  * @update_util_set:    CPUFreq utility callback is set
 236  * @iowait_boost:       iowait-related boost fraction
 237  * @last_update:        Time of the last update.
 238  * @pstate:             Stores P state limits for this CPU
 239  * @vid:                Stores VID limits for this CPU
 240  * @pid:                Stores PID parameters for this CPU
 241  * @last_sample_time:   Last Sample time
 242  * @prev_aperf:         Last APERF value read from APERF MSR
 243  * @prev_mperf:         Last MPERF value read from MPERF MSR
 244  * @prev_tsc:           Last timestamp counter (TSC) value
 245  * @prev_cummulative_iowait: IO Wait time difference from last and
 246  *                      current sample
 247  * @sample:             Storage for storing last Sample data
 248  * @perf_limits:        Pointer to perf_limit unique to this CPU
 249  *                      Not all field in the structure are applicable
 250  *                      when per cpu controls are enforced
 251  * @acpi_perf_data:     Stores ACPI perf information read from _PSS
 252  * @valid_pss_table:    Set to true for valid ACPI _PSS entries found
 253  * @epp_powersave:      Last saved HWP energy performance preference
 254  *                      (EPP) or energy performance bias (EPB),
 255  *                      when policy switched to performance
 256  * @epp_policy:         Last saved policy used to set EPP/EPB
 257  * @epp_default:        Power on default HWP energy performance
 258  *                      preference/bias
 259  * @epp_saved:          Saved EPP/EPB during system suspend or CPU offline
 260  *                      operation
 261  *
 262  * This structure stores per CPU instance data for all CPUs.
 263  */
 264 struct cpudata {
 265         int cpu;
 266
 267         unsigned int policy;
 268         struct update_util_data update_util;
 269         bool   update_util_set;
 270
 271         struct pstate_data pstate;
 272         struct vid_data vid;
 273         struct _pid pid;
 274
 275         u64     last_update;
 276         u64     last_sample_time;
 277         u64     prev_aperf;
 278         u64     prev_mperf;
 279         u64     prev_tsc;
 280         u64     prev_cummulative_iowait;
 281         struct sample sample;
 282         struct perf_limits *perf_limits;
 283 #ifdef CONFIG_ACPI
 284         struct acpi_processor_performance acpi_perf_data;
 285         bool valid_pss_table;
 286 #endif
 287         unsigned int iowait_boost;
 288         s16 epp_powersave;
 289         s16 epp_policy;
 290         s16 epp_default;
 291         s16 epp_saved;
 292 };
 293
 294 static struct cpudata **all_cpu_data;
 295
 296 /**
 297  * struct pstate_adjust_policy - Stores static PID configuration data
 298  * @sample_rate_ms:     PID calculation sample rate in ms
 299  * @sample_rate_ns:     Sample rate calculation in ns
 300  * @deadband:           PID deadband
 301  * @setpoint:           PID Setpoint
 302  * @p_gain_pct:         PID proportional gain
 303  * @i_gain_pct:         PID integral gain
 304  * @d_gain_pct:         PID derivative gain
 305  *
 306  * Stores per CPU model static PID configuration data.
 307  */
 308 struct pstate_adjust_policy {
 309         int sample_rate_ms;
 310         s64 sample_rate_ns;
 311         int deadband;
 312         int setpoint;
 313         int p_gain_pct;
 314         int d_gain_pct;
 315         int i_gain_pct;
 316 };
 317
 318 /**
 319  * struct pstate_funcs - Per CPU model specific callbacks
 320  * @get_max:            Callback to get maximum non turbo effective P state
 321  * @get_max_physical:   Callback to get maximum non turbo physical P state
 322  * @get_min:            Callback to get minimum P state
 323  * @get_turbo:          Callback to get turbo P state
 324  * @get_scaling:        Callback to get frequency scaling factor
 325  * @get_val:            Callback to convert P state to actual MSR write value
 326  * @get_vid:            Callback to get VID data for Atom platforms
 327  * @get_target_pstate:  Callback to a function to calculate next P state to use
 328  *
 329  * Core and Atom CPU models have different way to get P State limits. This
 330  * structure is used to store those callbacks.
 331  */
 332 struct pstate_funcs {
 333         int (*get_max)(void);
 334         int (*get_max_physical)(void);
 335         int (*get_min)(void);
 336         int (*get_turbo)(void);
 337         int (*get_scaling)(void);
 338         u64 (*get_val)(struct cpudata*, int pstate);
 339         void (*get_vid)(struct cpudata *);
 340         int32_t (*get_target_pstate)(struct cpudata *);
 341 };
 342
 343 /**
 344  * struct cpu_defaults- Per CPU model default config data
 345  * @pid_policy: PID config data
 346  * @funcs:              Callback function data
 347  */
 348 struct cpu_defaults {
 349         struct pstate_adjust_policy pid_policy;
 350         struct pstate_funcs funcs;
 351 };
 352
 353 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu);
 354 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu);
 355
 356 static struct pstate_adjust_policy pid_params __read_mostly;
 357 static struct pstate_funcs pstate_funcs __read_mostly;
 358 static int hwp_active __read_mostly;
 359 static bool per_cpu_limits __read_mostly;
 360
 361 static bool driver_registered __read_mostly;
 362
 363 #ifdef CONFIG_ACPI
 364 static bool acpi_ppc;
 365 #endif
 366
 367 static struct perf_limits performance_limits;
 368 static struct perf_limits powersave_limits;
 369 static struct perf_limits *limits;
 370
 371 static void intel_pstate_init_limits(struct perf_limits *limits)
 372 {
 373         memset(limits, 0, sizeof(*limits));
 374         limits->max_perf_pct = 100;
 375         limits->max_perf = int_ext_tofp(1);
 376         limits->max_policy_pct = 100;
 377         limits->max_sysfs_pct = 100;
 378 }
 379
 380 static void intel_pstate_set_performance_limits(struct perf_limits *limits)
 381 {
 382         intel_pstate_init_limits(limits);
 383         limits->min_perf_pct = 100;
 384         limits->min_perf = int_ext_tofp(1);
 385 }
 386
 387 static DEFINE_MUTEX(intel_pstate_driver_lock);
 388 static DEFINE_MUTEX(intel_pstate_limits_lock);
 389
 390 #ifdef CONFIG_ACPI
 391
 392 static bool intel_pstate_get_ppc_enable_status(void)
 393 {
 394         if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
 395             acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
 396                 return true;
 397
 398         return acpi_ppc;
 399 }
 400
 401 #ifdef CONFIG_ACPI_CPPC_LIB
 402
 403 /* The work item is needed to avoid CPU hotplug locking issues */
 404 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
 405 {
 406         sched_set_itmt_support();
 407 }
 408
 409 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
 410
 411 static void intel_pstate_set_itmt_prio(int cpu)
 412 {
 413         struct cppc_perf_caps cppc_perf;
 414         static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
 415         int ret;
 416
 417         ret = cppc_get_perf_caps(cpu, &cppc_perf);
 418         if (ret)
 419                 return;
 420
 421         /*
 422          * The priorities can be set regardless of whether or not
 423          * sched_set_itmt_support(true) has been called and it is valid to
 424          * update them at any time after it has been called.
 425          */
 426         sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
 427
 428         if (max_highest_perf <= min_highest_perf) {
 429                 if (cppc_perf.highest_perf > max_highest_perf)
 430                         max_highest_perf = cppc_perf.highest_perf;
 431
 432                 if (cppc_perf.highest_perf < min_highest_perf)
 433                         min_highest_perf = cppc_perf.highest_perf;
 434
 435                 if (max_highest_perf > min_highest_perf) {
 436                         /*
 437                          * This code can be run during CPU online under the
 438                          * CPU hotplug locks, so sched_set_itmt_support()
 439                          * cannot be called from here.  Queue up a work item
 440                          * to invoke it.
 441                          */
 442                         schedule_work(&sched_itmt_work);
 443                 }
 444         }
 445 }
 446 #else
 447 static void intel_pstate_set_itmt_prio(int cpu)
 448 {
 449 }
 450 #endif
 451
 452 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 453 {
 454         struct cpudata *cpu;
 455         int ret;
 456         int i;
 457
 458         if (hwp_active) {
 459                 intel_pstate_set_itmt_prio(policy->cpu);
 460                 return;
 461         }
 462
 463         if (!intel_pstate_get_ppc_enable_status())
 464                 return;
 465
 466         cpu = all_cpu_data[policy->cpu];
 467
 468         ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
 469                                                   policy->cpu);
 470         if (ret)
 471                 return;
 472
 473         /*
 474          * Check if the control value in _PSS is for PERF_CTL MSR, which should
 475          * guarantee that the states returned by it map to the states in our
 476          * list directly.
 477          */
 478         if (cpu->acpi_perf_data.control_register.space_id !=
 479                                                 ACPI_ADR_SPACE_FIXED_HARDWARE)
 480                 goto err;
 481
 482         /*
 483          * If there is only one entry _PSS, simply ignore _PSS and continue as
 484          * usual without taking _PSS into account
 485          */
 486         if (cpu->acpi_perf_data.state_count < 2)
 487                 goto err;
 488
 489         pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
 490         for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
 491                 pr_debug("     %cP%d: %u MHz, %u mW, 0x%x\n",
 492                          (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
 493                          (u32) cpu->acpi_perf_data.states[i].core_frequency,
 494                          (u32) cpu->acpi_perf_data.states[i].power,
 495                          (u32) cpu->acpi_perf_data.states[i].control);
 496         }
 497
 498         /*
 499          * The _PSS table doesn't contain whole turbo frequency range.
 500          * This just contains +1 MHZ above the max non turbo frequency,
 501          * with control value corresponding to max turbo ratio. But
 502          * when cpufreq set policy is called, it will call with this
 503          * max frequency, which will cause a reduced performance as
 504          * this driver uses real max turbo frequency as the max
 505          * frequency. So correct this frequency in _PSS table to
 506          * correct max turbo frequency based on the turbo state.
 507          * Also need to convert to MHz as _PSS freq is in MHz.
 508          */
 509         if (!limits->turbo_disabled)
 510                 cpu->acpi_perf_data.states[0].core_frequency =
 511                                         policy->cpuinfo.max_freq / 1000;
 512         cpu->valid_pss_table = true;
 513         pr_debug("_PPC limits will be enforced\n");
 514
 515         return;
 516
 517  err:
 518         cpu->valid_pss_table = false;
 519         acpi_processor_unregister_performance(policy->cpu);
 520 }
 521
 522 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 523 {
 524         struct cpudata *cpu;
 525
 526         cpu = all_cpu_data[policy->cpu];
 527         if (!cpu->valid_pss_table)
 528                 return;
 529
 530         acpi_processor_unregister_performance(policy->cpu);
 531 }
 532 #else
 533 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
 534 {
 535 }
 536
 537 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
 538 {
 539 }
 540 #endif
 541
 542 static inline void pid_reset(struct _pid *pid, int setpoint, int busy,
 543                              int deadband, int integral) {
 544         pid->setpoint = int_tofp(setpoint);
 545         pid->deadband  = int_tofp(deadband);
 546         pid->integral  = int_tofp(integral);
 547         pid->last_err  = int_tofp(setpoint) - int_tofp(busy);
 548 }
 549
 550 static inline void pid_p_gain_set(struct _pid *pid, int percent)
 551 {
 552         pid->p_gain = div_fp(percent, 100);
 553 }
 554
 555 static inline void pid_i_gain_set(struct _pid *pid, int percent)
 556 {
 557         pid->i_gain = div_fp(percent, 100);
 558 }
 559
 560 static inline void pid_d_gain_set(struct _pid *pid, int percent)
 561 {
 562         pid->d_gain = div_fp(percent, 100);
 563 }
 564
 565 static signed int pid_calc(struct _pid *pid, int32_t busy)
 566 {
 567         signed int result;
 568         int32_t pterm, dterm, fp_error;
 569         int32_t integral_limit;
 570
 571         fp_error = pid->setpoint - busy;
 572
 573         if (abs(fp_error) <= pid->deadband)
 574                 return 0;
 575
 576         pterm = mul_fp(pid->p_gain, fp_error);
 577
 578         pid->integral += fp_error;
 579
 580         /*
 581          * We limit the integral here so that it will never
 582          * get higher than 30.  This prevents it from becoming
 583          * too large an input over long periods of time and allows
 584          * it to get factored out sooner.
 585          *
 586          * The value of 30 was chosen through experimentation.
 587          */
 588         integral_limit = int_tofp(30);
 589         if (pid->integral > integral_limit)
 590                 pid->integral = integral_limit;
 591         if (pid->integral < -integral_limit)
 592                 pid->integral = -integral_limit;
 593
 594         dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
 595         pid->last_err = fp_error;
 596
 597         result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
 598         result = result + (1 << (FRAC_BITS-1));
 599         return (signed int)fp_toint(result);
 600 }
 601
 602 static inline void intel_pstate_busy_pid_reset(struct cpudata *cpu)
 603 {
 604         pid_p_gain_set(&cpu->pid, pid_params.p_gain_pct);
 605         pid_d_gain_set(&cpu->pid, pid_params.d_gain_pct);
 606         pid_i_gain_set(&cpu->pid, pid_params.i_gain_pct);
 607
 608         pid_reset(&cpu->pid, pid_params.setpoint, 100, pid_params.deadband, 0);
 609 }
 610
 611 static inline void intel_pstate_reset_all_pid(void)
 612 {
 613         unsigned int cpu;
 614
 615         for_each_online_cpu(cpu) {
 616                 if (all_cpu_data[cpu])
 617                         intel_pstate_busy_pid_reset(all_cpu_data[cpu]);
 618         }
 619 }
 620
 621 static inline void update_turbo_state(void)
 622 {
 623         u64 misc_en;
 624         struct cpudata *cpu;
 625
 626         cpu = all_cpu_data[0];
 627         rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
 628         limits->turbo_disabled =
 629                 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
 630                  cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
 631 }
 632
 633 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
 634 {
 635         u64 epb;
 636         int ret;
 637
 638         if (!static_cpu_has(X86_FEATURE_EPB))
 639                 return -ENXIO;
 640
 641         ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 642         if (ret)
 643                 return (s16)ret;
 644
 645         return (s16)(epb & 0x0f);
 646 }
 647
 648 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
 649 {
 650         s16 epp;
 651
 652         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 653                 /*
 654                  * When hwp_req_data is 0, means that caller didn't read
 655                  * MSR_HWP_REQUEST, so need to read and get EPP.
 656                  */
 657                 if (!hwp_req_data) {
 658                         epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
 659                                             &hwp_req_data);
 660                         if (epp)
 661                                 return epp;
 662                 }
 663                 epp = (hwp_req_data >> 24) & 0xff;
 664         } else {
 665                 /* When there is no EPP present, HWP uses EPB settings */
 666                 epp = intel_pstate_get_epb(cpu_data);
 667         }
 668
 669         return epp;
 670 }
 671
 672 static int intel_pstate_set_epb(int cpu, s16 pref)
 673 {
 674         u64 epb;
 675         int ret;
 676
 677         if (!static_cpu_has(X86_FEATURE_EPB))
 678                 return -ENXIO;
 679
 680         ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
 681         if (ret)
 682                 return ret;
 683
 684         epb = (epb & ~0x0f) | pref;
 685         wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
 686
 687         return 0;
 688 }
 689
 690 /*
 691  * EPP/EPB display strings corresponding to EPP index in the
 692  * energy_perf_strings[]
 693  *      index           String
 694  *-------------------------------------
 695  *      0               default
 696  *      1               performance
 697  *      2               balance_performance
 698  *      3               balance_power
 699  *      4               power
 700  */
 701 static const char * const energy_perf_strings[] = {
 702         "default",
 703         "performance",
 704         "balance_performance",
 705         "balance_power",
 706         "power",
 707         NULL
 708 };
 709
 710 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
 711 {
 712         s16 epp;
 713         int index = -EINVAL;
 714
 715         epp = intel_pstate_get_epp(cpu_data, 0);
 716         if (epp < 0)
 717                 return epp;
 718
 719         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 720                 /*
 721                  * Range:
 722                  *      0x00-0x3F       :       Performance
 723                  *      0x40-0x7F       :       Balance performance
 724                  *      0x80-0xBF       :       Balance power
 725                  *      0xC0-0xFF       :       Power
 726                  * The EPP is a 8 bit value, but our ranges restrict the
 727                  * value which can be set. Here only using top two bits
 728                  * effectively.
 729                  */
 730                 index = (epp >> 6) + 1;
 731         } else if (static_cpu_has(X86_FEATURE_EPB)) {
 732                 /*
 733                  * Range:
 734                  *      0x00-0x03       :       Performance
 735                  *      0x04-0x07       :       Balance performance
 736                  *      0x08-0x0B       :       Balance power
 737                  *      0x0C-0x0F       :       Power
 738                  * The EPB is a 4 bit value, but our ranges restrict the
 739                  * value which can be set. Here only using top two bits
 740                  * effectively.
 741                  */
 742                 index = (epp >> 2) + 1;
 743         }
 744
 745         return index;
 746 }
 747
 748 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
 749                                               int pref_index)
 750 {
 751         int epp = -EINVAL;
 752         int ret;
 753
 754         if (!pref_index)
 755                 epp = cpu_data->epp_default;
 756
 757         mutex_lock(&intel_pstate_limits_lock);
 758
 759         if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 760                 u64 value;
 761
 762                 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
 763                 if (ret)
 764                         goto return_pref;
 765
 766                 value &= ~GENMASK_ULL(31, 24);
 767
 768                 /*
 769                  * If epp is not default, convert from index into
 770                  * energy_perf_strings to epp value, by shifting 6
 771                  * bits left to use only top two bits in epp.
 772                  * The resultant epp need to shifted by 24 bits to
 773                  * epp position in MSR_HWP_REQUEST.
 774                  */
 775                 if (epp == -EINVAL)
 776                         epp = (pref_index - 1) << 6;
 777
 778                 value |= (u64)epp << 24;
 779                 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
 780         } else {
 781                 if (epp == -EINVAL)
 782                         epp = (pref_index - 1) << 2;
 783                 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
 784         }
 785 return_pref:
 786         mutex_unlock(&intel_pstate_limits_lock);
 787
 788         return ret;
 789 }
 790
 791 static ssize_t show_energy_performance_available_preferences(
 792                                 struct cpufreq_policy *policy, char *buf)
 793 {
 794         int i = 0;
 795         int ret = 0;
 796
 797         while (energy_perf_strings[i] != NULL)
 798                 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
 799
 800         ret += sprintf(&buf[ret], "\n");
 801
 802         return ret;
 803 }
 804
 805 cpufreq_freq_attr_ro(energy_performance_available_preferences);
 806
 807 static ssize_t store_energy_performance_preference(
 808                 struct cpufreq_policy *policy, const char *buf, size_t count)
 809 {
 810         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 811         char str_preference[21];
 812         int ret, i = 0;
 813
 814         ret = sscanf(buf, "%20s", str_preference);
 815         if (ret != 1)
 816                 return -EINVAL;
 817
 818         while (energy_perf_strings[i] != NULL) {
 819                 if (!strcmp(str_preference, energy_perf_strings[i])) {
 820                         intel_pstate_set_energy_pref_index(cpu_data, i);
 821                         return count;
 822                 }
 823                 ++i;
 824         }
 825
 826         return -EINVAL;
 827 }
 828
 829 static ssize_t show_energy_performance_preference(
 830                                 struct cpufreq_policy *policy, char *buf)
 831 {
 832         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 833         int preference;
 834
 835         preference = intel_pstate_get_energy_pref_index(cpu_data);
 836         if (preference < 0)
 837                 return preference;
 838
 839         return  sprintf(buf, "%s\n", energy_perf_strings[preference]);
 840 }
 841
 842 cpufreq_freq_attr_rw(energy_performance_preference);
 843
 844 static struct freq_attr *hwp_cpufreq_attrs[] = {
 845         &energy_performance_preference,
 846         &energy_performance_available_preferences,
 847         NULL,
 848 };
 849
 850 static void intel_pstate_hwp_set(struct cpufreq_policy *policy)
 851 {
 852         int min, hw_min, max, hw_max, cpu, range, adj_range;
 853         struct perf_limits *perf_limits = limits;
 854         u64 value, cap;
 855
 856         for_each_cpu(cpu, policy->cpus) {
 857                 int max_perf_pct, min_perf_pct;
 858                 struct cpudata *cpu_data = all_cpu_data[cpu];
 859                 s16 epp;
 860
 861                 if (per_cpu_limits)
 862                         perf_limits = all_cpu_data[cpu]->perf_limits;
 863
 864                 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
 865                 hw_min = HWP_LOWEST_PERF(cap);
 866                 if (limits->no_turbo)
 867                         hw_max = HWP_GUARANTEED_PERF(cap);
 868                 else
 869                         hw_max = HWP_HIGHEST_PERF(cap);
 870                 range = hw_max - hw_min;
 871
 872                 max_perf_pct = perf_limits->max_perf_pct;
 873                 min_perf_pct = perf_limits->min_perf_pct;
 874
 875                 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
 876                 adj_range = min_perf_pct * range / 100;
 877                 min = hw_min + adj_range;
 878                 value &= ~HWP_MIN_PERF(~0L);
 879                 value |= HWP_MIN_PERF(min);
 880
 881                 adj_range = max_perf_pct * range / 100;
 882                 max = hw_min + adj_range;
 883
 884                 value &= ~HWP_MAX_PERF(~0L);
 885                 value |= HWP_MAX_PERF(max);
 886
 887                 if (cpu_data->epp_policy == cpu_data->policy)
 888                         goto skip_epp;
 889
 890                 cpu_data->epp_policy = cpu_data->policy;
 891
 892                 if (cpu_data->epp_saved >= 0) {
 893                         epp = cpu_data->epp_saved;
 894                         cpu_data->epp_saved = -EINVAL;
 895                         goto update_epp;
 896                 }
 897
 898                 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
 899                         epp = intel_pstate_get_epp(cpu_data, value);
 900                         cpu_data->epp_powersave = epp;
 901                         /* If EPP read was failed, then don't try to write */
 902                         if (epp < 0)
 903                                 goto skip_epp;
 904
 905
 906                         epp = 0;
 907                 } else {
 908                         /* skip setting EPP, when saved value is invalid */
 909                         if (cpu_data->epp_powersave < 0)
 910                                 goto skip_epp;
 911
 912                         /*
 913                          * No need to restore EPP when it is not zero. This
 914                          * means:
 915                          *  - Policy is not changed
 916                          *  - user has manually changed
 917                          *  - Error reading EPB
 918                          */
 919                         epp = intel_pstate_get_epp(cpu_data, value);
 920                         if (epp)
 921                                 goto skip_epp;
 922
 923                         epp = cpu_data->epp_powersave;
 924                 }
 925 update_epp:
 926                 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
 927                         value &= ~GENMASK_ULL(31, 24);
 928                         value |= (u64)epp << 24;
 929                 } else {
 930                         intel_pstate_set_epb(cpu, epp);
 931                 }
 932 skip_epp:
 933                 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
 934         }
 935 }
 936
 937 static int intel_pstate_hwp_set_policy(struct cpufreq_policy *policy)
 938 {
 939         if (hwp_active)
 940                 intel_pstate_hwp_set(policy);
 941
 942         return 0;
 943 }
 944
 945 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
 946 {
 947         struct cpudata *cpu_data = all_cpu_data[policy->cpu];
 948
 949         if (!hwp_active)
 950                 return 0;
 951
 952         cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
 953
 954         return 0;
 955 }
 956
 957 static int intel_pstate_resume(struct cpufreq_policy *policy)
 958 {
 959         int ret;
 960
 961         if (!hwp_active)
 962                 return 0;
 963
 964         mutex_lock(&intel_pstate_limits_lock);
 965
 966         all_cpu_data[policy->cpu]->epp_policy = 0;
 967
 968         ret = intel_pstate_hwp_set_policy(policy);
 969
 970         mutex_unlock(&intel_pstate_limits_lock);
 971
 972         return ret;
 973 }
 974
 975 static void intel_pstate_update_policies(void)
 976 {
 977         int cpu;
 978
 979         for_each_possible_cpu(cpu)
 980                 cpufreq_update_policy(cpu);
 981 }
 982
 983 /************************** debugfs begin ************************/
 984 static int pid_param_set(void *data, u64 val)
 985 {
 986         *(u32 *)data = val;
 987         intel_pstate_reset_all_pid();
 988         return 0;
 989 }
 990
 991 static int pid_param_get(void *data, u64 *val)
 992 {
 993         *val = *(u32 *)data;
 994         return 0;
 995 }
 996 DEFINE_SIMPLE_ATTRIBUTE(fops_pid_param, pid_param_get, pid_param_set, "%llu\n");
 997
 998 static struct dentry *debugfs_parent;
 999
1000 struct pid_param {
1001         char *name;
1002         void *value;
1003         struct dentry *dentry;
1004 };
1005
1006 static struct pid_param pid_files[] = {
1007         {"sample_rate_ms", &pid_params.sample_rate_ms, },
1008         {"d_gain_pct", &pid_params.d_gain_pct, },
1009         {"i_gain_pct", &pid_params.i_gain_pct, },
1010         {"deadband", &pid_params.deadband, },
1011         {"setpoint", &pid_params.setpoint, },
1012         {"p_gain_pct", &pid_params.p_gain_pct, },
1013         {NULL, NULL, }
1014 };
1015
1016 static void intel_pstate_debug_expose_params(void)
1017 {
1018         int i;
1019
1020         debugfs_parent = debugfs_create_dir("pstate_snb", NULL);
1021         if (IS_ERR_OR_NULL(debugfs_parent))
1022                 return;
1023
1024         for (i = 0; pid_files[i].name; i++) {
1025                 struct dentry *dentry;
1026
1027                 dentry = debugfs_create_file(pid_files[i].name, 0660,
1028                                              debugfs_parent, pid_files[i].value,
1029                                              &fops_pid_param);
1030                 if (!IS_ERR(dentry))
1031                         pid_files[i].dentry = dentry;
1032         }
1033 }
1034
1035 static void intel_pstate_debug_hide_params(void)
1036 {
1037         int i;
1038
1039         if (IS_ERR_OR_NULL(debugfs_parent))
1040                 return;
1041
1042         for (i = 0; pid_files[i].name; i++) {
1043                 debugfs_remove(pid_files[i].dentry);
1044                 pid_files[i].dentry = NULL;
1045         }
1046
1047         debugfs_remove(debugfs_parent);
1048         debugfs_parent = NULL;
1049 }
1050
1051 /************************** debugfs end ************************/
1052
1053 /************************** sysfs begin ************************/
1054 #define show_one(file_name, object)                                     \
1055         static ssize_t show_##file_name                                 \
1056         (struct kobject *kobj, struct attribute *attr, char *buf)       \
1057         {                                                               \
1058                 return sprintf(buf, "%u\n", limits->object);            \
1059         }
1060
1061 static ssize_t intel_pstate_show_status(char *buf);
1062 static int intel_pstate_update_status(const char *buf, size_t size);
1063
1064 static ssize_t show_status(struct kobject *kobj,
1065                            struct attribute *attr, char *buf)
1066 {
1067         ssize_t ret;
1068
1069         mutex_lock(&intel_pstate_driver_lock);
1070         ret = intel_pstate_show_status(buf);
1071         mutex_unlock(&intel_pstate_driver_lock);
1072
1073         return ret;
1074 }
1075
1076 static ssize_t store_status(struct kobject *a, struct attribute *b,
1077                             const char *buf, size_t count)
1078 {
1079         char *p = memchr(buf, '\n', count);
1080         int ret;
1081
1082         mutex_lock(&intel_pstate_driver_lock);
1083         ret = intel_pstate_update_status(buf, p ? p - buf : count);
1084         mutex_unlock(&intel_pstate_driver_lock);
1085
1086         return ret < 0 ? ret : count;
1087 }
1088
1089 static ssize_t show_turbo_pct(struct kobject *kobj,
1090                                 struct attribute *attr, char *buf)
1091 {
1092         struct cpudata *cpu;
1093         int total, no_turbo, turbo_pct;
1094         uint32_t turbo_fp;
1095
1096         mutex_lock(&intel_pstate_driver_lock);
1097
1098         if (!driver_registered) {
1099                 mutex_unlock(&intel_pstate_driver_lock);
1100                 return -EAGAIN;
1101         }
1102
1103         cpu = all_cpu_data[0];
1104
1105         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1106         no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1107         turbo_fp = div_fp(no_turbo, total);
1108         turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1109
1110         mutex_unlock(&intel_pstate_driver_lock);
1111
1112         return sprintf(buf, "%u\n", turbo_pct);
1113 }
1114
1115 static ssize_t show_num_pstates(struct kobject *kobj,
1116                                 struct attribute *attr, char *buf)
1117 {
1118         struct cpudata *cpu;
1119         int total;
1120
1121         mutex_lock(&intel_pstate_driver_lock);
1122
1123         if (!driver_registered) {
1124                 mutex_unlock(&intel_pstate_driver_lock);
1125                 return -EAGAIN;
1126         }
1127
1128         cpu = all_cpu_data[0];
1129         total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1130
1131         mutex_unlock(&intel_pstate_driver_lock);
1132
1133         return sprintf(buf, "%u\n", total);
1134 }
1135
1136 static ssize_t show_no_turbo(struct kobject *kobj,
1137                              struct attribute *attr, char *buf)
1138 {
1139         ssize_t ret;
1140
1141         mutex_lock(&intel_pstate_driver_lock);
1142
1143         if (!driver_registered) {
1144                 mutex_unlock(&intel_pstate_driver_lock);
1145                 return -EAGAIN;
1146         }
1147
1148         update_turbo_state();
1149         if (limits->turbo_disabled)
1150                 ret = sprintf(buf, "%u\n", limits->turbo_disabled);
1151         else
1152                 ret = sprintf(buf, "%u\n", limits->no_turbo);
1153
1154         mutex_unlock(&intel_pstate_driver_lock);
1155
1156         return ret;
1157 }
1158
1159 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
1160                               const char *buf, size_t count)
1161 {
1162         unsigned int input;
1163         int ret;
1164
1165         ret = sscanf(buf, "%u", &input);
1166         if (ret != 1)
1167                 return -EINVAL;
1168
1169         mutex_lock(&intel_pstate_driver_lock);
1170
1171         if (!driver_registered) {
1172                 mutex_unlock(&intel_pstate_driver_lock);
1173                 return -EAGAIN;
1174         }
1175
1176         mutex_lock(&intel_pstate_limits_lock);
1177
1178         update_turbo_state();
1179         if (limits->turbo_disabled) {
1180                 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
1181                 mutex_unlock(&intel_pstate_limits_lock);
1182                 mutex_unlock(&intel_pstate_driver_lock);
1183                 return -EPERM;
1184         }
1185
1186         limits->no_turbo = clamp_t(int, input, 0, 1);
1187
1188         mutex_unlock(&intel_pstate_limits_lock);
1189
1190         intel_pstate_update_policies();
1191
1192         mutex_unlock(&intel_pstate_driver_lock);
1193
1194         return count;
1195 }
1196
1197 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
1198                                   const char *buf, size_t count)
1199 {
1200         unsigned int input;
1201         int ret;
1202
1203         ret = sscanf(buf, "%u", &input);
1204         if (ret != 1)
1205                 return -EINVAL;
1206
1207         mutex_lock(&intel_pstate_driver_lock);
1208
1209         if (!driver_registered) {
1210                 mutex_unlock(&intel_pstate_driver_lock);
1211                 return -EAGAIN;
1212         }
1213
1214         mutex_lock(&intel_pstate_limits_lock);
1215
1216         limits->max_sysfs_pct = clamp_t(int, input, 0 , 100);
1217         limits->max_perf_pct = min(limits->max_policy_pct,
1218                                    limits->max_sysfs_pct);
1219         limits->max_perf_pct = max(limits->min_policy_pct,
1220                                    limits->max_perf_pct);
1221         limits->max_perf_pct = max(limits->min_perf_pct,
1222                                    limits->max_perf_pct);
1223         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
1224
1225         mutex_unlock(&intel_pstate_limits_lock);
1226
1227         intel_pstate_update_policies();
1228
1229         mutex_unlock(&intel_pstate_driver_lock);
1230
1231         return count;
1232 }
1233
1234 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1235                                   const char *buf, size_t count)
1236 {
1237         unsigned int input;
1238         int ret;
1239
1240         ret = sscanf(buf, "%u", &input);
1241         if (ret != 1)
1242                 return -EINVAL;
1243
1244         mutex_lock(&intel_pstate_driver_lock);
1245
1246         if (!driver_registered) {
1247                 mutex_unlock(&intel_pstate_driver_lock);
1248                 return -EAGAIN;
1249         }
1250
1251         mutex_lock(&intel_pstate_limits_lock);
1252
1253         limits->min_sysfs_pct = clamp_t(int, input, 0 , 100);
1254         limits->min_perf_pct = max(limits->min_policy_pct,
1255                                    limits->min_sysfs_pct);
1256         limits->min_perf_pct = min(limits->max_policy_pct,
1257                                    limits->min_perf_pct);
1258         limits->min_perf_pct = min(limits->max_perf_pct,
1259                                    limits->min_perf_pct);
1260         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
1261
1262         mutex_unlock(&intel_pstate_limits_lock);
1263
1264         intel_pstate_update_policies();
1265
1266         mutex_unlock(&intel_pstate_driver_lock);
1267
1268         return count;
1269 }
1270
1271 show_one(max_perf_pct, max_perf_pct);
1272 show_one(min_perf_pct, min_perf_pct);
1273
1274 define_one_global_rw(status);
1275 define_one_global_rw(no_turbo);
1276 define_one_global_rw(max_perf_pct);
1277 define_one_global_rw(min_perf_pct);
1278 define_one_global_ro(turbo_pct);
1279 define_one_global_ro(num_pstates);
1280
1281 static struct attribute *intel_pstate_attributes[] = {
1282         &status.attr,
1283         &no_turbo.attr,
1284         &turbo_pct.attr,
1285         &num_pstates.attr,
1286         NULL
1287 };
1288
1289 static struct attribute_group intel_pstate_attr_group = {
1290         .attrs = intel_pstate_attributes,
1291 };
1292
1293 static void __init intel_pstate_sysfs_expose_params(void)
1294 {
1295         struct kobject *intel_pstate_kobject;
1296         int rc;
1297
1298         intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1299                                                 &cpu_subsys.dev_root->kobj);
1300         if (WARN_ON(!intel_pstate_kobject))
1301                 return;
1302
1303         rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1304         if (WARN_ON(rc))
1305                 return;
1306
1307         /*
1308          * If per cpu limits are enforced there are no global limits, so
1309          * return without creating max/min_perf_pct attributes
1310          */
1311         if (per_cpu_limits)
1312                 return;
1313
1314         rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1315         WARN_ON(rc);
1316
1317         rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1318         WARN_ON(rc);
1319
1320 }
1321 /************************** sysfs end ************************/
1322
1323 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1324 {
1325         /* First disable HWP notification interrupt as we don't process them */
1326         if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1327                 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1328
1329         wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1330         cpudata->epp_policy = 0;
1331         if (cpudata->epp_default == -EINVAL)
1332                 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1333 }
1334
1335 #define MSR_IA32_POWER_CTL_BIT_EE       19
1336
1337 /* Disable energy efficiency optimization */
1338 static void intel_pstate_disable_ee(int cpu)
1339 {
1340         u64 power_ctl;
1341         int ret;
1342
1343         ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1344         if (ret)
1345                 return;
1346
1347         if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1348                 pr_info("Disabling energy efficiency optimization\n");
1349                 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1350                 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1351         }
1352 }
1353
1354 static int atom_get_min_pstate(void)
1355 {
1356         u64 value;
1357
1358         rdmsrl(ATOM_RATIOS, value);
1359         return (value >> 8) & 0x7F;
1360 }
1361
1362 static int atom_get_max_pstate(void)
1363 {
1364         u64 value;
1365
1366         rdmsrl(ATOM_RATIOS, value);
1367         return (value >> 16) & 0x7F;
1368 }
1369
1370 static int atom_get_turbo_pstate(void)
1371 {
1372         u64 value;
1373
1374         rdmsrl(ATOM_TURBO_RATIOS, value);
1375         return value & 0x7F;
1376 }
1377
1378 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1379 {
1380         u64 val;
1381         int32_t vid_fp;
1382         u32 vid;
1383
1384         val = (u64)pstate << 8;
1385         if (limits->no_turbo && !limits->turbo_disabled)
1386                 val |= (u64)1 << 32;
1387
1388         vid_fp = cpudata->vid.min + mul_fp(
1389                 int_tofp(pstate - cpudata->pstate.min_pstate),
1390                 cpudata->vid.ratio);
1391
1392         vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1393         vid = ceiling_fp(vid_fp);
1394
1395         if (pstate > cpudata->pstate.max_pstate)
1396                 vid = cpudata->vid.turbo;
1397
1398         return val | vid;
1399 }
1400
1401 static int silvermont_get_scaling(void)
1402 {
1403         u64 value;
1404         int i;
1405         /* Defined in Table 35-6 from SDM (Sept 2015) */
1406         static int silvermont_freq_table[] = {
1407                 83300, 100000, 133300, 116700, 80000};
1408
1409         rdmsrl(MSR_FSB_FREQ, value);
1410         i = value & 0x7;
1411         WARN_ON(i > 4);
1412
1413         return silvermont_freq_table[i];
1414 }
1415
1416 static int airmont_get_scaling(void)
1417 {
1418         u64 value;
1419         int i;
1420         /* Defined in Table 35-10 from SDM (Sept 2015) */
1421         static int airmont_freq_table[] = {
1422                 83300, 100000, 133300, 116700, 80000,
1423                 93300, 90000, 88900, 87500};
1424
1425         rdmsrl(MSR_FSB_FREQ, value);
1426         i = value & 0xF;
1427         WARN_ON(i > 8);
1428
1429         return airmont_freq_table[i];
1430 }
1431
1432 static void atom_get_vid(struct cpudata *cpudata)
1433 {
1434         u64 value;
1435
1436         rdmsrl(ATOM_VIDS, value);
1437         cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1438         cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1439         cpudata->vid.ratio = div_fp(
1440                 cpudata->vid.max - cpudata->vid.min,
1441                 int_tofp(cpudata->pstate.max_pstate -
1442                         cpudata->pstate.min_pstate));
1443
1444         rdmsrl(ATOM_TURBO_VIDS, value);
1445         cpudata->vid.turbo = value & 0x7f;
1446 }
1447
1448 static int core_get_min_pstate(void)
1449 {
1450         u64 value;
1451
1452         rdmsrl(MSR_PLATFORM_INFO, value);
1453         return (value >> 40) & 0xFF;
1454 }
1455
1456 static int core_get_max_pstate_physical(void)
1457 {
1458         u64 value;
1459
1460         rdmsrl(MSR_PLATFORM_INFO, value);
1461         return (value >> 8) & 0xFF;
1462 }
1463
1464 static int core_get_tdp_ratio(u64 plat_info)
1465 {
1466         /* Check how many TDP levels present */
1467         if (plat_info & 0x600000000) {
1468                 u64 tdp_ctrl;
1469                 u64 tdp_ratio;
1470                 int tdp_msr;
1471                 int err;
1472
1473                 /* Get the TDP level (0, 1, 2) to get ratios */
1474                 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1475                 if (err)
1476                         return err;
1477
1478                 /* TDP MSR are continuous starting at 0x648 */
1479                 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1480                 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1481                 if (err)
1482                         return err;
1483
1484                 /* For level 1 and 2, bits[23:16] contain the ratio */
1485                 if (tdp_ctrl & 0x03)
1486                         tdp_ratio >>= 16;
1487
1488                 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1489                 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1490
1491                 return (int)tdp_ratio;
1492         }
1493
1494         return -ENXIO;
1495 }
1496
1497 static int core_get_max_pstate(void)
1498 {
1499         u64 tar;
1500         u64 plat_info;
1501         int max_pstate;
1502         int tdp_ratio;
1503         int err;
1504
1505         rdmsrl(MSR_PLATFORM_INFO, plat_info);
1506         max_pstate = (plat_info >> 8) & 0xFF;
1507
1508         tdp_ratio = core_get_tdp_ratio(plat_info);
1509         if (tdp_ratio <= 0)
1510                 return max_pstate;
1511
1512         if (hwp_active) {
1513                 /* Turbo activation ratio is not used on HWP platforms */
1514                 return tdp_ratio;
1515         }
1516
1517         err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1518         if (!err) {
1519                 int tar_levels;
1520
1521                 /* Do some sanity checking for safety */
1522                 tar_levels = tar & 0xff;
1523                 if (tdp_ratio - 1 == tar_levels) {
1524                         max_pstate = tar_levels;
1525                         pr_debug("max_pstate=TAC %x\n", max_pstate);
1526                 }
1527         }
1528
1529         return max_pstate;
1530 }
1531
1532 static int core_get_turbo_pstate(void)
1533 {
1534         u64 value;
1535         int nont, ret;
1536
1537         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1538         nont = core_get_max_pstate();
1539         ret = (value) & 255;
1540         if (ret <= nont)
1541                 ret = nont;
1542         return ret;
1543 }
1544
1545 static inline int core_get_scaling(void)
1546 {
1547         return 100000;
1548 }
1549
1550 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1551 {
1552         u64 val;
1553
1554         val = (u64)pstate << 8;
1555         if (limits->no_turbo && !limits->turbo_disabled)
1556                 val |= (u64)1 << 32;
1557
1558         return val;
1559 }
1560
1561 static int knl_get_turbo_pstate(void)
1562 {
1563         u64 value;
1564         int nont, ret;
1565
1566         rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1567         nont = core_get_max_pstate();
1568         ret = (((value) >> 8) & 0xFF);
1569         if (ret <= nont)
1570                 ret = nont;
1571         return ret;
1572 }
1573
1574 static struct cpu_defaults core_params = {
1575         .pid_policy = {
1576                 .sample_rate_ms = 10,
1577                 .deadband = 0,
1578                 .setpoint = 97,
1579                 .p_gain_pct = 20,
1580                 .d_gain_pct = 0,
1581                 .i_gain_pct = 0,
1582         },
1583         .funcs = {
1584                 .get_max = core_get_max_pstate,
1585                 .get_max_physical = core_get_max_pstate_physical,
1586                 .get_min = core_get_min_pstate,
1587                 .get_turbo = core_get_turbo_pstate,
1588                 .get_scaling = core_get_scaling,
1589                 .get_val = core_get_val,
1590                 .get_target_pstate = get_target_pstate_use_performance,
1591         },
1592 };
1593
1594 static const struct cpu_defaults silvermont_params = {
1595         .pid_policy = {
1596                 .sample_rate_ms = 10,
1597                 .deadband = 0,
1598                 .setpoint = 60,
1599                 .p_gain_pct = 14,
1600                 .d_gain_pct = 0,
1601                 .i_gain_pct = 4,
1602         },
1603         .funcs = {
1604                 .get_max = atom_get_max_pstate,
1605                 .get_max_physical = atom_get_max_pstate,
1606                 .get_min = atom_get_min_pstate,
1607                 .get_turbo = atom_get_turbo_pstate,
1608                 .get_val = atom_get_val,
1609                 .get_scaling = silvermont_get_scaling,
1610                 .get_vid = atom_get_vid,
1611                 .get_target_pstate = get_target_pstate_use_cpu_load,
1612         },
1613 };
1614
1615 static const struct cpu_defaults airmont_params = {
1616         .pid_policy = {
1617                 .sample_rate_ms = 10,
1618                 .deadband = 0,
1619                 .setpoint = 60,
1620                 .p_gain_pct = 14,
1621                 .d_gain_pct = 0,
1622                 .i_gain_pct = 4,
1623         },
1624         .funcs = {
1625                 .get_max = atom_get_max_pstate,
1626                 .get_max_physical = atom_get_max_pstate,
1627                 .get_min = atom_get_min_pstate,
1628                 .get_turbo = atom_get_turbo_pstate,
1629                 .get_val = atom_get_val,
1630                 .get_scaling = airmont_get_scaling,
1631                 .get_vid = atom_get_vid,
1632                 .get_target_pstate = get_target_pstate_use_cpu_load,
1633         },
1634 };
1635
1636 static const struct cpu_defaults knl_params = {
1637         .pid_policy = {
1638                 .sample_rate_ms = 10,
1639                 .deadband = 0,
1640                 .setpoint = 97,
1641                 .p_gain_pct = 20,
1642                 .d_gain_pct = 0,
1643                 .i_gain_pct = 0,
1644         },
1645         .funcs = {
1646                 .get_max = core_get_max_pstate,
1647                 .get_max_physical = core_get_max_pstate_physical,
1648                 .get_min = core_get_min_pstate,
1649                 .get_turbo = knl_get_turbo_pstate,
1650                 .get_scaling = core_get_scaling,
1651                 .get_val = core_get_val,
1652                 .get_target_pstate = get_target_pstate_use_performance,
1653         },
1654 };
1655
1656 static const struct cpu_defaults bxt_params = {
1657         .pid_policy = {
1658                 .sample_rate_ms = 10,
1659                 .deadband = 0,
1660                 .setpoint = 60,
1661                 .p_gain_pct = 14,
1662                 .d_gain_pct = 0,
1663                 .i_gain_pct = 4,
1664         },
1665         .funcs = {
1666                 .get_max = core_get_max_pstate,
1667                 .get_max_physical = core_get_max_pstate_physical,
1668                 .get_min = core_get_min_pstate,
1669                 .get_turbo = core_get_turbo_pstate,
1670                 .get_scaling = core_get_scaling,
1671                 .get_val = core_get_val,
1672                 .get_target_pstate = get_target_pstate_use_cpu_load,
1673         },
1674 };
1675
1676 static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
1677 {
1678         int max_perf = cpu->pstate.turbo_pstate;
1679         int max_perf_adj;
1680         int min_perf;
1681         struct perf_limits *perf_limits = limits;
1682
1683         if (limits->no_turbo || limits->turbo_disabled)
1684                 max_perf = cpu->pstate.max_pstate;
1685
1686         if (per_cpu_limits)
1687                 perf_limits = cpu->perf_limits;
1688
1689         /*
1690          * performance can be limited by user through sysfs, by cpufreq
1691          * policy, or by cpu specific default values determined through
1692          * experimentation.
1693          */
1694         max_perf_adj = fp_ext_toint(max_perf * perf_limits->max_perf);
1695         *max = clamp_t(int, max_perf_adj,
1696                         cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
1697
1698         min_perf = fp_ext_toint(max_perf * perf_limits->min_perf);
1699         *min = clamp_t(int, min_perf, cpu->pstate.min_pstate, max_perf);
1700 }
1701
1702 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1703 {
1704         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1705         cpu->pstate.current_pstate = pstate;
1706         /*
1707          * Generally, there is no guarantee that this code will always run on
1708          * the CPU being updated, so force the register update to run on the
1709          * right CPU.
1710          */
1711         wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1712                       pstate_funcs.get_val(cpu, pstate));
1713 }
1714
1715 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1716 {
1717         intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1718 }
1719
1720 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1721 {
1722         int min_pstate, max_pstate;
1723
1724         update_turbo_state();
1725         intel_pstate_get_min_max(cpu, &min_pstate, &max_pstate);
1726         intel_pstate_set_pstate(cpu, max_pstate);
1727 }
1728
1729 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1730 {
1731         cpu->pstate.min_pstate = pstate_funcs.get_min();
1732         cpu->pstate.max_pstate = pstate_funcs.get_max();
1733         cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1734         cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1735         cpu->pstate.scaling = pstate_funcs.get_scaling();
1736         cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1737         cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1738
1739         if (pstate_funcs.get_vid)
1740                 pstate_funcs.get_vid(cpu);
1741
1742         intel_pstate_set_min_pstate(cpu);
1743 }
1744
1745 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1746 {
1747         struct sample *sample = &cpu->sample;
1748
1749         sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1750 }
1751
1752 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1753 {
1754         u64 aperf, mperf;
1755         unsigned long flags;
1756         u64 tsc;
1757
1758         local_irq_save(flags);
1759         rdmsrl(MSR_IA32_APERF, aperf);
1760         rdmsrl(MSR_IA32_MPERF, mperf);
1761         tsc = rdtsc();
1762         if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1763                 local_irq_restore(flags);
1764                 return false;
1765         }
1766         local_irq_restore(flags);
1767
1768         cpu->last_sample_time = cpu->sample.time;
1769         cpu->sample.time = time;
1770         cpu->sample.aperf = aperf;
1771         cpu->sample.mperf = mperf;
1772         cpu->sample.tsc =  tsc;
1773         cpu->sample.aperf -= cpu->prev_aperf;
1774         cpu->sample.mperf -= cpu->prev_mperf;
1775         cpu->sample.tsc -= cpu->prev_tsc;
1776
1777         cpu->prev_aperf = aperf;
1778         cpu->prev_mperf = mperf;
1779         cpu->prev_tsc = tsc;
1780         /*
1781          * First time this function is invoked in a given cycle, all of the
1782          * previous sample data fields are equal to zero or stale and they must
1783          * be populated with meaningful numbers for things to work, so assume
1784          * that sample.time will always be reset before setting the utilization
1785          * update hook and make the caller skip the sample then.
1786          */
1787         return !!cpu->last_sample_time;
1788 }
1789
1790 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1791 {
1792         return mul_ext_fp(cpu->sample.core_avg_perf,
1793                           cpu->pstate.max_pstate_physical * cpu->pstate.scaling);
1794 }
1795
1796 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1797 {
1798         return mul_ext_fp(cpu->pstate.max_pstate_physical,
1799                           cpu->sample.core_avg_perf);
1800 }
1801
1802 static inline int32_t get_target_pstate_use_cpu_load(struct cpudata *cpu)
1803 {
1804         struct sample *sample = &cpu->sample;
1805         int32_t busy_frac, boost;
1806         int target, avg_pstate;
1807
1808         busy_frac = div_fp(sample->mperf, sample->tsc);
1809
1810         boost = cpu->iowait_boost;
1811         cpu->iowait_boost >>= 1;
1812
1813         if (busy_frac < boost)
1814                 busy_frac = boost;
1815
1816         sample->busy_scaled = busy_frac * 100;
1817
1818         target = limits->no_turbo || limits->turbo_disabled ?
1819                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1820         target += target >> 2;
1821         target = mul_fp(target, busy_frac);
1822         if (target < cpu->pstate.min_pstate)
1823                 target = cpu->pstate.min_pstate;
1824
1825         /*
1826          * If the average P-state during the previous cycle was higher than the
1827          * current target, add 50% of the difference to the target to reduce
1828          * possible performance oscillations and offset possible performance
1829          * loss related to moving the workload from one CPU to another within
1830          * a package/module.
1831          */
1832         avg_pstate = get_avg_pstate(cpu);
1833         if (avg_pstate > target)
1834                 target += (avg_pstate - target) >> 1;
1835
1836         return target;
1837 }
1838
1839 static inline int32_t get_target_pstate_use_performance(struct cpudata *cpu)
1840 {
1841         int32_t perf_scaled, max_pstate, current_pstate, sample_ratio;
1842         u64 duration_ns;
1843
1844         /*
1845          * perf_scaled is the ratio of the average P-state during the last
1846          * sampling period to the P-state requested last time (in percent).
1847          *
1848          * That measures the system's response to the previous P-state
1849          * selection.
1850          */
1851         max_pstate = cpu->pstate.max_pstate_physical;
1852         current_pstate = cpu->pstate.current_pstate;
1853         perf_scaled = mul_ext_fp(cpu->sample.core_avg_perf,
1854                                div_fp(100 * max_pstate, current_pstate));
1855
1856         /*
1857          * Since our utilization update callback will not run unless we are
1858          * in C0, check if the actual elapsed time is significantly greater (3x)
1859          * than our sample interval.  If it is, then we were idle for a long
1860          * enough period of time to adjust our performance metric.
1861          */
1862         duration_ns = cpu->sample.time - cpu->last_sample_time;
1863         if ((s64)duration_ns > pid_params.sample_rate_ns * 3) {
1864                 sample_ratio = div_fp(pid_params.sample_rate_ns, duration_ns);
1865                 perf_scaled = mul_fp(perf_scaled, sample_ratio);
1866         } else {
1867                 sample_ratio = div_fp(100 * cpu->sample.mperf, cpu->sample.tsc);
1868                 if (sample_ratio < int_tofp(1))
1869                         perf_scaled = 0;
1870         }
1871
1872         cpu->sample.busy_scaled = perf_scaled;
1873         return cpu->pstate.current_pstate - pid_calc(&cpu->pid, perf_scaled);
1874 }
1875
1876 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1877 {
1878         int max_perf, min_perf;
1879
1880         intel_pstate_get_min_max(cpu, &min_perf, &max_perf);
1881         pstate = clamp_t(int, pstate, min_perf, max_perf);
1882         trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1883         return pstate;
1884 }
1885
1886 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1887 {
1888         pstate = intel_pstate_prepare_request(cpu, pstate);
1889         if (pstate == cpu->pstate.current_pstate)
1890                 return;
1891
1892         cpu->pstate.current_pstate = pstate;
1893         wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1894 }
1895
1896 static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
1897 {
1898         int from, target_pstate;
1899         struct sample *sample;
1900
1901         from = cpu->pstate.current_pstate;
1902
1903         target_pstate = cpu->policy == CPUFREQ_POLICY_PERFORMANCE ?
1904                 cpu->pstate.turbo_pstate : pstate_funcs.get_target_pstate(cpu);
1905
1906         update_turbo_state();
1907
1908         intel_pstate_update_pstate(cpu, target_pstate);
1909
1910         sample = &cpu->sample;
1911         trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1912                 fp_toint(sample->busy_scaled),
1913                 from,
1914                 cpu->pstate.current_pstate,
1915                 sample->mperf,
1916                 sample->aperf,
1917                 sample->tsc,
1918                 get_avg_frequency(cpu),
1919                 fp_toint(cpu->iowait_boost * 100));
1920 }
1921
1922 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1923                                      unsigned int flags)
1924 {
1925         struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1926         u64 delta_ns;
1927
1928         if (pstate_funcs.get_target_pstate == get_target_pstate_use_cpu_load) {
1929                 if (flags & SCHED_CPUFREQ_IOWAIT) {
1930                         cpu->iowait_boost = int_tofp(1);
1931                 } else if (cpu->iowait_boost) {
1932                         /* Clear iowait_boost if the CPU may have been idle. */
1933                         delta_ns = time - cpu->last_update;
1934                         if (delta_ns > TICK_NSEC)
1935                                 cpu->iowait_boost = 0;
1936                 }
1937                 cpu->last_update = time;
1938         }
1939
1940         delta_ns = time - cpu->sample.time;
1941         if ((s64)delta_ns >= pid_params.sample_rate_ns) {
1942                 bool sample_taken = intel_pstate_sample(cpu, time);
1943
1944                 if (sample_taken) {
1945                         intel_pstate_calc_avg_perf(cpu);
1946                         if (!hwp_active)
1947                                 intel_pstate_adjust_busy_pstate(cpu);
1948                 }
1949         }
1950 }
1951
1952 #define ICPU(model, policy) \
1953         { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1954                         (unsigned long)&policy }
1955
1956 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1957         ICPU(INTEL_FAM6_SANDYBRIDGE,            core_params),
1958         ICPU(INTEL_FAM6_SANDYBRIDGE_X,          core_params),
1959         ICPU(INTEL_FAM6_ATOM_SILVERMONT1,       silvermont_params),
1960         ICPU(INTEL_FAM6_IVYBRIDGE,              core_params),
1961         ICPU(INTEL_FAM6_HASWELL_CORE,           core_params),
1962         ICPU(INTEL_FAM6_BROADWELL_CORE,         core_params),
1963         ICPU(INTEL_FAM6_IVYBRIDGE_X,            core_params),
1964         ICPU(INTEL_FAM6_HASWELL_X,              core_params),
1965         ICPU(INTEL_FAM6_HASWELL_ULT,            core_params),
1966         ICPU(INTEL_FAM6_HASWELL_GT3E,           core_params),
1967         ICPU(INTEL_FAM6_BROADWELL_GT3E,         core_params),
1968         ICPU(INTEL_FAM6_ATOM_AIRMONT,           airmont_params),
1969         ICPU(INTEL_FAM6_SKYLAKE_MOBILE,         core_params),
1970         ICPU(INTEL_FAM6_BROADWELL_X,            core_params),
1971         ICPU(INTEL_FAM6_SKYLAKE_DESKTOP,        core_params),
1972         ICPU(INTEL_FAM6_BROADWELL_XEON_D,       core_params),
1973         ICPU(INTEL_FAM6_XEON_PHI_KNL,           knl_params),
1974         ICPU(INTEL_FAM6_XEON_PHI_KNM,           knl_params),
1975         ICPU(INTEL_FAM6_ATOM_GOLDMONT,          bxt_params),
1976         {}
1977 };
1978 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1979
1980 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1981         ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_params),
1982         ICPU(INTEL_FAM6_BROADWELL_X, core_params),
1983         ICPU(INTEL_FAM6_SKYLAKE_X, core_params),
1984         {}
1985 };
1986
1987 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1988         ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_params),
1989         {}
1990 };
1991
1992 static int intel_pstate_init_cpu(unsigned int cpunum)
1993 {
1994         struct cpudata *cpu;
1995
1996         cpu = all_cpu_data[cpunum];
1997
1998         if (!cpu) {
1999                 unsigned int size = sizeof(struct cpudata);
2000
2001                 if (per_cpu_limits)
2002                         size += sizeof(struct perf_limits);
2003
2004                 cpu = kzalloc(size, GFP_KERNEL);
2005                 if (!cpu)
2006                         return -ENOMEM;
2007
2008                 all_cpu_data[cpunum] = cpu;
2009                 if (per_cpu_limits)
2010                         cpu->perf_limits = (struct perf_limits *)(cpu + 1);
2011
2012                 cpu->epp_default = -EINVAL;
2013                 cpu->epp_powersave = -EINVAL;
2014                 cpu->epp_saved = -EINVAL;
2015         }
2016
2017         cpu = all_cpu_data[cpunum];
2018
2019         cpu->cpu = cpunum;
2020
2021         if (hwp_active) {
2022                 const struct x86_cpu_id *id;
2023
2024                 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
2025                 if (id)
2026                         intel_pstate_disable_ee(cpunum);
2027
2028                 intel_pstate_hwp_enable(cpu);
2029                 pid_params.sample_rate_ms = 50;
2030                 pid_params.sample_rate_ns = 50 * NSEC_PER_MSEC;
2031         }
2032
2033         intel_pstate_get_cpu_pstates(cpu);
2034
2035         intel_pstate_busy_pid_reset(cpu);
2036
2037         pr_debug("controlling: cpu %d\n", cpunum);
2038
2039         return 0;
2040 }
2041
2042 static unsigned int intel_pstate_get(unsigned int cpu_num)
2043 {
2044         struct cpudata *cpu = all_cpu_data[cpu_num];
2045
2046         return cpu ? get_avg_frequency(cpu) : 0;
2047 }
2048
2049 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2050 {
2051         struct cpudata *cpu = all_cpu_data[cpu_num];
2052
2053         if (cpu->update_util_set)
2054                 return;
2055
2056         /* Prevent intel_pstate_update_util() from using stale data. */
2057         cpu->sample.time = 0;
2058         cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2059                                      intel_pstate_update_util);
2060         cpu->update_util_set = true;
2061 }
2062
2063 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2064 {
2065         struct cpudata *cpu_data = all_cpu_data[cpu];
2066
2067         if (!cpu_data->update_util_set)
2068                 return;
2069
2070         cpufreq_remove_update_util_hook(cpu);
2071         cpu_data->update_util_set = false;
2072         synchronize_sched();
2073 }
2074
2075 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
2076                                             struct perf_limits *limits)
2077 {
2078
2079         limits->max_policy_pct = DIV_ROUND_UP(policy->max * 100,
2080                                               policy->cpuinfo.max_freq);
2081         limits->max_policy_pct = clamp_t(int, limits->max_policy_pct, 0, 100);
2082         if (policy->max == policy->min) {
2083                 limits->min_policy_pct = limits->max_policy_pct;
2084         } else {
2085                 limits->min_policy_pct = DIV_ROUND_UP(policy->min * 100,
2086                                                       policy->cpuinfo.max_freq);
2087                 limits->min_policy_pct = clamp_t(int, limits->min_policy_pct,
2088                                                  0, 100);
2089         }
2090
2091         /* Normalize user input to [min_policy_pct, max_policy_pct] */
2092         limits->min_perf_pct = max(limits->min_policy_pct,
2093                                    limits->min_sysfs_pct);
2094         limits->min_perf_pct = min(limits->max_policy_pct,
2095                                    limits->min_perf_pct);
2096         limits->max_perf_pct = min(limits->max_policy_pct,
2097                                    limits->max_sysfs_pct);
2098         limits->max_perf_pct = max(limits->min_policy_pct,
2099                                    limits->max_perf_pct);
2100
2101         /* Make sure min_perf_pct <= max_perf_pct */
2102         limits->min_perf_pct = min(limits->max_perf_pct, limits->min_perf_pct);
2103
2104         limits->min_perf = div_ext_fp(limits->min_perf_pct, 100);
2105         limits->max_perf = div_ext_fp(limits->max_perf_pct, 100);
2106         limits->max_perf = round_up(limits->max_perf, EXT_FRAC_BITS);
2107         limits->min_perf = round_up(limits->min_perf, EXT_FRAC_BITS);
2108
2109         pr_debug("cpu:%d max_perf_pct:%d min_perf_pct:%d\n", policy->cpu,
2110                  limits->max_perf_pct, limits->min_perf_pct);
2111 }
2112
2113 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2114 {
2115         struct cpudata *cpu;
2116         struct perf_limits *perf_limits = NULL;
2117
2118         if (!policy->cpuinfo.max_freq)
2119                 return -ENODEV;
2120
2121         pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2122                  policy->cpuinfo.max_freq, policy->max);
2123
2124         cpu = all_cpu_data[policy->cpu];
2125         cpu->policy = policy->policy;
2126
2127         if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2128             policy->max < policy->cpuinfo.max_freq &&
2129             policy->max > cpu->pstate.max_pstate * cpu->pstate.scaling) {
2130                 pr_debug("policy->max > max non turbo frequency\n");
2131                 policy->max = policy->cpuinfo.max_freq;
2132         }
2133
2134         if (per_cpu_limits)
2135                 perf_limits = cpu->perf_limits;
2136
2137         mutex_lock(&intel_pstate_limits_lock);
2138
2139         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE) {
2140                 if (!perf_limits) {
2141                         limits = &performance_limits;
2142                         perf_limits = limits;
2143                 }
2144                 if (policy->max >= policy->cpuinfo.max_freq &&
2145                     !limits->no_turbo) {
2146                         pr_debug("set performance\n");
2147                         intel_pstate_set_performance_limits(perf_limits);
2148                         goto out;
2149                 }
2150         } else {
2151                 pr_debug("set powersave\n");
2152                 if (!perf_limits) {
2153                         limits = &powersave_limits;
2154                         perf_limits = limits;
2155                 }
2156
2157         }
2158
2159         intel_pstate_update_perf_limits(policy, perf_limits);
2160  out:
2161         if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2162                 /*
2163                  * NOHZ_FULL CPUs need this as the governor callback may not
2164                  * be invoked on them.
2165                  */
2166                 intel_pstate_clear_update_util_hook(policy->cpu);
2167                 intel_pstate_max_within_limits(cpu);
2168         }
2169
2170         intel_pstate_set_update_util_hook(policy->cpu);
2171
2172         intel_pstate_hwp_set_policy(policy);
2173
2174         mutex_unlock(&intel_pstate_limits_lock);
2175
2176         return 0;
2177 }
2178
2179 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2180 {
2181         struct cpudata *cpu = all_cpu_data[policy->cpu];
2182         struct perf_limits *perf_limits;
2183
2184         if (policy->policy == CPUFREQ_POLICY_PERFORMANCE)
2185                 perf_limits = &performance_limits;
2186         else
2187                 perf_limits = &powersave_limits;
2188
2189         update_turbo_state();
2190         policy->cpuinfo.max_freq = perf_limits->turbo_disabled ||
2191                                         perf_limits->no_turbo ?
2192                                         cpu->pstate.max_freq :
2193                                         cpu->pstate.turbo_freq;
2194
2195         cpufreq_verify_within_cpu_limits(policy);
2196
2197         if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2198             policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2199                 return -EINVAL;
2200
2201         /* When per-CPU limits are used, sysfs limits are not used */
2202         if (!per_cpu_limits) {
2203                 unsigned int max_freq, min_freq;
2204
2205                 max_freq = policy->cpuinfo.max_freq *
2206                                                 limits->max_sysfs_pct / 100;
2207                 min_freq = policy->cpuinfo.max_freq *
2208                                                 limits->min_sysfs_pct / 100;
2209                 cpufreq_verify_within_limits(policy, min_freq, max_freq);
2210         }
2211
2212         return 0;
2213 }
2214
2215 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2216 {
2217         intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2218 }
2219
2220 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2221 {
2222         pr_debug("CPU %d exiting\n", policy->cpu);
2223
2224         intel_pstate_clear_update_util_hook(policy->cpu);
2225         if (hwp_active)
2226                 intel_pstate_hwp_save_state(policy);
2227         else
2228                 intel_cpufreq_stop_cpu(policy);
2229 }
2230
2231 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2232 {
2233         intel_pstate_exit_perf_limits(policy);
2234
2235         policy->fast_switch_possible = false;
2236
2237         return 0;
2238 }
2239
2240 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2241 {
2242         struct cpudata *cpu;
2243         int rc;
2244
2245         rc = intel_pstate_init_cpu(policy->cpu);
2246         if (rc)
2247                 return rc;
2248
2249         cpu = all_cpu_data[policy->cpu];
2250
2251         /*
2252          * We need sane value in the cpu->perf_limits, so inherit from global
2253          * perf_limits limits, which are seeded with values based on the
2254          * CONFIG_CPU_FREQ_DEFAULT_GOV_*, during boot up.
2255          */
2256         if (per_cpu_limits)
2257                 memcpy(cpu->perf_limits, limits, sizeof(struct perf_limits));
2258
2259         policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2260         policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2261
2262         /* cpuinfo and default policy values */
2263         policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2264         update_turbo_state();
2265         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2266                         cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2267         policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2268
2269         intel_pstate_init_acpi_perf_limits(policy);
2270         cpumask_set_cpu(policy->cpu, policy->cpus);
2271
2272         policy->fast_switch_possible = true;
2273
2274         return 0;
2275 }
2276
2277 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2278 {
2279         int ret = __intel_pstate_cpu_init(policy);
2280
2281         if (ret)
2282                 return ret;
2283
2284         policy->cpuinfo.transition_latency = CPUFREQ_ETERNAL;
2285         if (limits->min_perf_pct == 100 && limits->max_perf_pct == 100)
2286                 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2287         else
2288                 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2289
2290         return 0;
2291 }
2292
2293 static struct cpufreq_driver intel_pstate = {
2294         .flags          = CPUFREQ_CONST_LOOPS,
2295         .verify         = intel_pstate_verify_policy,
2296         .setpolicy      = intel_pstate_set_policy,
2297         .suspend        = intel_pstate_hwp_save_state,
2298         .resume         = intel_pstate_resume,
2299         .get            = intel_pstate_get,
2300         .init           = intel_pstate_cpu_init,
2301         .exit           = intel_pstate_cpu_exit,
2302         .stop_cpu       = intel_pstate_stop_cpu,
2303         .name           = "intel_pstate",
2304 };
2305
2306 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2307 {
2308         struct cpudata *cpu = all_cpu_data[policy->cpu];
2309         struct perf_limits *perf_limits = limits;
2310
2311         update_turbo_state();
2312         policy->cpuinfo.max_freq = limits->turbo_disabled ?
2313                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2314
2315         cpufreq_verify_within_cpu_limits(policy);
2316
2317         if (per_cpu_limits)
2318                 perf_limits = cpu->perf_limits;
2319
2320         mutex_lock(&intel_pstate_limits_lock);
2321
2322         intel_pstate_update_perf_limits(policy, perf_limits);
2323
2324         mutex_unlock(&intel_pstate_limits_lock);
2325
2326         return 0;
2327 }
2328
2329 static unsigned int intel_cpufreq_turbo_update(struct cpudata *cpu,
2330                                                struct cpufreq_policy *policy,
2331                                                unsigned int target_freq)
2332 {
2333         unsigned int max_freq;
2334
2335         update_turbo_state();
2336
2337         max_freq = limits->no_turbo || limits->turbo_disabled ?
2338                         cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2339         policy->cpuinfo.max_freq = max_freq;
2340         if (policy->max > max_freq)
2341                 policy->max = max_freq;
2342
2343         if (target_freq > max_freq)
2344                 target_freq = max_freq;
2345
2346         return target_freq;
2347 }
2348
2349 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2350                                 unsigned int target_freq,
2351                                 unsigned int relation)
2352 {
2353         struct cpudata *cpu = all_cpu_data[policy->cpu];
2354         struct cpufreq_freqs freqs;
2355         int target_pstate;
2356
2357         freqs.old = policy->cur;
2358         freqs.new = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2359
2360         cpufreq_freq_transition_begin(policy, &freqs);
2361         switch (relation) {
2362         case CPUFREQ_RELATION_L:
2363                 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2364                 break;
2365         case CPUFREQ_RELATION_H:
2366                 target_pstate = freqs.new / cpu->pstate.scaling;
2367                 break;
2368         default:
2369                 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2370                 break;
2371         }
2372         target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2373         if (target_pstate != cpu->pstate.current_pstate) {
2374                 cpu->pstate.current_pstate = target_pstate;
2375                 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2376                               pstate_funcs.get_val(cpu, target_pstate));
2377         }
2378         cpufreq_freq_transition_end(policy, &freqs, false);
2379
2380         return 0;
2381 }
2382
2383 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2384                                               unsigned int target_freq)
2385 {
2386         struct cpudata *cpu = all_cpu_data[policy->cpu];
2387         int target_pstate;
2388
2389         target_freq = intel_cpufreq_turbo_update(cpu, policy, target_freq);
2390         target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2391         intel_pstate_update_pstate(cpu, target_pstate);
2392         return target_freq;
2393 }
2394
2395 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2396 {
2397         int ret = __intel_pstate_cpu_init(policy);
2398
2399         if (ret)
2400                 return ret;
2401
2402         policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2403         /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2404         policy->cur = policy->cpuinfo.min_freq;
2405
2406         return 0;
2407 }
2408
2409 static struct cpufreq_driver intel_cpufreq = {
2410         .flags          = CPUFREQ_CONST_LOOPS,
2411         .verify         = intel_cpufreq_verify_policy,
2412         .target         = intel_cpufreq_target,
2413         .fast_switch    = intel_cpufreq_fast_switch,
2414         .init           = intel_cpufreq_cpu_init,
2415         .exit           = intel_pstate_cpu_exit,
2416         .stop_cpu       = intel_cpufreq_stop_cpu,
2417         .name           = "intel_cpufreq",
2418 };
2419
2420 static struct cpufreq_driver *intel_pstate_driver = &intel_pstate;
2421
2422 static void intel_pstate_driver_cleanup(void)
2423 {
2424         unsigned int cpu;
2425
2426         get_online_cpus();
2427         for_each_online_cpu(cpu) {
2428                 if (all_cpu_data[cpu]) {
2429                         if (intel_pstate_driver == &intel_pstate)
2430                                 intel_pstate_clear_update_util_hook(cpu);
2431
2432                         kfree(all_cpu_data[cpu]);
2433                         all_cpu_data[cpu] = NULL;
2434                 }
2435         }
2436         put_online_cpus();
2437 }
2438
2439 static int intel_pstate_register_driver(void)
2440 {
2441         int ret;
2442
2443         intel_pstate_init_limits(&powersave_limits);
2444         intel_pstate_set_performance_limits(&performance_limits);
2445         limits = IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE) ?
2446                         &performance_limits : &powersave_limits;
2447
2448         ret = cpufreq_register_driver(intel_pstate_driver);
2449         if (ret) {
2450                 intel_pstate_driver_cleanup();
2451                 return ret;
2452         }
2453
2454         mutex_lock(&intel_pstate_limits_lock);
2455         driver_registered = true;
2456         mutex_unlock(&intel_pstate_limits_lock);
2457
2458         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2459             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2460                 intel_pstate_debug_expose_params();
2461
2462         return 0;
2463 }
2464
2465 static int intel_pstate_unregister_driver(void)
2466 {
2467         if (hwp_active)
2468                 return -EBUSY;
2469
2470         if (intel_pstate_driver == &intel_pstate && !hwp_active &&
2471             pstate_funcs.get_target_pstate != get_target_pstate_use_cpu_load)
2472                 intel_pstate_debug_hide_params();
2473
2474         mutex_lock(&intel_pstate_limits_lock);
2475         driver_registered = false;
2476         mutex_unlock(&intel_pstate_limits_lock);
2477
2478         cpufreq_unregister_driver(intel_pstate_driver);
2479         intel_pstate_driver_cleanup();
2480
2481         return 0;
2482 }
2483
2484 static ssize_t intel_pstate_show_status(char *buf)
2485 {
2486         if (!driver_registered)
2487                 return sprintf(buf, "off\n");
2488
2489         return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2490                                         "active" : "passive");
2491 }
2492
2493 static int intel_pstate_update_status(const char *buf, size_t size)
2494 {
2495         int ret;
2496
2497         if (size == 3 && !strncmp(buf, "off", size))
2498                 return driver_registered ?
2499                         intel_pstate_unregister_driver() : -EINVAL;
2500
2501         if (size == 6 && !strncmp(buf, "active", size)) {
2502                 if (driver_registered) {
2503                         if (intel_pstate_driver == &intel_pstate)
2504                                 return 0;
2505
2506                         ret = intel_pstate_unregister_driver();
2507                         if (ret)
2508                                 return ret;
2509                 }
2510
2511                 intel_pstate_driver = &intel_pstate;
2512                 return intel_pstate_register_driver();
2513         }
2514
2515         if (size == 7 && !strncmp(buf, "passive", size)) {
2516                 if (driver_registered) {
2517                         if (intel_pstate_driver != &intel_pstate)
2518                                 return 0;
2519
2520                         ret = intel_pstate_unregister_driver();
2521                         if (ret)
2522                                 return ret;
2523                 }
2524
2525                 intel_pstate_driver = &intel_cpufreq;
2526                 return intel_pstate_register_driver();
2527         }
2528
2529         return -EINVAL;
2530 }
2531
2532 static int no_load __initdata;
2533 static int no_hwp __initdata;
2534 static int hwp_only __initdata;
2535 static unsigned int force_load __initdata;
2536
2537 static int __init intel_pstate_msrs_not_valid(void)
2538 {
2539         if (!pstate_funcs.get_max() ||
2540             !pstate_funcs.get_min() ||
2541             !pstate_funcs.get_turbo())
2542                 return -ENODEV;
2543
2544         return 0;
2545 }
2546
2547 static void __init copy_pid_params(struct pstate_adjust_policy *policy)
2548 {
2549         pid_params.sample_rate_ms = policy->sample_rate_ms;
2550         pid_params.sample_rate_ns = pid_params.sample_rate_ms * NSEC_PER_MSEC;
2551         pid_params.p_gain_pct = policy->p_gain_pct;
2552         pid_params.i_gain_pct = policy->i_gain_pct;
2553         pid_params.d_gain_pct = policy->d_gain_pct;
2554         pid_params.deadband = policy->deadband;
2555         pid_params.setpoint = policy->setpoint;
2556 }
2557
2558 #ifdef CONFIG_ACPI
2559 static void intel_pstate_use_acpi_profile(void)
2560 {
2561         if (acpi_gbl_FADT.preferred_profile == PM_MOBILE)
2562                 pstate_funcs.get_target_pstate =
2563                                 get_target_pstate_use_cpu_load;
2564 }
2565 #else
2566 static void intel_pstate_use_acpi_profile(void)
2567 {
2568 }
2569 #endif
2570
2571 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2572 {
2573         pstate_funcs.get_max   = funcs->get_max;
2574         pstate_funcs.get_max_physical = funcs->get_max_physical;
2575         pstate_funcs.get_min   = funcs->get_min;
2576         pstate_funcs.get_turbo = funcs->get_turbo;
2577         pstate_funcs.get_scaling = funcs->get_scaling;
2578         pstate_funcs.get_val   = funcs->get_val;
2579         pstate_funcs.get_vid   = funcs->get_vid;
2580         pstate_funcs.get_target_pstate = funcs->get_target_pstate;
2581
2582         intel_pstate_use_acpi_profile();
2583 }
2584
2585 #ifdef CONFIG_ACPI
2586
2587 static bool __init intel_pstate_no_acpi_pss(void)
2588 {
2589         int i;
2590
2591         for_each_possible_cpu(i) {
2592                 acpi_status status;
2593                 union acpi_object *pss;
2594                 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2595                 struct acpi_processor *pr = per_cpu(processors, i);
2596
2597                 if (!pr)
2598                         continue;
2599
2600                 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2601                 if (ACPI_FAILURE(status))
2602                         continue;
2603
2604                 pss = buffer.pointer;
2605                 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2606                         kfree(pss);
2607                         return false;
2608                 }
2609
2610                 kfree(pss);
2611         }
2612
2613         return true;
2614 }
2615
2616 static bool __init intel_pstate_has_acpi_ppc(void)
2617 {
2618         int i;
2619
2620         for_each_possible_cpu(i) {
2621                 struct acpi_processor *pr = per_cpu(processors, i);
2622
2623                 if (!pr)
2624                         continue;
2625                 if (acpi_has_method(pr->handle, "_PPC"))
2626                         return true;
2627         }
2628         return false;
2629 }
2630
2631 enum {
2632         PSS,
2633         PPC,
2634 };
2635
2636 struct hw_vendor_info {
2637         u16  valid;
2638         char oem_id[ACPI_OEM_ID_SIZE];
2639         char oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
2640         int  oem_pwr_table;
2641 };
2642
2643 /* Hardware vendor-specific info that has its own power management modes */
2644 static struct hw_vendor_info vendor_info[] __initdata = {
2645         {1, "HP    ", "ProLiant", PSS},
2646         {1, "ORACLE", "X4-2    ", PPC},
2647         {1, "ORACLE", "X4-2L   ", PPC},
2648         {1, "ORACLE", "X4-2B   ", PPC},
2649         {1, "ORACLE", "X3-2    ", PPC},
2650         {1, "ORACLE", "X3-2L   ", PPC},
2651         {1, "ORACLE", "X3-2B   ", PPC},
2652         {1, "ORACLE", "X4470M2 ", PPC},
2653         {1, "ORACLE", "X4270M3 ", PPC},
2654         {1, "ORACLE", "X4270M2 ", PPC},
2655         {1, "ORACLE", "X4170M2 ", PPC},
2656         {1, "ORACLE", "X4170 M3", PPC},
2657         {1, "ORACLE", "X4275 M3", PPC},
2658         {1, "ORACLE", "X6-2    ", PPC},
2659         {1, "ORACLE", "Sudbury ", PPC},
2660         {0, "", ""},
2661 };
2662
2663 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2664 {
2665         struct acpi_table_header hdr;
2666         struct hw_vendor_info *v_info;
2667         const struct x86_cpu_id *id;
2668         u64 misc_pwr;
2669
2670         id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2671         if (id) {
2672                 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2673                 if ( misc_pwr & (1 << 8))
2674                         return true;
2675         }
2676
2677         if (acpi_disabled ||
2678             ACPI_FAILURE(acpi_get_table_header(ACPI_SIG_FADT, 0, &hdr)))
2679                 return false;
2680
2681         for (v_info = vendor_info; v_info->valid; v_info++) {
2682                 if (!strncmp(hdr.oem_id, v_info->oem_id, ACPI_OEM_ID_SIZE) &&
2683                         !strncmp(hdr.oem_table_id, v_info->oem_table_id,
2684                                                 ACPI_OEM_TABLE_ID_SIZE))
2685                         switch (v_info->oem_pwr_table) {
2686                         case PSS:
2687                                 return intel_pstate_no_acpi_pss();
2688                         case PPC:
2689                                 return intel_pstate_has_acpi_ppc() &&
2690                                         (!force_load);
2691                         }
2692         }
2693
2694         return false;
2695 }
2696
2697 static void intel_pstate_request_control_from_smm(void)
2698 {
2699         /*
2700          * It may be unsafe to request P-states control from SMM if _PPC support
2701          * has not been enabled.
2702          */
2703         if (acpi_ppc)
2704                 acpi_processor_pstate_control();
2705 }
2706 #else /* CONFIG_ACPI not enabled */
2707 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2708 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2709 static inline void intel_pstate_request_control_from_smm(void) {}
2710 #endif /* CONFIG_ACPI */
2711
2712 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2713         { X86_VENDOR_INTEL, 6, X86_MODEL_ANY, X86_FEATURE_HWP },
2714         {}
2715 };
2716
2717 static int __init intel_pstate_init(void)
2718 {
2719         const struct x86_cpu_id *id;
2720         struct cpu_defaults *cpu_def;
2721         int rc = 0;
2722
2723         if (no_load)
2724                 return -ENODEV;
2725
2726         if (x86_match_cpu(hwp_support_ids) && !no_hwp) {
2727                 copy_cpu_funcs(&core_params.funcs);
2728                 hwp_active++;
2729                 intel_pstate.attr = hwp_cpufreq_attrs;
2730                 goto hwp_cpu_matched;
2731         }
2732
2733         id = x86_match_cpu(intel_pstate_cpu_ids);
2734         if (!id)
2735                 return -ENODEV;
2736
2737         cpu_def = (struct cpu_defaults *)id->driver_data;
2738
2739         copy_pid_params(&cpu_def->pid_policy);
2740         copy_cpu_funcs(&cpu_def->funcs);
2741
2742         if (intel_pstate_msrs_not_valid())
2743                 return -ENODEV;
2744
2745 hwp_cpu_matched:
2746         /*
2747          * The Intel pstate driver will be ignored if the platform
2748          * firmware has its own power management modes.
2749          */
2750         if (intel_pstate_platform_pwr_mgmt_exists())
2751                 return -ENODEV;
2752
2753         if (!hwp_active && hwp_only)
2754                 return -ENOTSUPP;
2755
2756         pr_info("Intel P-state driver initializing\n");
2757
2758         all_cpu_data = vzalloc(sizeof(void *) * num_possible_cpus());
2759         if (!all_cpu_data)
2760                 return -ENOMEM;
2761
2762         intel_pstate_request_control_from_smm();
2763
2764         intel_pstate_sysfs_expose_params();
2765
2766         mutex_lock(&intel_pstate_driver_lock);
2767         rc = intel_pstate_register_driver();
2768         mutex_unlock(&intel_pstate_driver_lock);
2769         if (rc)
2770                 return rc;
2771
2772         if (hwp_active)
2773                 pr_info("HWP enabled\n");
2774
2775         return 0;
2776 }
2777 device_initcall(intel_pstate_init);
2778
2779 static int __init intel_pstate_setup(char *str)
2780 {
2781         if (!str)
2782                 return -EINVAL;
2783
2784         if (!strcmp(str, "disable")) {
2785                 no_load = 1;
2786         } else if (!strcmp(str, "passive")) {
2787                 pr_info("Passive mode enabled\n");
2788                 intel_pstate_driver = &intel_cpufreq;
2789                 no_hwp = 1;
2790         }
2791         if (!strcmp(str, "no_hwp")) {
2792                 pr_info("HWP disabled\n");
2793                 no_hwp = 1;
2794         }
2795         if (!strcmp(str, "force"))
2796                 force_load = 1;
2797         if (!strcmp(str, "hwp_only"))
2798                 hwp_only = 1;
2799         if (!strcmp(str, "per_cpu_perf_limits"))
2800                 per_cpu_limits = true;
2801
2802 #ifdef CONFIG_ACPI
2803         if (!strcmp(str, "support_acpi_ppc"))
2804                 acpi_ppc = true;
2805 #endif
2806
2807         return 0;
2808 }
2809 early_param("intel_pstate", intel_pstate_setup);
2810
2811 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2812 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2813 MODULE_LICENSE("GPL");