2 * intel_pstate.c: Native P state management for Intel processors
4 * (C) Copyright 2012 Intel Corporation
5 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
15 #include <linux/kernel.h>
16 #include <linux/kernel_stat.h>
17 #include <linux/module.h>
18 #include <linux/ktime.h>
19 #include <linux/hrtimer.h>
20 #include <linux/tick.h>
21 #include <linux/slab.h>
22 #include <linux/sched/cpufreq.h>
23 #include <linux/list.h>
24 #include <linux/cpu.h>
25 #include <linux/cpufreq.h>
26 #include <linux/sysfs.h>
27 #include <linux/types.h>
29 #include <linux/acpi.h>
30 #include <linux/vmalloc.h>
31 #include <trace/events/power.h>
33 #include <asm/div64.h>
35 #include <asm/cpu_device_id.h>
36 #include <asm/cpufeature.h>
37 #include <asm/intel-family.h>
39 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
41 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
54 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
55 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
56 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
58 static inline int32_t mul_fp(int32_t x, int32_t y)
60 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 static inline int32_t div_fp(s64 x, s64 y)
65 return div64_s64((int64_t)x << FRAC_BITS, y);
68 static inline int ceiling_fp(int32_t x)
73 mask = (1 << FRAC_BITS) - 1;
79 static inline int32_t percent_fp(int percent)
81 return div_fp(percent, 100);
84 static inline u64 mul_ext_fp(u64 x, u64 y)
86 return (x * y) >> EXT_FRAC_BITS;
89 static inline u64 div_ext_fp(u64 x, u64 y)
91 return div64_u64(x << EXT_FRAC_BITS, y);
94 static inline int32_t percent_ext_fp(int percent)
96 return div_ext_fp(percent, 100);
100 * struct sample - Store performance sample
101 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
102 * performance during last sample period
103 * @busy_scaled: Scaled busy value which is used to calculate next
104 * P state. This can be different than core_avg_perf
105 * to account for cpu idle period
106 * @aperf: Difference of actual performance frequency clock count
107 * read from APERF MSR between last and current sample
108 * @mperf: Difference of maximum performance frequency clock count
109 * read from MPERF MSR between last and current sample
110 * @tsc: Difference of time stamp counter between last and
112 * @time: Current time from scheduler
114 * This structure is used in the cpudata structure to store performance sample
115 * data for choosing next P State.
118 int32_t core_avg_perf;
127 * struct pstate_data - Store P state data
128 * @current_pstate: Current requested P state
129 * @min_pstate: Min P state possible for this platform
130 * @max_pstate: Max P state possible for this platform
131 * @max_pstate_physical:This is physical Max P state for a processor
132 * This can be higher than the max_pstate which can
133 * be limited by platform thermal design power limits
134 * @scaling: Scaling factor to convert frequency to cpufreq
136 * @turbo_pstate: Max Turbo P state possible for this platform
137 * @max_freq: @max_pstate frequency in cpufreq units
138 * @turbo_freq: @turbo_pstate frequency in cpufreq units
140 * Stores the per cpu model P state limits and current P state.
146 int max_pstate_physical;
149 unsigned int max_freq;
150 unsigned int turbo_freq;
154 * struct vid_data - Stores voltage information data
155 * @min: VID data for this platform corresponding to
157 * @max: VID data corresponding to the highest P State.
158 * @turbo: VID data for turbo P state
159 * @ratio: Ratio of (vid max - vid min) /
160 * (max P state - Min P State)
162 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
163 * This data is used in Atom platforms, where in addition to target P state,
164 * the voltage data needs to be specified to select next P State.
174 * struct global_params - Global parameters, mostly tunable via sysfs.
175 * @no_turbo: Whether or not to use turbo P-states.
176 * @turbo_disabled: Whethet or not turbo P-states are available at all,
177 * based on the MSR_IA32_MISC_ENABLE value and whether or
178 * not the maximum reported turbo P-state is different from
179 * the maximum reported non-turbo one.
180 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
182 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
185 struct global_params {
193 * struct cpudata - Per CPU instance data storage
194 * @cpu: CPU number for this instance data
195 * @policy: CPUFreq policy value
196 * @update_util: CPUFreq utility callback information
197 * @update_util_set: CPUFreq utility callback is set
198 * @iowait_boost: iowait-related boost fraction
199 * @last_update: Time of the last update.
200 * @pstate: Stores P state limits for this CPU
201 * @vid: Stores VID limits for this CPU
202 * @last_sample_time: Last Sample time
203 * @aperf_mperf_shift: Number of clock cycles after aperf, merf is incremented
204 * This shift is a multiplier to mperf delta to
205 * calculate CPU busy.
206 * @prev_aperf: Last APERF value read from APERF MSR
207 * @prev_mperf: Last MPERF value read from MPERF MSR
208 * @prev_tsc: Last timestamp counter (TSC) value
209 * @prev_cummulative_iowait: IO Wait time difference from last and
211 * @sample: Storage for storing last Sample data
212 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
213 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
214 * @acpi_perf_data: Stores ACPI perf information read from _PSS
215 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
216 * @epp_powersave: Last saved HWP energy performance preference
217 * (EPP) or energy performance bias (EPB),
218 * when policy switched to performance
219 * @epp_policy: Last saved policy used to set EPP/EPB
220 * @epp_default: Power on default HWP energy performance
222 * @epp_saved: Saved EPP/EPB during system suspend or CPU offline
224 * @hwp_req_cached: Cached value of the last HWP Request MSR
225 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
226 * @last_io_update: Last time when IO wake flag was set
227 * @sched_flags: Store scheduler flags for possible cross CPU update
228 * @hwp_boost_min: Last HWP boosted min performance
230 * This structure stores per CPU instance data for all CPUs.
236 struct update_util_data update_util;
237 bool update_util_set;
239 struct pstate_data pstate;
243 u64 last_sample_time;
244 u64 aperf_mperf_shift;
248 u64 prev_cummulative_iowait;
249 struct sample sample;
250 int32_t min_perf_ratio;
251 int32_t max_perf_ratio;
253 struct acpi_processor_performance acpi_perf_data;
254 bool valid_pss_table;
256 unsigned int iowait_boost;
264 unsigned int sched_flags;
268 static struct cpudata **all_cpu_data;
271 * struct pstate_funcs - Per CPU model specific callbacks
272 * @get_max: Callback to get maximum non turbo effective P state
273 * @get_max_physical: Callback to get maximum non turbo physical P state
274 * @get_min: Callback to get minimum P state
275 * @get_turbo: Callback to get turbo P state
276 * @get_scaling: Callback to get frequency scaling factor
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
283 struct pstate_funcs {
284 int (*get_max)(void);
285 int (*get_max_physical)(void);
286 int (*get_min)(void);
287 int (*get_turbo)(void);
288 int (*get_scaling)(void);
289 int (*get_aperf_mperf_shift)(void);
290 u64 (*get_val)(struct cpudata*, int pstate);
291 void (*get_vid)(struct cpudata *);
294 static struct pstate_funcs pstate_funcs __read_mostly;
296 static int hwp_active __read_mostly;
297 static int hwp_mode_bdw __read_mostly;
298 static bool per_cpu_limits __read_mostly;
299 static bool hwp_boost __read_mostly;
301 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304 static bool acpi_ppc;
307 static struct global_params global;
309 static DEFINE_MUTEX(intel_pstate_driver_lock);
310 static DEFINE_MUTEX(intel_pstate_limits_lock);
314 static bool intel_pstate_acpi_pm_profile_server(void)
316 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
317 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
323 static bool intel_pstate_get_ppc_enable_status(void)
325 if (intel_pstate_acpi_pm_profile_server())
331 #ifdef CONFIG_ACPI_CPPC_LIB
333 /* The work item is needed to avoid CPU hotplug locking issues */
334 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
336 sched_set_itmt_support();
339 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
341 static void intel_pstate_set_itmt_prio(int cpu)
343 struct cppc_perf_caps cppc_perf;
344 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
347 ret = cppc_get_perf_caps(cpu, &cppc_perf);
352 * The priorities can be set regardless of whether or not
353 * sched_set_itmt_support(true) has been called and it is valid to
354 * update them at any time after it has been called.
356 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
358 if (max_highest_perf <= min_highest_perf) {
359 if (cppc_perf.highest_perf > max_highest_perf)
360 max_highest_perf = cppc_perf.highest_perf;
362 if (cppc_perf.highest_perf < min_highest_perf)
363 min_highest_perf = cppc_perf.highest_perf;
365 if (max_highest_perf > min_highest_perf) {
367 * This code can be run during CPU online under the
368 * CPU hotplug locks, so sched_set_itmt_support()
369 * cannot be called from here. Queue up a work item
372 schedule_work(&sched_itmt_work);
377 static void intel_pstate_set_itmt_prio(int cpu)
382 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
389 intel_pstate_set_itmt_prio(policy->cpu);
393 if (!intel_pstate_get_ppc_enable_status())
396 cpu = all_cpu_data[policy->cpu];
398 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
404 * Check if the control value in _PSS is for PERF_CTL MSR, which should
405 * guarantee that the states returned by it map to the states in our
408 if (cpu->acpi_perf_data.control_register.space_id !=
409 ACPI_ADR_SPACE_FIXED_HARDWARE)
413 * If there is only one entry _PSS, simply ignore _PSS and continue as
414 * usual without taking _PSS into account
416 if (cpu->acpi_perf_data.state_count < 2)
419 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
420 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
421 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
422 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
423 (u32) cpu->acpi_perf_data.states[i].core_frequency,
424 (u32) cpu->acpi_perf_data.states[i].power,
425 (u32) cpu->acpi_perf_data.states[i].control);
429 * The _PSS table doesn't contain whole turbo frequency range.
430 * This just contains +1 MHZ above the max non turbo frequency,
431 * with control value corresponding to max turbo ratio. But
432 * when cpufreq set policy is called, it will call with this
433 * max frequency, which will cause a reduced performance as
434 * this driver uses real max turbo frequency as the max
435 * frequency. So correct this frequency in _PSS table to
436 * correct max turbo frequency based on the turbo state.
437 * Also need to convert to MHz as _PSS freq is in MHz.
439 if (!global.turbo_disabled)
440 cpu->acpi_perf_data.states[0].core_frequency =
441 policy->cpuinfo.max_freq / 1000;
442 cpu->valid_pss_table = true;
443 pr_debug("_PPC limits will be enforced\n");
448 cpu->valid_pss_table = false;
449 acpi_processor_unregister_performance(policy->cpu);
452 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
456 cpu = all_cpu_data[policy->cpu];
457 if (!cpu->valid_pss_table)
460 acpi_processor_unregister_performance(policy->cpu);
463 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
467 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
471 static inline bool intel_pstate_acpi_pm_profile_server(void)
477 static inline void update_turbo_state(void)
482 cpu = all_cpu_data[0];
483 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
484 global.turbo_disabled =
485 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
486 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
489 static int min_perf_pct_min(void)
491 struct cpudata *cpu = all_cpu_data[0];
492 int turbo_pstate = cpu->pstate.turbo_pstate;
494 return turbo_pstate ?
495 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
498 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
503 if (!static_cpu_has(X86_FEATURE_EPB))
506 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
510 return (s16)(epb & 0x0f);
513 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
517 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
519 * When hwp_req_data is 0, means that caller didn't read
520 * MSR_HWP_REQUEST, so need to read and get EPP.
523 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
528 epp = (hwp_req_data >> 24) & 0xff;
530 /* When there is no EPP present, HWP uses EPB settings */
531 epp = intel_pstate_get_epb(cpu_data);
537 static int intel_pstate_set_epb(int cpu, s16 pref)
542 if (!static_cpu_has(X86_FEATURE_EPB))
545 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
549 epb = (epb & ~0x0f) | pref;
550 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
556 * EPP/EPB display strings corresponding to EPP index in the
557 * energy_perf_strings[]
559 *-------------------------------------
562 * 2 balance_performance
566 static const char * const energy_perf_strings[] = {
569 "balance_performance",
574 static const unsigned int epp_values[] = {
576 HWP_EPP_BALANCE_PERFORMANCE,
577 HWP_EPP_BALANCE_POWERSAVE,
581 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data)
586 epp = intel_pstate_get_epp(cpu_data, 0);
590 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
591 if (epp == HWP_EPP_PERFORMANCE)
593 if (epp <= HWP_EPP_BALANCE_PERFORMANCE)
595 if (epp <= HWP_EPP_BALANCE_POWERSAVE)
599 } else if (static_cpu_has(X86_FEATURE_EPB)) {
602 * 0x00-0x03 : Performance
603 * 0x04-0x07 : Balance performance
604 * 0x08-0x0B : Balance power
606 * The EPB is a 4 bit value, but our ranges restrict the
607 * value which can be set. Here only using top two bits
610 index = (epp >> 2) + 1;
616 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
623 epp = cpu_data->epp_default;
625 mutex_lock(&intel_pstate_limits_lock);
627 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
630 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, &value);
634 value &= ~GENMASK_ULL(31, 24);
637 epp = epp_values[pref_index - 1];
639 value |= (u64)epp << 24;
640 ret = wrmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST, value);
643 epp = (pref_index - 1) << 2;
644 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
647 mutex_unlock(&intel_pstate_limits_lock);
652 static ssize_t show_energy_performance_available_preferences(
653 struct cpufreq_policy *policy, char *buf)
658 while (energy_perf_strings[i] != NULL)
659 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
661 ret += sprintf(&buf[ret], "\n");
666 cpufreq_freq_attr_ro(energy_performance_available_preferences);
668 static ssize_t store_energy_performance_preference(
669 struct cpufreq_policy *policy, const char *buf, size_t count)
671 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
672 char str_preference[21];
675 ret = sscanf(buf, "%20s", str_preference);
679 while (energy_perf_strings[i] != NULL) {
680 if (!strcmp(str_preference, energy_perf_strings[i])) {
681 intel_pstate_set_energy_pref_index(cpu_data, i);
690 static ssize_t show_energy_performance_preference(
691 struct cpufreq_policy *policy, char *buf)
693 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
696 preference = intel_pstate_get_energy_pref_index(cpu_data);
700 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
703 cpufreq_freq_attr_rw(energy_performance_preference);
705 static struct freq_attr *hwp_cpufreq_attrs[] = {
706 &energy_performance_preference,
707 &energy_performance_available_preferences,
711 static void intel_pstate_get_hwp_max(unsigned int cpu, int *phy_max,
716 rdmsrl_on_cpu(cpu, MSR_HWP_CAPABILITIES, &cap);
717 WRITE_ONCE(all_cpu_data[cpu]->hwp_cap_cached, cap);
719 *current_max = HWP_GUARANTEED_PERF(cap);
721 *current_max = HWP_HIGHEST_PERF(cap);
723 *phy_max = HWP_HIGHEST_PERF(cap);
726 static void intel_pstate_hwp_set(unsigned int cpu)
728 struct cpudata *cpu_data = all_cpu_data[cpu];
733 max = cpu_data->max_perf_ratio;
734 min = cpu_data->min_perf_ratio;
736 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
739 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
741 value &= ~HWP_MIN_PERF(~0L);
742 value |= HWP_MIN_PERF(min);
744 value &= ~HWP_MAX_PERF(~0L);
745 value |= HWP_MAX_PERF(max);
747 if (cpu_data->epp_policy == cpu_data->policy)
750 cpu_data->epp_policy = cpu_data->policy;
752 if (cpu_data->epp_saved >= 0) {
753 epp = cpu_data->epp_saved;
754 cpu_data->epp_saved = -EINVAL;
758 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
759 epp = intel_pstate_get_epp(cpu_data, value);
760 cpu_data->epp_powersave = epp;
761 /* If EPP read was failed, then don't try to write */
767 /* skip setting EPP, when saved value is invalid */
768 if (cpu_data->epp_powersave < 0)
772 * No need to restore EPP when it is not zero. This
774 * - Policy is not changed
775 * - user has manually changed
776 * - Error reading EPB
778 epp = intel_pstate_get_epp(cpu_data, value);
782 epp = cpu_data->epp_powersave;
785 if (static_cpu_has(X86_FEATURE_HWP_EPP)) {
786 value &= ~GENMASK_ULL(31, 24);
787 value |= (u64)epp << 24;
789 intel_pstate_set_epb(cpu, epp);
792 WRITE_ONCE(cpu_data->hwp_req_cached, value);
793 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
796 static int intel_pstate_hwp_save_state(struct cpufreq_policy *policy)
798 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
803 cpu_data->epp_saved = intel_pstate_get_epp(cpu_data, 0);
808 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
810 static int intel_pstate_resume(struct cpufreq_policy *policy)
815 mutex_lock(&intel_pstate_limits_lock);
817 if (policy->cpu == 0)
818 intel_pstate_hwp_enable(all_cpu_data[policy->cpu]);
820 all_cpu_data[policy->cpu]->epp_policy = 0;
821 intel_pstate_hwp_set(policy->cpu);
823 mutex_unlock(&intel_pstate_limits_lock);
828 static void intel_pstate_update_policies(void)
832 for_each_possible_cpu(cpu)
833 cpufreq_update_policy(cpu);
836 /************************** sysfs begin ************************/
837 #define show_one(file_name, object) \
838 static ssize_t show_##file_name \
839 (struct kobject *kobj, struct attribute *attr, char *buf) \
841 return sprintf(buf, "%u\n", global.object); \
844 static ssize_t intel_pstate_show_status(char *buf);
845 static int intel_pstate_update_status(const char *buf, size_t size);
847 static ssize_t show_status(struct kobject *kobj,
848 struct attribute *attr, char *buf)
852 mutex_lock(&intel_pstate_driver_lock);
853 ret = intel_pstate_show_status(buf);
854 mutex_unlock(&intel_pstate_driver_lock);
859 static ssize_t store_status(struct kobject *a, struct attribute *b,
860 const char *buf, size_t count)
862 char *p = memchr(buf, '\n', count);
865 mutex_lock(&intel_pstate_driver_lock);
866 ret = intel_pstate_update_status(buf, p ? p - buf : count);
867 mutex_unlock(&intel_pstate_driver_lock);
869 return ret < 0 ? ret : count;
872 static ssize_t show_turbo_pct(struct kobject *kobj,
873 struct attribute *attr, char *buf)
876 int total, no_turbo, turbo_pct;
879 mutex_lock(&intel_pstate_driver_lock);
881 if (!intel_pstate_driver) {
882 mutex_unlock(&intel_pstate_driver_lock);
886 cpu = all_cpu_data[0];
888 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
889 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
890 turbo_fp = div_fp(no_turbo, total);
891 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
893 mutex_unlock(&intel_pstate_driver_lock);
895 return sprintf(buf, "%u\n", turbo_pct);
898 static ssize_t show_num_pstates(struct kobject *kobj,
899 struct attribute *attr, char *buf)
904 mutex_lock(&intel_pstate_driver_lock);
906 if (!intel_pstate_driver) {
907 mutex_unlock(&intel_pstate_driver_lock);
911 cpu = all_cpu_data[0];
912 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
914 mutex_unlock(&intel_pstate_driver_lock);
916 return sprintf(buf, "%u\n", total);
919 static ssize_t show_no_turbo(struct kobject *kobj,
920 struct attribute *attr, char *buf)
924 mutex_lock(&intel_pstate_driver_lock);
926 if (!intel_pstate_driver) {
927 mutex_unlock(&intel_pstate_driver_lock);
931 update_turbo_state();
932 if (global.turbo_disabled)
933 ret = sprintf(buf, "%u\n", global.turbo_disabled);
935 ret = sprintf(buf, "%u\n", global.no_turbo);
937 mutex_unlock(&intel_pstate_driver_lock);
942 static ssize_t store_no_turbo(struct kobject *a, struct attribute *b,
943 const char *buf, size_t count)
948 ret = sscanf(buf, "%u", &input);
952 mutex_lock(&intel_pstate_driver_lock);
954 if (!intel_pstate_driver) {
955 mutex_unlock(&intel_pstate_driver_lock);
959 mutex_lock(&intel_pstate_limits_lock);
961 update_turbo_state();
962 if (global.turbo_disabled) {
963 pr_warn("Turbo disabled by BIOS or unavailable on processor\n");
964 mutex_unlock(&intel_pstate_limits_lock);
965 mutex_unlock(&intel_pstate_driver_lock);
969 global.no_turbo = clamp_t(int, input, 0, 1);
971 if (global.no_turbo) {
972 struct cpudata *cpu = all_cpu_data[0];
973 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
975 /* Squash the global minimum into the permitted range. */
976 if (global.min_perf_pct > pct)
977 global.min_perf_pct = pct;
980 mutex_unlock(&intel_pstate_limits_lock);
982 intel_pstate_update_policies();
984 mutex_unlock(&intel_pstate_driver_lock);
989 static ssize_t store_max_perf_pct(struct kobject *a, struct attribute *b,
990 const char *buf, size_t count)
995 ret = sscanf(buf, "%u", &input);
999 mutex_lock(&intel_pstate_driver_lock);
1001 if (!intel_pstate_driver) {
1002 mutex_unlock(&intel_pstate_driver_lock);
1006 mutex_lock(&intel_pstate_limits_lock);
1008 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1010 mutex_unlock(&intel_pstate_limits_lock);
1012 intel_pstate_update_policies();
1014 mutex_unlock(&intel_pstate_driver_lock);
1019 static ssize_t store_min_perf_pct(struct kobject *a, struct attribute *b,
1020 const char *buf, size_t count)
1025 ret = sscanf(buf, "%u", &input);
1029 mutex_lock(&intel_pstate_driver_lock);
1031 if (!intel_pstate_driver) {
1032 mutex_unlock(&intel_pstate_driver_lock);
1036 mutex_lock(&intel_pstate_limits_lock);
1038 global.min_perf_pct = clamp_t(int, input,
1039 min_perf_pct_min(), global.max_perf_pct);
1041 mutex_unlock(&intel_pstate_limits_lock);
1043 intel_pstate_update_policies();
1045 mutex_unlock(&intel_pstate_driver_lock);
1050 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1051 struct attribute *attr, char *buf)
1053 return sprintf(buf, "%u\n", hwp_boost);
1056 static ssize_t store_hwp_dynamic_boost(struct kobject *a, struct attribute *b,
1057 const char *buf, size_t count)
1062 ret = kstrtouint(buf, 10, &input);
1066 mutex_lock(&intel_pstate_driver_lock);
1067 hwp_boost = !!input;
1068 intel_pstate_update_policies();
1069 mutex_unlock(&intel_pstate_driver_lock);
1074 show_one(max_perf_pct, max_perf_pct);
1075 show_one(min_perf_pct, min_perf_pct);
1077 define_one_global_rw(status);
1078 define_one_global_rw(no_turbo);
1079 define_one_global_rw(max_perf_pct);
1080 define_one_global_rw(min_perf_pct);
1081 define_one_global_ro(turbo_pct);
1082 define_one_global_ro(num_pstates);
1083 define_one_global_rw(hwp_dynamic_boost);
1085 static struct attribute *intel_pstate_attributes[] = {
1093 static const struct attribute_group intel_pstate_attr_group = {
1094 .attrs = intel_pstate_attributes,
1097 static void __init intel_pstate_sysfs_expose_params(void)
1099 struct kobject *intel_pstate_kobject;
1102 intel_pstate_kobject = kobject_create_and_add("intel_pstate",
1103 &cpu_subsys.dev_root->kobj);
1104 if (WARN_ON(!intel_pstate_kobject))
1107 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1112 * If per cpu limits are enforced there are no global limits, so
1113 * return without creating max/min_perf_pct attributes
1118 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1121 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1125 rc = sysfs_create_file(intel_pstate_kobject,
1126 &hwp_dynamic_boost.attr);
1130 /************************** sysfs end ************************/
1132 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1134 /* First disable HWP notification interrupt as we don't process them */
1135 if (static_cpu_has(X86_FEATURE_HWP_NOTIFY))
1136 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1138 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1139 cpudata->epp_policy = 0;
1140 if (cpudata->epp_default == -EINVAL)
1141 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1144 #define MSR_IA32_POWER_CTL_BIT_EE 19
1146 /* Disable energy efficiency optimization */
1147 static void intel_pstate_disable_ee(int cpu)
1152 ret = rdmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, &power_ctl);
1156 if (!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE))) {
1157 pr_info("Disabling energy efficiency optimization\n");
1158 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1159 wrmsrl_on_cpu(cpu, MSR_IA32_POWER_CTL, power_ctl);
1163 static int atom_get_min_pstate(void)
1167 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1168 return (value >> 8) & 0x7F;
1171 static int atom_get_max_pstate(void)
1175 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1176 return (value >> 16) & 0x7F;
1179 static int atom_get_turbo_pstate(void)
1183 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1184 return value & 0x7F;
1187 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1193 val = (u64)pstate << 8;
1194 if (global.no_turbo && !global.turbo_disabled)
1195 val |= (u64)1 << 32;
1197 vid_fp = cpudata->vid.min + mul_fp(
1198 int_tofp(pstate - cpudata->pstate.min_pstate),
1199 cpudata->vid.ratio);
1201 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1202 vid = ceiling_fp(vid_fp);
1204 if (pstate > cpudata->pstate.max_pstate)
1205 vid = cpudata->vid.turbo;
1210 static int silvermont_get_scaling(void)
1214 /* Defined in Table 35-6 from SDM (Sept 2015) */
1215 static int silvermont_freq_table[] = {
1216 83300, 100000, 133300, 116700, 80000};
1218 rdmsrl(MSR_FSB_FREQ, value);
1222 return silvermont_freq_table[i];
1225 static int airmont_get_scaling(void)
1229 /* Defined in Table 35-10 from SDM (Sept 2015) */
1230 static int airmont_freq_table[] = {
1231 83300, 100000, 133300, 116700, 80000,
1232 93300, 90000, 88900, 87500};
1234 rdmsrl(MSR_FSB_FREQ, value);
1238 return airmont_freq_table[i];
1241 static void atom_get_vid(struct cpudata *cpudata)
1245 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1246 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1247 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1248 cpudata->vid.ratio = div_fp(
1249 cpudata->vid.max - cpudata->vid.min,
1250 int_tofp(cpudata->pstate.max_pstate -
1251 cpudata->pstate.min_pstate));
1253 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1254 cpudata->vid.turbo = value & 0x7f;
1257 static int core_get_min_pstate(void)
1261 rdmsrl(MSR_PLATFORM_INFO, value);
1262 return (value >> 40) & 0xFF;
1265 static int core_get_max_pstate_physical(void)
1269 rdmsrl(MSR_PLATFORM_INFO, value);
1270 return (value >> 8) & 0xFF;
1273 static int core_get_tdp_ratio(u64 plat_info)
1275 /* Check how many TDP levels present */
1276 if (plat_info & 0x600000000) {
1282 /* Get the TDP level (0, 1, 2) to get ratios */
1283 err = rdmsrl_safe(MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1287 /* TDP MSR are continuous starting at 0x648 */
1288 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1289 err = rdmsrl_safe(tdp_msr, &tdp_ratio);
1293 /* For level 1 and 2, bits[23:16] contain the ratio */
1294 if (tdp_ctrl & 0x03)
1297 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1298 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1300 return (int)tdp_ratio;
1306 static int core_get_max_pstate(void)
1314 rdmsrl(MSR_PLATFORM_INFO, plat_info);
1315 max_pstate = (plat_info >> 8) & 0xFF;
1317 tdp_ratio = core_get_tdp_ratio(plat_info);
1322 /* Turbo activation ratio is not used on HWP platforms */
1326 err = rdmsrl_safe(MSR_TURBO_ACTIVATION_RATIO, &tar);
1330 /* Do some sanity checking for safety */
1331 tar_levels = tar & 0xff;
1332 if (tdp_ratio - 1 == tar_levels) {
1333 max_pstate = tar_levels;
1334 pr_debug("max_pstate=TAC %x\n", max_pstate);
1341 static int core_get_turbo_pstate(void)
1346 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1347 nont = core_get_max_pstate();
1348 ret = (value) & 255;
1354 static inline int core_get_scaling(void)
1359 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1363 val = (u64)pstate << 8;
1364 if (global.no_turbo && !global.turbo_disabled)
1365 val |= (u64)1 << 32;
1370 static int knl_get_aperf_mperf_shift(void)
1375 static int knl_get_turbo_pstate(void)
1380 rdmsrl(MSR_TURBO_RATIO_LIMIT, value);
1381 nont = core_get_max_pstate();
1382 ret = (((value) >> 8) & 0xFF);
1388 static int intel_pstate_get_base_pstate(struct cpudata *cpu)
1390 return global.no_turbo || global.turbo_disabled ?
1391 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1394 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
1396 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
1397 cpu->pstate.current_pstate = pstate;
1399 * Generally, there is no guarantee that this code will always run on
1400 * the CPU being updated, so force the register update to run on the
1403 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
1404 pstate_funcs.get_val(cpu, pstate));
1407 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
1409 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
1412 static void intel_pstate_max_within_limits(struct cpudata *cpu)
1416 update_turbo_state();
1417 pstate = intel_pstate_get_base_pstate(cpu);
1418 pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
1419 intel_pstate_set_pstate(cpu, pstate);
1422 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
1424 cpu->pstate.min_pstate = pstate_funcs.get_min();
1425 cpu->pstate.max_pstate = pstate_funcs.get_max();
1426 cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
1427 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
1428 cpu->pstate.scaling = pstate_funcs.get_scaling();
1429 cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
1431 if (hwp_active && !hwp_mode_bdw) {
1432 unsigned int phy_max, current_max;
1434 intel_pstate_get_hwp_max(cpu->cpu, &phy_max, ¤t_max);
1435 cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
1437 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
1440 if (pstate_funcs.get_aperf_mperf_shift)
1441 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
1443 if (pstate_funcs.get_vid)
1444 pstate_funcs.get_vid(cpu);
1446 intel_pstate_set_min_pstate(cpu);
1450 * Long hold time will keep high perf limits for long time,
1451 * which negatively impacts perf/watt for some workloads,
1452 * like specpower. 3ms is based on experiements on some
1455 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
1457 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
1459 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
1460 u32 max_limit = (hwp_req & 0xff00) >> 8;
1461 u32 min_limit = (hwp_req & 0xff);
1465 * Cases to consider (User changes via sysfs or boot time):
1466 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
1468 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
1469 * Should result in one level boost only for P0.
1470 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
1471 * Should result in two level boost:
1472 * (min + p1)/2 and P1.
1473 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
1474 * Should result in three level boost:
1475 * (min + p1)/2, P1 and P0.
1478 /* If max and min are equal or already at max, nothing to boost */
1479 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
1482 if (!cpu->hwp_boost_min)
1483 cpu->hwp_boost_min = min_limit;
1485 /* level at half way mark between min and guranteed */
1486 boost_level1 = (HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) + min_limit) >> 1;
1488 if (cpu->hwp_boost_min < boost_level1)
1489 cpu->hwp_boost_min = boost_level1;
1490 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1491 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(cpu->hwp_cap_cached);
1492 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(cpu->hwp_cap_cached) &&
1493 max_limit != HWP_GUARANTEED_PERF(cpu->hwp_cap_cached))
1494 cpu->hwp_boost_min = max_limit;
1498 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
1499 wrmsrl(MSR_HWP_REQUEST, hwp_req);
1500 cpu->last_update = cpu->sample.time;
1503 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
1505 if (cpu->hwp_boost_min) {
1508 /* Check if we are idle for hold time to boost down */
1509 expired = time_after64(cpu->sample.time, cpu->last_update +
1510 hwp_boost_hold_time_ns);
1512 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
1513 cpu->hwp_boost_min = 0;
1516 cpu->last_update = cpu->sample.time;
1519 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
1522 cpu->sample.time = time;
1524 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
1527 cpu->sched_flags = 0;
1529 * Set iowait_boost flag and update time. Since IO WAIT flag
1530 * is set all the time, we can't just conclude that there is
1531 * some IO bound activity is scheduled on this CPU with just
1532 * one occurrence. If we receive at least two in two
1533 * consecutive ticks, then we treat as boost candidate.
1535 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
1538 cpu->last_io_update = time;
1541 intel_pstate_hwp_boost_up(cpu);
1544 intel_pstate_hwp_boost_down(cpu);
1548 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
1549 u64 time, unsigned int flags)
1551 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1553 cpu->sched_flags |= flags;
1555 if (smp_processor_id() == cpu->cpu)
1556 intel_pstate_update_util_hwp_local(cpu, time);
1559 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
1561 struct sample *sample = &cpu->sample;
1563 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
1566 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
1569 unsigned long flags;
1572 local_irq_save(flags);
1573 rdmsrl(MSR_IA32_APERF, aperf);
1574 rdmsrl(MSR_IA32_MPERF, mperf);
1576 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
1577 local_irq_restore(flags);
1580 local_irq_restore(flags);
1582 cpu->last_sample_time = cpu->sample.time;
1583 cpu->sample.time = time;
1584 cpu->sample.aperf = aperf;
1585 cpu->sample.mperf = mperf;
1586 cpu->sample.tsc = tsc;
1587 cpu->sample.aperf -= cpu->prev_aperf;
1588 cpu->sample.mperf -= cpu->prev_mperf;
1589 cpu->sample.tsc -= cpu->prev_tsc;
1591 cpu->prev_aperf = aperf;
1592 cpu->prev_mperf = mperf;
1593 cpu->prev_tsc = tsc;
1595 * First time this function is invoked in a given cycle, all of the
1596 * previous sample data fields are equal to zero or stale and they must
1597 * be populated with meaningful numbers for things to work, so assume
1598 * that sample.time will always be reset before setting the utilization
1599 * update hook and make the caller skip the sample then.
1601 if (cpu->last_sample_time) {
1602 intel_pstate_calc_avg_perf(cpu);
1608 static inline int32_t get_avg_frequency(struct cpudata *cpu)
1610 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
1613 static inline int32_t get_avg_pstate(struct cpudata *cpu)
1615 return mul_ext_fp(cpu->pstate.max_pstate_physical,
1616 cpu->sample.core_avg_perf);
1619 static inline int32_t get_target_pstate(struct cpudata *cpu)
1621 struct sample *sample = &cpu->sample;
1622 int32_t busy_frac, boost;
1623 int target, avg_pstate;
1625 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
1628 boost = cpu->iowait_boost;
1629 cpu->iowait_boost >>= 1;
1631 if (busy_frac < boost)
1634 sample->busy_scaled = busy_frac * 100;
1636 target = global.no_turbo || global.turbo_disabled ?
1637 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
1638 target += target >> 2;
1639 target = mul_fp(target, busy_frac);
1640 if (target < cpu->pstate.min_pstate)
1641 target = cpu->pstate.min_pstate;
1644 * If the average P-state during the previous cycle was higher than the
1645 * current target, add 50% of the difference to the target to reduce
1646 * possible performance oscillations and offset possible performance
1647 * loss related to moving the workload from one CPU to another within
1650 avg_pstate = get_avg_pstate(cpu);
1651 if (avg_pstate > target)
1652 target += (avg_pstate - target) >> 1;
1657 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
1659 int max_pstate = intel_pstate_get_base_pstate(cpu);
1662 min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
1663 max_pstate = max(min_pstate, cpu->max_perf_ratio);
1664 return clamp_t(int, pstate, min_pstate, max_pstate);
1667 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
1669 if (pstate == cpu->pstate.current_pstate)
1672 cpu->pstate.current_pstate = pstate;
1673 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
1676 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
1678 int from = cpu->pstate.current_pstate;
1679 struct sample *sample;
1682 update_turbo_state();
1684 target_pstate = get_target_pstate(cpu);
1685 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
1686 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
1687 intel_pstate_update_pstate(cpu, target_pstate);
1689 sample = &cpu->sample;
1690 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
1691 fp_toint(sample->busy_scaled),
1693 cpu->pstate.current_pstate,
1697 get_avg_frequency(cpu),
1698 fp_toint(cpu->iowait_boost * 100));
1701 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
1704 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
1707 /* Don't allow remote callbacks */
1708 if (smp_processor_id() != cpu->cpu)
1711 if (flags & SCHED_CPUFREQ_IOWAIT) {
1712 cpu->iowait_boost = int_tofp(1);
1713 cpu->last_update = time;
1715 * The last time the busy was 100% so P-state was max anyway
1716 * so avoid overhead of computation.
1718 if (fp_toint(cpu->sample.busy_scaled) == 100)
1722 } else if (cpu->iowait_boost) {
1723 /* Clear iowait_boost if the CPU may have been idle. */
1724 delta_ns = time - cpu->last_update;
1725 if (delta_ns > TICK_NSEC)
1726 cpu->iowait_boost = 0;
1728 cpu->last_update = time;
1729 delta_ns = time - cpu->sample.time;
1730 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
1734 if (intel_pstate_sample(cpu, time))
1735 intel_pstate_adjust_pstate(cpu);
1738 static struct pstate_funcs core_funcs = {
1739 .get_max = core_get_max_pstate,
1740 .get_max_physical = core_get_max_pstate_physical,
1741 .get_min = core_get_min_pstate,
1742 .get_turbo = core_get_turbo_pstate,
1743 .get_scaling = core_get_scaling,
1744 .get_val = core_get_val,
1747 static const struct pstate_funcs silvermont_funcs = {
1748 .get_max = atom_get_max_pstate,
1749 .get_max_physical = atom_get_max_pstate,
1750 .get_min = atom_get_min_pstate,
1751 .get_turbo = atom_get_turbo_pstate,
1752 .get_val = atom_get_val,
1753 .get_scaling = silvermont_get_scaling,
1754 .get_vid = atom_get_vid,
1757 static const struct pstate_funcs airmont_funcs = {
1758 .get_max = atom_get_max_pstate,
1759 .get_max_physical = atom_get_max_pstate,
1760 .get_min = atom_get_min_pstate,
1761 .get_turbo = atom_get_turbo_pstate,
1762 .get_val = atom_get_val,
1763 .get_scaling = airmont_get_scaling,
1764 .get_vid = atom_get_vid,
1767 static const struct pstate_funcs knl_funcs = {
1768 .get_max = core_get_max_pstate,
1769 .get_max_physical = core_get_max_pstate_physical,
1770 .get_min = core_get_min_pstate,
1771 .get_turbo = knl_get_turbo_pstate,
1772 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
1773 .get_scaling = core_get_scaling,
1774 .get_val = core_get_val,
1777 #define ICPU(model, policy) \
1778 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF,\
1779 (unsigned long)&policy }
1781 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
1782 ICPU(INTEL_FAM6_SANDYBRIDGE, core_funcs),
1783 ICPU(INTEL_FAM6_SANDYBRIDGE_X, core_funcs),
1784 ICPU(INTEL_FAM6_ATOM_SILVERMONT1, silvermont_funcs),
1785 ICPU(INTEL_FAM6_IVYBRIDGE, core_funcs),
1786 ICPU(INTEL_FAM6_HASWELL_CORE, core_funcs),
1787 ICPU(INTEL_FAM6_BROADWELL_CORE, core_funcs),
1788 ICPU(INTEL_FAM6_IVYBRIDGE_X, core_funcs),
1789 ICPU(INTEL_FAM6_HASWELL_X, core_funcs),
1790 ICPU(INTEL_FAM6_HASWELL_ULT, core_funcs),
1791 ICPU(INTEL_FAM6_HASWELL_GT3E, core_funcs),
1792 ICPU(INTEL_FAM6_BROADWELL_GT3E, core_funcs),
1793 ICPU(INTEL_FAM6_ATOM_AIRMONT, airmont_funcs),
1794 ICPU(INTEL_FAM6_SKYLAKE_MOBILE, core_funcs),
1795 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1796 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1797 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1798 ICPU(INTEL_FAM6_XEON_PHI_KNL, knl_funcs),
1799 ICPU(INTEL_FAM6_XEON_PHI_KNM, knl_funcs),
1800 ICPU(INTEL_FAM6_ATOM_GOLDMONT, core_funcs),
1801 ICPU(INTEL_FAM6_ATOM_GEMINI_LAKE, core_funcs),
1802 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1805 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
1807 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
1808 ICPU(INTEL_FAM6_BROADWELL_XEON_D, core_funcs),
1809 ICPU(INTEL_FAM6_BROADWELL_X, core_funcs),
1810 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1814 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
1815 ICPU(INTEL_FAM6_KABYLAKE_DESKTOP, core_funcs),
1819 static const struct x86_cpu_id intel_pstate_hwp_boost_ids[] = {
1820 ICPU(INTEL_FAM6_SKYLAKE_X, core_funcs),
1821 ICPU(INTEL_FAM6_SKYLAKE_DESKTOP, core_funcs),
1825 static int intel_pstate_init_cpu(unsigned int cpunum)
1827 struct cpudata *cpu;
1829 cpu = all_cpu_data[cpunum];
1832 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
1836 all_cpu_data[cpunum] = cpu;
1838 cpu->epp_default = -EINVAL;
1839 cpu->epp_powersave = -EINVAL;
1840 cpu->epp_saved = -EINVAL;
1843 cpu = all_cpu_data[cpunum];
1848 const struct x86_cpu_id *id;
1850 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
1852 intel_pstate_disable_ee(cpunum);
1854 intel_pstate_hwp_enable(cpu);
1856 id = x86_match_cpu(intel_pstate_hwp_boost_ids);
1857 if (id && intel_pstate_acpi_pm_profile_server())
1861 intel_pstate_get_cpu_pstates(cpu);
1863 pr_debug("controlling: cpu %d\n", cpunum);
1868 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
1870 struct cpudata *cpu = all_cpu_data[cpu_num];
1872 if (hwp_active && !hwp_boost)
1875 if (cpu->update_util_set)
1878 /* Prevent intel_pstate_update_util() from using stale data. */
1879 cpu->sample.time = 0;
1880 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
1882 intel_pstate_update_util_hwp :
1883 intel_pstate_update_util));
1884 cpu->update_util_set = true;
1887 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
1889 struct cpudata *cpu_data = all_cpu_data[cpu];
1891 if (!cpu_data->update_util_set)
1894 cpufreq_remove_update_util_hook(cpu);
1895 cpu_data->update_util_set = false;
1896 synchronize_sched();
1899 static int intel_pstate_get_max_freq(struct cpudata *cpu)
1901 return global.turbo_disabled || global.no_turbo ?
1902 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
1905 static void intel_pstate_update_perf_limits(struct cpufreq_policy *policy,
1906 struct cpudata *cpu)
1908 int max_freq = intel_pstate_get_max_freq(cpu);
1909 int32_t max_policy_perf, min_policy_perf;
1910 int max_state, turbo_max;
1913 * HWP needs some special consideration, because on BDX the
1914 * HWP_REQUEST uses abstract value to represent performance
1915 * rather than pure ratios.
1918 intel_pstate_get_hwp_max(cpu->cpu, &turbo_max, &max_state);
1920 max_state = intel_pstate_get_base_pstate(cpu);
1921 turbo_max = cpu->pstate.turbo_pstate;
1924 max_policy_perf = max_state * policy->max / max_freq;
1925 if (policy->max == policy->min) {
1926 min_policy_perf = max_policy_perf;
1928 min_policy_perf = max_state * policy->min / max_freq;
1929 min_policy_perf = clamp_t(int32_t, min_policy_perf,
1930 0, max_policy_perf);
1933 pr_debug("cpu:%d max_state %d min_policy_perf:%d max_policy_perf:%d\n",
1934 policy->cpu, max_state,
1935 min_policy_perf, max_policy_perf);
1937 /* Normalize user input to [min_perf, max_perf] */
1938 if (per_cpu_limits) {
1939 cpu->min_perf_ratio = min_policy_perf;
1940 cpu->max_perf_ratio = max_policy_perf;
1942 int32_t global_min, global_max;
1944 /* Global limits are in percent of the maximum turbo P-state. */
1945 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
1946 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
1947 global_min = clamp_t(int32_t, global_min, 0, global_max);
1949 pr_debug("cpu:%d global_min:%d global_max:%d\n", policy->cpu,
1950 global_min, global_max);
1952 cpu->min_perf_ratio = max(min_policy_perf, global_min);
1953 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
1954 cpu->max_perf_ratio = min(max_policy_perf, global_max);
1955 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
1957 /* Make sure min_perf <= max_perf */
1958 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
1959 cpu->max_perf_ratio);
1962 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", policy->cpu,
1963 cpu->max_perf_ratio,
1964 cpu->min_perf_ratio);
1967 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
1969 struct cpudata *cpu;
1971 if (!policy->cpuinfo.max_freq)
1974 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
1975 policy->cpuinfo.max_freq, policy->max);
1977 cpu = all_cpu_data[policy->cpu];
1978 cpu->policy = policy->policy;
1980 mutex_lock(&intel_pstate_limits_lock);
1982 intel_pstate_update_perf_limits(policy, cpu);
1984 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
1986 * NOHZ_FULL CPUs need this as the governor callback may not
1987 * be invoked on them.
1989 intel_pstate_clear_update_util_hook(policy->cpu);
1990 intel_pstate_max_within_limits(cpu);
1992 intel_pstate_set_update_util_hook(policy->cpu);
1997 * When hwp_boost was active before and dynamically it
1998 * was turned off, in that case we need to clear the
2002 intel_pstate_clear_update_util_hook(policy->cpu);
2003 intel_pstate_hwp_set(policy->cpu);
2006 mutex_unlock(&intel_pstate_limits_lock);
2011 static void intel_pstate_adjust_policy_max(struct cpufreq_policy *policy,
2012 struct cpudata *cpu)
2014 if (cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2015 policy->max < policy->cpuinfo.max_freq &&
2016 policy->max > cpu->pstate.max_freq) {
2017 pr_debug("policy->max > max non turbo frequency\n");
2018 policy->max = policy->cpuinfo.max_freq;
2022 static int intel_pstate_verify_policy(struct cpufreq_policy *policy)
2024 struct cpudata *cpu = all_cpu_data[policy->cpu];
2026 update_turbo_state();
2027 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2028 intel_pstate_get_max_freq(cpu));
2030 if (policy->policy != CPUFREQ_POLICY_POWERSAVE &&
2031 policy->policy != CPUFREQ_POLICY_PERFORMANCE)
2034 intel_pstate_adjust_policy_max(policy, cpu);
2039 static void intel_cpufreq_stop_cpu(struct cpufreq_policy *policy)
2041 intel_pstate_set_min_pstate(all_cpu_data[policy->cpu]);
2044 static void intel_pstate_stop_cpu(struct cpufreq_policy *policy)
2046 pr_debug("CPU %d exiting\n", policy->cpu);
2048 intel_pstate_clear_update_util_hook(policy->cpu);
2050 intel_pstate_hwp_save_state(policy);
2052 intel_cpufreq_stop_cpu(policy);
2055 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2057 intel_pstate_exit_perf_limits(policy);
2059 policy->fast_switch_possible = false;
2064 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2066 struct cpudata *cpu;
2069 rc = intel_pstate_init_cpu(policy->cpu);
2073 cpu = all_cpu_data[policy->cpu];
2075 cpu->max_perf_ratio = 0xFF;
2076 cpu->min_perf_ratio = 0;
2078 policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
2079 policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
2081 /* cpuinfo and default policy values */
2082 policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
2083 update_turbo_state();
2084 policy->cpuinfo.max_freq = global.turbo_disabled ?
2085 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2086 policy->cpuinfo.max_freq *= cpu->pstate.scaling;
2088 intel_pstate_init_acpi_perf_limits(policy);
2090 policy->fast_switch_possible = true;
2095 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2097 int ret = __intel_pstate_cpu_init(policy);
2102 if (IS_ENABLED(CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE))
2103 policy->policy = CPUFREQ_POLICY_PERFORMANCE;
2105 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2110 static struct cpufreq_driver intel_pstate = {
2111 .flags = CPUFREQ_CONST_LOOPS,
2112 .verify = intel_pstate_verify_policy,
2113 .setpolicy = intel_pstate_set_policy,
2114 .suspend = intel_pstate_hwp_save_state,
2115 .resume = intel_pstate_resume,
2116 .init = intel_pstate_cpu_init,
2117 .exit = intel_pstate_cpu_exit,
2118 .stop_cpu = intel_pstate_stop_cpu,
2119 .name = "intel_pstate",
2122 static int intel_cpufreq_verify_policy(struct cpufreq_policy *policy)
2124 struct cpudata *cpu = all_cpu_data[policy->cpu];
2126 update_turbo_state();
2127 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq,
2128 intel_pstate_get_max_freq(cpu));
2130 intel_pstate_adjust_policy_max(policy, cpu);
2132 intel_pstate_update_perf_limits(policy, cpu);
2137 /* Use of trace in passive mode:
2139 * In passive mode the trace core_busy field (also known as the
2140 * performance field, and lablelled as such on the graphs; also known as
2141 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2142 * driver call was via the normal or fast switch path. Various graphs
2143 * output from the intel_pstate_tracer.py utility that include core_busy
2144 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2145 * so we use 10 to indicate the the normal path through the driver, and
2146 * 90 to indicate the fast switch path through the driver.
2147 * The scaled_busy field is not used, and is set to 0.
2150 #define INTEL_PSTATE_TRACE_TARGET 10
2151 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2153 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2155 struct sample *sample;
2157 if (!trace_pstate_sample_enabled())
2160 if (!intel_pstate_sample(cpu, ktime_get()))
2163 sample = &cpu->sample;
2164 trace_pstate_sample(trace_type,
2167 cpu->pstate.current_pstate,
2171 get_avg_frequency(cpu),
2172 fp_toint(cpu->iowait_boost * 100));
2175 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2176 unsigned int target_freq,
2177 unsigned int relation)
2179 struct cpudata *cpu = all_cpu_data[policy->cpu];
2180 struct cpufreq_freqs freqs;
2181 int target_pstate, old_pstate;
2183 update_turbo_state();
2185 freqs.old = policy->cur;
2186 freqs.new = target_freq;
2188 cpufreq_freq_transition_begin(policy, &freqs);
2190 case CPUFREQ_RELATION_L:
2191 target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
2193 case CPUFREQ_RELATION_H:
2194 target_pstate = freqs.new / cpu->pstate.scaling;
2197 target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
2200 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2201 old_pstate = cpu->pstate.current_pstate;
2202 if (target_pstate != cpu->pstate.current_pstate) {
2203 cpu->pstate.current_pstate = target_pstate;
2204 wrmsrl_on_cpu(policy->cpu, MSR_IA32_PERF_CTL,
2205 pstate_funcs.get_val(cpu, target_pstate));
2207 freqs.new = target_pstate * cpu->pstate.scaling;
2208 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_TARGET, old_pstate);
2209 cpufreq_freq_transition_end(policy, &freqs, false);
2214 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2215 unsigned int target_freq)
2217 struct cpudata *cpu = all_cpu_data[policy->cpu];
2218 int target_pstate, old_pstate;
2220 update_turbo_state();
2222 target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
2223 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2224 old_pstate = cpu->pstate.current_pstate;
2225 intel_pstate_update_pstate(cpu, target_pstate);
2226 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
2227 return target_pstate * cpu->pstate.scaling;
2230 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
2232 int ret = __intel_pstate_cpu_init(policy);
2237 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
2238 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
2239 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
2240 policy->cur = policy->cpuinfo.min_freq;
2245 static struct cpufreq_driver intel_cpufreq = {
2246 .flags = CPUFREQ_CONST_LOOPS,
2247 .verify = intel_cpufreq_verify_policy,
2248 .target = intel_cpufreq_target,
2249 .fast_switch = intel_cpufreq_fast_switch,
2250 .init = intel_cpufreq_cpu_init,
2251 .exit = intel_pstate_cpu_exit,
2252 .stop_cpu = intel_cpufreq_stop_cpu,
2253 .name = "intel_cpufreq",
2256 static struct cpufreq_driver *default_driver = &intel_pstate;
2258 static void intel_pstate_driver_cleanup(void)
2263 for_each_online_cpu(cpu) {
2264 if (all_cpu_data[cpu]) {
2265 if (intel_pstate_driver == &intel_pstate)
2266 intel_pstate_clear_update_util_hook(cpu);
2268 kfree(all_cpu_data[cpu]);
2269 all_cpu_data[cpu] = NULL;
2273 intel_pstate_driver = NULL;
2276 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
2280 memset(&global, 0, sizeof(global));
2281 global.max_perf_pct = 100;
2283 intel_pstate_driver = driver;
2284 ret = cpufreq_register_driver(intel_pstate_driver);
2286 intel_pstate_driver_cleanup();
2290 global.min_perf_pct = min_perf_pct_min();
2295 static int intel_pstate_unregister_driver(void)
2300 cpufreq_unregister_driver(intel_pstate_driver);
2301 intel_pstate_driver_cleanup();
2306 static ssize_t intel_pstate_show_status(char *buf)
2308 if (!intel_pstate_driver)
2309 return sprintf(buf, "off\n");
2311 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
2312 "active" : "passive");
2315 static int intel_pstate_update_status(const char *buf, size_t size)
2319 if (size == 3 && !strncmp(buf, "off", size))
2320 return intel_pstate_driver ?
2321 intel_pstate_unregister_driver() : -EINVAL;
2323 if (size == 6 && !strncmp(buf, "active", size)) {
2324 if (intel_pstate_driver) {
2325 if (intel_pstate_driver == &intel_pstate)
2328 ret = intel_pstate_unregister_driver();
2333 return intel_pstate_register_driver(&intel_pstate);
2336 if (size == 7 && !strncmp(buf, "passive", size)) {
2337 if (intel_pstate_driver) {
2338 if (intel_pstate_driver == &intel_cpufreq)
2341 ret = intel_pstate_unregister_driver();
2346 return intel_pstate_register_driver(&intel_cpufreq);
2352 static int no_load __initdata;
2353 static int no_hwp __initdata;
2354 static int hwp_only __initdata;
2355 static unsigned int force_load __initdata;
2357 static int __init intel_pstate_msrs_not_valid(void)
2359 if (!pstate_funcs.get_max() ||
2360 !pstate_funcs.get_min() ||
2361 !pstate_funcs.get_turbo())
2367 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
2369 pstate_funcs.get_max = funcs->get_max;
2370 pstate_funcs.get_max_physical = funcs->get_max_physical;
2371 pstate_funcs.get_min = funcs->get_min;
2372 pstate_funcs.get_turbo = funcs->get_turbo;
2373 pstate_funcs.get_scaling = funcs->get_scaling;
2374 pstate_funcs.get_val = funcs->get_val;
2375 pstate_funcs.get_vid = funcs->get_vid;
2376 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
2381 static bool __init intel_pstate_no_acpi_pss(void)
2385 for_each_possible_cpu(i) {
2387 union acpi_object *pss;
2388 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
2389 struct acpi_processor *pr = per_cpu(processors, i);
2394 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
2395 if (ACPI_FAILURE(status))
2398 pss = buffer.pointer;
2399 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
2410 static bool __init intel_pstate_no_acpi_pcch(void)
2415 status = acpi_get_handle(NULL, "\\_SB", &handle);
2416 if (ACPI_FAILURE(status))
2419 return !acpi_has_method(handle, "PCCH");
2422 static bool __init intel_pstate_has_acpi_ppc(void)
2426 for_each_possible_cpu(i) {
2427 struct acpi_processor *pr = per_cpu(processors, i);
2431 if (acpi_has_method(pr->handle, "_PPC"))
2442 /* Hardware vendor-specific info that has its own power management modes */
2443 static struct acpi_platform_list plat_info[] __initdata = {
2444 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, 0, PSS},
2445 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2446 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2447 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2448 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2449 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2450 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2451 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2452 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2453 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2454 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2455 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2456 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2457 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2458 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, 0, PPC},
2462 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
2464 const struct x86_cpu_id *id;
2468 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
2470 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
2471 if ( misc_pwr & (1 << 8))
2475 idx = acpi_match_platform_list(plat_info);
2479 switch (plat_info[idx].data) {
2481 if (!intel_pstate_no_acpi_pss())
2484 return intel_pstate_no_acpi_pcch();
2486 return intel_pstate_has_acpi_ppc() && !force_load;
2492 static void intel_pstate_request_control_from_smm(void)
2495 * It may be unsafe to request P-states control from SMM if _PPC support
2496 * has not been enabled.
2499 acpi_processor_pstate_control();
2501 #else /* CONFIG_ACPI not enabled */
2502 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
2503 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
2504 static inline void intel_pstate_request_control_from_smm(void) {}
2505 #endif /* CONFIG_ACPI */
2507 #define INTEL_PSTATE_HWP_BROADWELL 0x01
2509 #define ICPU_HWP(model, hwp_mode) \
2510 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_HWP, hwp_mode }
2512 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
2513 ICPU_HWP(INTEL_FAM6_BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
2514 ICPU_HWP(INTEL_FAM6_BROADWELL_XEON_D, INTEL_PSTATE_HWP_BROADWELL),
2515 ICPU_HWP(X86_MODEL_ANY, 0),
2519 static int __init intel_pstate_init(void)
2521 const struct x86_cpu_id *id;
2527 id = x86_match_cpu(hwp_support_ids);
2529 copy_cpu_funcs(&core_funcs);
2532 hwp_mode_bdw = id->driver_data;
2533 intel_pstate.attr = hwp_cpufreq_attrs;
2534 goto hwp_cpu_matched;
2537 id = x86_match_cpu(intel_pstate_cpu_ids);
2541 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
2544 if (intel_pstate_msrs_not_valid())
2549 * The Intel pstate driver will be ignored if the platform
2550 * firmware has its own power management modes.
2552 if (intel_pstate_platform_pwr_mgmt_exists())
2555 if (!hwp_active && hwp_only)
2558 pr_info("Intel P-state driver initializing\n");
2560 all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
2564 intel_pstate_request_control_from_smm();
2566 intel_pstate_sysfs_expose_params();
2568 mutex_lock(&intel_pstate_driver_lock);
2569 rc = intel_pstate_register_driver(default_driver);
2570 mutex_unlock(&intel_pstate_driver_lock);
2575 pr_info("HWP enabled\n");
2579 device_initcall(intel_pstate_init);
2581 static int __init intel_pstate_setup(char *str)
2586 if (!strcmp(str, "disable")) {
2588 } else if (!strcmp(str, "passive")) {
2589 pr_info("Passive mode enabled\n");
2590 default_driver = &intel_cpufreq;
2593 if (!strcmp(str, "no_hwp")) {
2594 pr_info("HWP disabled\n");
2597 if (!strcmp(str, "force"))
2599 if (!strcmp(str, "hwp_only"))
2601 if (!strcmp(str, "per_cpu_perf_limits"))
2602 per_cpu_limits = true;
2605 if (!strcmp(str, "support_acpi_ppc"))
2611 early_param("intel_pstate", intel_pstate_setup);
2613 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
2614 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
2615 MODULE_LICENSE("GPL");