arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #include "kvm_onhyperv.h"
  47 #include "svm_onhyperv.h"
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 #ifdef MODULE
  53 static const struct x86_cpu_id svm_cpu_id[] = {
  54         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  55         {}
  56 };
  57 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  58 #endif
  59
  60 #define SEG_TYPE_LDT 2
  61 #define SEG_TYPE_BUSY_TSS16 3
  62
  63 #define SVM_FEATURE_LBRV           (1 <<  1)
  64 #define SVM_FEATURE_SVML           (1 <<  2)
  65 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  66 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  67 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  68 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  69 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  70
  71 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  72
  73 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  74 #define TSC_RATIO_MIN           0x0000000000000001ULL
  75 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  76
  77 static bool erratum_383_found __read_mostly;
  78
  79 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  80
  81 /*
  82  * Set osvw_len to higher value when updated Revision Guides
  83  * are published and we know what the new status bits are
  84  */
  85 static uint64_t osvw_len = 4, osvw_status;
  86
  87 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  88 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  89
  90 static const struct svm_direct_access_msrs {
  91         u32 index;   /* Index of the MSR */
  92         bool always; /* True if intercept is initially cleared */
  93 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  94         { .index = MSR_STAR,                            .always = true  },
  95         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  96         { .index = MSR_IA32_SYSENTER_EIP,               .always = false },
  97         { .index = MSR_IA32_SYSENTER_ESP,               .always = false },
  98 #ifdef CONFIG_X86_64
  99         { .index = MSR_GS_BASE,                         .always = true  },
 100         { .index = MSR_FS_BASE,                         .always = true  },
 101         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 102         { .index = MSR_LSTAR,                           .always = true  },
 103         { .index = MSR_CSTAR,                           .always = true  },
 104         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 105 #endif
 106         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 107         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 108         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 109         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 110         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 111         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 112         { .index = MSR_EFER,                            .always = false },
 113         { .index = MSR_IA32_CR_PAT,                     .always = false },
 114         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 115         { .index = MSR_INVALID,                         .always = false },
 116 };
 117
 118 /*
 119  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 120  * pause_filter_count: On processors that support Pause filtering(indicated
 121  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 122  *      count value. On VMRUN this value is loaded into an internal counter.
 123  *      Each time a pause instruction is executed, this counter is decremented
 124  *      until it reaches zero at which time a #VMEXIT is generated if pause
 125  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 126  *      Intercept Filtering for more details.
 127  *      This also indicate if ple logic enabled.
 128  *
 129  * pause_filter_thresh: In addition, some processor families support advanced
 130  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 131  *      the amount of time a guest is allowed to execute in a pause loop.
 132  *      In this mode, a 16-bit pause filter threshold field is added in the
 133  *      VMCB. The threshold value is a cycle count that is used to reset the
 134  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 135  *      count value from VMCB into an internal counter. Then, on each pause
 136  *      instruction the hardware checks the elapsed number of cycles since
 137  *      the most recent pause instruction against the pause filter threshold.
 138  *      If the elapsed cycle count is greater than the pause filter threshold,
 139  *      then the internal pause count is reloaded from the VMCB and execution
 140  *      continues. If the elapsed cycle count is less than the pause filter
 141  *      threshold, then the internal pause count is decremented. If the count
 142  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 143  *      triggered. If advanced pause filtering is supported and pause filter
 144  *      threshold field is set to zero, the filter will operate in the simpler,
 145  *      count only mode.
 146  */
 147
 148 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 149 module_param(pause_filter_thresh, ushort, 0444);
 150
 151 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 152 module_param(pause_filter_count, ushort, 0444);
 153
 154 /* Default doubles per-vcpu window every exit. */
 155 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 156 module_param(pause_filter_count_grow, ushort, 0444);
 157
 158 /* Default resets per-vcpu window every exit to pause_filter_count. */
 159 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 160 module_param(pause_filter_count_shrink, ushort, 0444);
 161
 162 /* Default is to compute the maximum so we can never overflow. */
 163 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 164 module_param(pause_filter_count_max, ushort, 0444);
 165
 166 /*
 167  * Use nested page tables by default.  Note, NPT may get forced off by
 168  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 169  */
 170 bool npt_enabled = true;
 171 module_param_named(npt, npt_enabled, bool, 0444);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /*
 190  * enable / disable AVIC.  Because the defaults differ for APICv
 191  * support between VMX and SVM we cannot use module_param_named.
 192  */
 193 static bool avic;
 194 module_param(avic, bool, 0444);
 195
 196 bool __read_mostly dump_invalid_vmcb;
 197 module_param(dump_invalid_vmcb, bool, 0644);
 198
 199
 200 bool intercept_smi = true;
 201 module_param(intercept_smi, bool, 0444);
 202
 203
 204 static bool svm_gp_erratum_intercept = true;
 205
 206 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 207
 208 static unsigned long iopm_base;
 209
 210 struct kvm_ldttss_desc {
 211         u16 limit0;
 212         u16 base0;
 213         unsigned base1:8, type:5, dpl:2, p:1;
 214         unsigned limit1:4, zero0:3, g:1, base2:8;
 215         u32 base3;
 216         u32 zero1;
 217 } __attribute__((packed));
 218
 219 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 220
 221 /*
 222  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 223  * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
 224  *
 225  * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
 226  * defer the restoration of TSC_AUX until the CPU returns to userspace.
 227  */
 228 static int tsc_aux_uret_slot __read_mostly = -1;
 229
 230 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 231
 232 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 233 #define MSRS_RANGE_SIZE 2048
 234 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 235
 236 u32 svm_msrpm_offset(u32 msr)
 237 {
 238         u32 offset;
 239         int i;
 240
 241         for (i = 0; i < NUM_MSR_MAPS; i++) {
 242                 if (msr < msrpm_ranges[i] ||
 243                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 244                         continue;
 245
 246                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 247                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 248
 249                 /* Now we have the u8 offset - but need the u32 offset */
 250                 return offset / 4;
 251         }
 252
 253         /* MSR not in any range */
 254         return MSR_INVALID;
 255 }
 256
 257 #define MAX_INST_SIZE 15
 258
 259 static int get_max_npt_level(void)
 260 {
 261 #ifdef CONFIG_X86_64
 262         return PT64_ROOT_4LEVEL;
 263 #else
 264         return PT32E_ROOT_LEVEL;
 265 #endif
 266 }
 267
 268 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 269 {
 270         struct vcpu_svm *svm = to_svm(vcpu);
 271         u64 old_efer = vcpu->arch.efer;
 272         vcpu->arch.efer = efer;
 273
 274         if (!npt_enabled) {
 275                 /* Shadow paging assumes NX to be available.  */
 276                 efer |= EFER_NX;
 277
 278                 if (!(efer & EFER_LMA))
 279                         efer &= ~EFER_LME;
 280         }
 281
 282         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 283                 if (!(efer & EFER_SVME)) {
 284                         svm_leave_nested(svm);
 285                         svm_set_gif(svm, true);
 286                         /* #GP intercept is still needed for vmware backdoor */
 287                         if (!enable_vmware_backdoor)
 288                                 clr_exception_intercept(svm, GP_VECTOR);
 289
 290                         /*
 291                          * Free the nested guest state, unless we are in SMM.
 292                          * In this case we will return to the nested guest
 293                          * as soon as we leave SMM.
 294                          */
 295                         if (!is_smm(vcpu))
 296                                 svm_free_nested(svm);
 297
 298                 } else {
 299                         int ret = svm_allocate_nested(svm);
 300
 301                         if (ret) {
 302                                 vcpu->arch.efer = old_efer;
 303                                 return ret;
 304                         }
 305
 306                         if (svm_gp_erratum_intercept)
 307                                 set_exception_intercept(svm, GP_VECTOR);
 308                 }
 309         }
 310
 311         svm->vmcb->save.efer = efer | EFER_SVME;
 312         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 313         return 0;
 314 }
 315
 316 static int is_external_interrupt(u32 info)
 317 {
 318         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 319         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 320 }
 321
 322 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 323 {
 324         struct vcpu_svm *svm = to_svm(vcpu);
 325         u32 ret = 0;
 326
 327         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 328                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 329         return ret;
 330 }
 331
 332 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 333 {
 334         struct vcpu_svm *svm = to_svm(vcpu);
 335
 336         if (mask == 0)
 337                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 338         else
 339                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 340
 341 }
 342
 343 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 344 {
 345         struct vcpu_svm *svm = to_svm(vcpu);
 346
 347         /*
 348          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 349          * the type of exit and the #VC handler in the guest.
 350          */
 351         if (sev_es_guest(vcpu->kvm))
 352                 goto done;
 353
 354         if (nrips && svm->vmcb->control.next_rip != 0) {
 355                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 356                 svm->next_rip = svm->vmcb->control.next_rip;
 357         }
 358
 359         if (!svm->next_rip) {
 360                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 361                         return 0;
 362         } else {
 363                 kvm_rip_write(vcpu, svm->next_rip);
 364         }
 365
 366 done:
 367         svm_set_interrupt_shadow(vcpu, 0);
 368
 369         return 1;
 370 }
 371
 372 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 373 {
 374         struct vcpu_svm *svm = to_svm(vcpu);
 375         unsigned nr = vcpu->arch.exception.nr;
 376         bool has_error_code = vcpu->arch.exception.has_error_code;
 377         u32 error_code = vcpu->arch.exception.error_code;
 378
 379         kvm_deliver_exception_payload(vcpu);
 380
 381         if (nr == BP_VECTOR && !nrips) {
 382                 unsigned long rip, old_rip = kvm_rip_read(vcpu);
 383
 384                 /*
 385                  * For guest debugging where we have to reinject #BP if some
 386                  * INT3 is guest-owned:
 387                  * Emulate nRIP by moving RIP forward. Will fail if injection
 388                  * raises a fault that is not intercepted. Still better than
 389                  * failing in all cases.
 390                  */
 391                 (void)skip_emulated_instruction(vcpu);
 392                 rip = kvm_rip_read(vcpu);
 393                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 394                 svm->int3_injected = rip - old_rip;
 395         }
 396
 397         svm->vmcb->control.event_inj = nr
 398                 | SVM_EVTINJ_VALID
 399                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 400                 | SVM_EVTINJ_TYPE_EXEPT;
 401         svm->vmcb->control.event_inj_err = error_code;
 402 }
 403
 404 static void svm_init_erratum_383(void)
 405 {
 406         u32 low, high;
 407         int err;
 408         u64 val;
 409
 410         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 411                 return;
 412
 413         /* Use _safe variants to not break nested virtualization */
 414         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 415         if (err)
 416                 return;
 417
 418         val |= (1ULL << 47);
 419
 420         low  = lower_32_bits(val);
 421         high = upper_32_bits(val);
 422
 423         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 424
 425         erratum_383_found = true;
 426 }
 427
 428 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 429 {
 430         /*
 431          * Guests should see errata 400 and 415 as fixed (assuming that
 432          * HLT and IO instructions are intercepted).
 433          */
 434         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 435         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 436
 437         /*
 438          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 439          * all osvw.status bits inside that length, including bit 0 (which is
 440          * reserved for erratum 298), are valid. However, if host processor's
 441          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 442          * be conservative here and therefore we tell the guest that erratum 298
 443          * is present (because we really don't know).
 444          */
 445         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 446                 vcpu->arch.osvw.status |= 1;
 447 }
 448
 449 static int has_svm(void)
 450 {
 451         const char *msg;
 452
 453         if (!cpu_has_svm(&msg)) {
 454                 printk(KERN_INFO "has_svm: %s\n", msg);
 455                 return 0;
 456         }
 457
 458         if (sev_active()) {
 459                 pr_info("KVM is unsupported when running as an SEV guest\n");
 460                 return 0;
 461         }
 462
 463         if (pgtable_l5_enabled()) {
 464                 pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
 465                 return 0;
 466         }
 467
 468         return 1;
 469 }
 470
 471 static void svm_hardware_disable(void)
 472 {
 473         /* Make sure we clean up behind us */
 474         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 475                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 476
 477         cpu_svm_disable();
 478
 479         amd_pmu_disable_virt();
 480 }
 481
 482 static int svm_hardware_enable(void)
 483 {
 484
 485         struct svm_cpu_data *sd;
 486         uint64_t efer;
 487         struct desc_struct *gdt;
 488         int me = raw_smp_processor_id();
 489
 490         rdmsrl(MSR_EFER, efer);
 491         if (efer & EFER_SVME)
 492                 return -EBUSY;
 493
 494         if (!has_svm()) {
 495                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 496                 return -EINVAL;
 497         }
 498         sd = per_cpu(svm_data, me);
 499         if (!sd) {
 500                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 501                 return -EINVAL;
 502         }
 503
 504         sd->asid_generation = 1;
 505         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 506         sd->next_asid = sd->max_asid + 1;
 507         sd->min_asid = max_sev_asid + 1;
 508
 509         gdt = get_current_gdt_rw();
 510         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 511
 512         wrmsrl(MSR_EFER, efer | EFER_SVME);
 513
 514         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 515
 516         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 517                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 518                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 519         }
 520
 521
 522         /*
 523          * Get OSVW bits.
 524          *
 525          * Note that it is possible to have a system with mixed processor
 526          * revisions and therefore different OSVW bits. If bits are not the same
 527          * on different processors then choose the worst case (i.e. if erratum
 528          * is present on one processor and not on another then assume that the
 529          * erratum is present everywhere).
 530          */
 531         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 532                 uint64_t len, status = 0;
 533                 int err;
 534
 535                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 536                 if (!err)
 537                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 538                                                       &err);
 539
 540                 if (err)
 541                         osvw_status = osvw_len = 0;
 542                 else {
 543                         if (len < osvw_len)
 544                                 osvw_len = len;
 545                         osvw_status |= status;
 546                         osvw_status &= (1ULL << osvw_len) - 1;
 547                 }
 548         } else
 549                 osvw_status = osvw_len = 0;
 550
 551         svm_init_erratum_383();
 552
 553         amd_pmu_enable_virt();
 554
 555         return 0;
 556 }
 557
 558 static void svm_cpu_uninit(int cpu)
 559 {
 560         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 561
 562         if (!sd)
 563                 return;
 564
 565         per_cpu(svm_data, cpu) = NULL;
 566         kfree(sd->sev_vmcbs);
 567         __free_page(sd->save_area);
 568         kfree(sd);
 569 }
 570
 571 static int svm_cpu_init(int cpu)
 572 {
 573         struct svm_cpu_data *sd;
 574         int ret = -ENOMEM;
 575
 576         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 577         if (!sd)
 578                 return ret;
 579         sd->cpu = cpu;
 580         sd->save_area = alloc_page(GFP_KERNEL);
 581         if (!sd->save_area)
 582                 goto free_cpu_data;
 583
 584         clear_page(page_address(sd->save_area));
 585
 586         ret = sev_cpu_init(sd);
 587         if (ret)
 588                 goto free_save_area;
 589
 590         per_cpu(svm_data, cpu) = sd;
 591
 592         return 0;
 593
 594 free_save_area:
 595         __free_page(sd->save_area);
 596 free_cpu_data:
 597         kfree(sd);
 598         return ret;
 599
 600 }
 601
 602 static int direct_access_msr_slot(u32 msr)
 603 {
 604         u32 i;
 605
 606         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 607                 if (direct_access_msrs[i].index == msr)
 608                         return i;
 609
 610         return -ENOENT;
 611 }
 612
 613 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 614                                      int write)
 615 {
 616         struct vcpu_svm *svm = to_svm(vcpu);
 617         int slot = direct_access_msr_slot(msr);
 618
 619         if (slot == -ENOENT)
 620                 return;
 621
 622         /* Set the shadow bitmaps to the desired intercept states */
 623         if (read)
 624                 set_bit(slot, svm->shadow_msr_intercept.read);
 625         else
 626                 clear_bit(slot, svm->shadow_msr_intercept.read);
 627
 628         if (write)
 629                 set_bit(slot, svm->shadow_msr_intercept.write);
 630         else
 631                 clear_bit(slot, svm->shadow_msr_intercept.write);
 632 }
 633
 634 static bool valid_msr_intercept(u32 index)
 635 {
 636         return direct_access_msr_slot(index) != -ENOENT;
 637 }
 638
 639 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 640 {
 641         u8 bit_write;
 642         unsigned long tmp;
 643         u32 offset;
 644         u32 *msrpm;
 645
 646         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 647                                       to_svm(vcpu)->msrpm;
 648
 649         offset    = svm_msrpm_offset(msr);
 650         bit_write = 2 * (msr & 0x0f) + 1;
 651         tmp       = msrpm[offset];
 652
 653         BUG_ON(offset == MSR_INVALID);
 654
 655         return !!test_bit(bit_write,  &tmp);
 656 }
 657
 658 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 659                                         u32 msr, int read, int write)
 660 {
 661         u8 bit_read, bit_write;
 662         unsigned long tmp;
 663         u32 offset;
 664
 665         /*
 666          * If this warning triggers extend the direct_access_msrs list at the
 667          * beginning of the file
 668          */
 669         WARN_ON(!valid_msr_intercept(msr));
 670
 671         /* Enforce non allowed MSRs to trap */
 672         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 673                 read = 0;
 674
 675         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 676                 write = 0;
 677
 678         offset    = svm_msrpm_offset(msr);
 679         bit_read  = 2 * (msr & 0x0f);
 680         bit_write = 2 * (msr & 0x0f) + 1;
 681         tmp       = msrpm[offset];
 682
 683         BUG_ON(offset == MSR_INVALID);
 684
 685         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 686         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 687
 688         msrpm[offset] = tmp;
 689
 690         svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
 691
 692 }
 693
 694 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 695                           int read, int write)
 696 {
 697         set_shadow_msr_intercept(vcpu, msr, read, write);
 698         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 699 }
 700
 701 u32 *svm_vcpu_alloc_msrpm(void)
 702 {
 703         unsigned int order = get_order(MSRPM_SIZE);
 704         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
 705         u32 *msrpm;
 706
 707         if (!pages)
 708                 return NULL;
 709
 710         msrpm = page_address(pages);
 711         memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
 712
 713         return msrpm;
 714 }
 715
 716 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 717 {
 718         int i;
 719
 720         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 721                 if (!direct_access_msrs[i].always)
 722                         continue;
 723                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 724         }
 725 }
 726
 727
 728 void svm_vcpu_free_msrpm(u32 *msrpm)
 729 {
 730         __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
 731 }
 732
 733 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 734 {
 735         struct vcpu_svm *svm = to_svm(vcpu);
 736         u32 i;
 737
 738         /*
 739          * Set intercept permissions for all direct access MSRs again. They
 740          * will automatically get filtered through the MSR filter, so we are
 741          * back in sync after this.
 742          */
 743         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 744                 u32 msr = direct_access_msrs[i].index;
 745                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 746                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 747
 748                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 749         }
 750 }
 751
 752 static void add_msr_offset(u32 offset)
 753 {
 754         int i;
 755
 756         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 757
 758                 /* Offset already in list? */
 759                 if (msrpm_offsets[i] == offset)
 760                         return;
 761
 762                 /* Slot used by another offset? */
 763                 if (msrpm_offsets[i] != MSR_INVALID)
 764                         continue;
 765
 766                 /* Add offset to list */
 767                 msrpm_offsets[i] = offset;
 768
 769                 return;
 770         }
 771
 772         /*
 773          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 774          * increase MSRPM_OFFSETS in this case.
 775          */
 776         BUG();
 777 }
 778
 779 static void init_msrpm_offsets(void)
 780 {
 781         int i;
 782
 783         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 784
 785         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 786                 u32 offset;
 787
 788                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 789                 BUG_ON(offset == MSR_INVALID);
 790
 791                 add_msr_offset(offset);
 792         }
 793 }
 794
 795 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 796 {
 797         struct vcpu_svm *svm = to_svm(vcpu);
 798
 799         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 800         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 801         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 802         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 803         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 804 }
 805
 806 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 807 {
 808         struct vcpu_svm *svm = to_svm(vcpu);
 809
 810         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 811         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 812         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 813         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 814         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 815 }
 816
 817 void disable_nmi_singlestep(struct vcpu_svm *svm)
 818 {
 819         svm->nmi_singlestep = false;
 820
 821         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 822                 /* Clear our flags if they were not set by the guest */
 823                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 824                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 825                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 826                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 827         }
 828 }
 829
 830 static void grow_ple_window(struct kvm_vcpu *vcpu)
 831 {
 832         struct vcpu_svm *svm = to_svm(vcpu);
 833         struct vmcb_control_area *control = &svm->vmcb->control;
 834         int old = control->pause_filter_count;
 835
 836         control->pause_filter_count = __grow_ple_window(old,
 837                                                         pause_filter_count,
 838                                                         pause_filter_count_grow,
 839                                                         pause_filter_count_max);
 840
 841         if (control->pause_filter_count != old) {
 842                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 843                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 844                                             control->pause_filter_count, old);
 845         }
 846 }
 847
 848 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 849 {
 850         struct vcpu_svm *svm = to_svm(vcpu);
 851         struct vmcb_control_area *control = &svm->vmcb->control;
 852         int old = control->pause_filter_count;
 853
 854         control->pause_filter_count =
 855                                 __shrink_ple_window(old,
 856                                                     pause_filter_count,
 857                                                     pause_filter_count_shrink,
 858                                                     pause_filter_count);
 859         if (control->pause_filter_count != old) {
 860                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 861                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 862                                             control->pause_filter_count, old);
 863         }
 864 }
 865
 866 /*
 867  * The default MMIO mask is a single bit (excluding the present bit),
 868  * which could conflict with the memory encryption bit. Check for
 869  * memory encryption support and override the default MMIO mask if
 870  * memory encryption is enabled.
 871  */
 872 static __init void svm_adjust_mmio_mask(void)
 873 {
 874         unsigned int enc_bit, mask_bit;
 875         u64 msr, mask;
 876
 877         /* If there is no memory encryption support, use existing mask */
 878         if (cpuid_eax(0x80000000) < 0x8000001f)
 879                 return;
 880
 881         /* If memory encryption is not enabled, use existing mask */
 882         rdmsrl(MSR_AMD64_SYSCFG, msr);
 883         if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
 884                 return;
 885
 886         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 887         mask_bit = boot_cpu_data.x86_phys_bits;
 888
 889         /* Increment the mask bit if it is the same as the encryption bit */
 890         if (enc_bit == mask_bit)
 891                 mask_bit++;
 892
 893         /*
 894          * If the mask bit location is below 52, then some bits above the
 895          * physical addressing limit will always be reserved, so use the
 896          * rsvd_bits() function to generate the mask. This mask, along with
 897          * the present bit, will be used to generate a page fault with
 898          * PFER.RSV = 1.
 899          *
 900          * If the mask bit location is 52 (or above), then clear the mask.
 901          */
 902         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 903
 904         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 905 }
 906
 907 static void svm_hardware_teardown(void)
 908 {
 909         int cpu;
 910
 911         sev_hardware_teardown();
 912
 913         for_each_possible_cpu(cpu)
 914                 svm_cpu_uninit(cpu);
 915
 916         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
 917         get_order(IOPM_SIZE));
 918         iopm_base = 0;
 919 }
 920
 921 static __init void svm_set_cpu_caps(void)
 922 {
 923         kvm_set_cpu_caps();
 924
 925         supported_xss = 0;
 926
 927         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 928         if (nested) {
 929                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 930
 931                 if (nrips)
 932                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 933
 934                 if (npt_enabled)
 935                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 936
 937                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 938                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 939         }
 940
 941         /* CPUID 0x80000008 */
 942         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 943             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 944                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 945
 946         /* CPUID 0x8000001F (SME/SEV features) */
 947         sev_set_cpu_caps();
 948 }
 949
 950 static __init int svm_hardware_setup(void)
 951 {
 952         int cpu;
 953         struct page *iopm_pages;
 954         void *iopm_va;
 955         int r;
 956         unsigned int order = get_order(IOPM_SIZE);
 957
 958         /*
 959          * NX is required for shadow paging and for NPT if the NX huge pages
 960          * mitigation is enabled.
 961          */
 962         if (!boot_cpu_has(X86_FEATURE_NX)) {
 963                 pr_err_ratelimited("NX (Execute Disable) not supported\n");
 964                 return -EOPNOTSUPP;
 965         }
 966         kvm_enable_efer_bits(EFER_NX);
 967
 968         iopm_pages = alloc_pages(GFP_KERNEL, order);
 969
 970         if (!iopm_pages)
 971                 return -ENOMEM;
 972
 973         iopm_va = page_address(iopm_pages);
 974         memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
 975         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 976
 977         init_msrpm_offsets();
 978
 979         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 980
 981         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 982                 kvm_enable_efer_bits(EFER_FFXSR);
 983
 984         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 985                 kvm_has_tsc_control = true;
 986                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 987                 kvm_tsc_scaling_ratio_frac_bits = 32;
 988         }
 989
 990         tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
 991
 992         /* Check for pause filtering support */
 993         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 994                 pause_filter_count = 0;
 995                 pause_filter_thresh = 0;
 996         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 997                 pause_filter_thresh = 0;
 998         }
 999
1000         if (nested) {
1001                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
1002                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
1003         }
1004
1005         /*
1006          * KVM's MMU doesn't support using 2-level paging for itself, and thus
1007          * NPT isn't supported if the host is using 2-level paging since host
1008          * CR4 is unchanged on VMRUN.
1009          */
1010         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
1011                 npt_enabled = false;
1012
1013         if (!boot_cpu_has(X86_FEATURE_NPT))
1014                 npt_enabled = false;
1015
1016         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
1017         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1018
1019         /* Note, SEV setup consumes npt_enabled. */
1020         sev_hardware_setup();
1021
1022         svm_hv_hardware_setup();
1023
1024         svm_adjust_mmio_mask();
1025
1026         for_each_possible_cpu(cpu) {
1027                 r = svm_cpu_init(cpu);
1028                 if (r)
1029                         goto err;
1030         }
1031
1032         if (nrips) {
1033                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1034                         nrips = false;
1035         }
1036
1037         enable_apicv = avic = avic && npt_enabled && boot_cpu_has(X86_FEATURE_AVIC);
1038
1039         if (enable_apicv) {
1040                 pr_info("AVIC enabled\n");
1041
1042                 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1043         }
1044
1045         if (vls) {
1046                 if (!npt_enabled ||
1047                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1048                     !IS_ENABLED(CONFIG_X86_64)) {
1049                         vls = false;
1050                 } else {
1051                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1052                 }
1053         }
1054
1055         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1056                 svm_gp_erratum_intercept = false;
1057
1058         if (vgif) {
1059                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1060                         vgif = false;
1061                 else
1062                         pr_info("Virtual GIF supported\n");
1063         }
1064
1065         svm_set_cpu_caps();
1066
1067         /*
1068          * It seems that on AMD processors PTE's accessed bit is
1069          * being set by the CPU hardware before the NPF vmexit.
1070          * This is not expected behaviour and our tests fail because
1071          * of it.
1072          * A workaround here is to disable support for
1073          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1074          * In this case userspace can know if there is support using
1075          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1076          * it
1077          * If future AMD CPU models change the behaviour described above,
1078          * this variable can be changed accordingly
1079          */
1080         allow_smaller_maxphyaddr = !npt_enabled;
1081
1082         return 0;
1083
1084 err:
1085         svm_hardware_teardown();
1086         return r;
1087 }
1088
1089 static void init_seg(struct vmcb_seg *seg)
1090 {
1091         seg->selector = 0;
1092         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1093                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1094         seg->limit = 0xffff;
1095         seg->base = 0;
1096 }
1097
1098 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1099 {
1100         seg->selector = 0;
1101         seg->attrib = SVM_SELECTOR_P_MASK | type;
1102         seg->limit = 0xffff;
1103         seg->base = 0;
1104 }
1105
1106 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1107 {
1108         struct vcpu_svm *svm = to_svm(vcpu);
1109
1110         return svm->nested.ctl.tsc_offset;
1111 }
1112
1113 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1114 {
1115         return kvm_default_tsc_scaling_ratio;
1116 }
1117
1118 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1119 {
1120         struct vcpu_svm *svm = to_svm(vcpu);
1121
1122         svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1123         svm->vmcb->control.tsc_offset = offset;
1124         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1125 }
1126
1127 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1128 {
1129         wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
1130 }
1131
1132 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1133 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1134                                               struct vcpu_svm *svm)
1135 {
1136         /*
1137          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1138          * roots, or if INVPCID is disabled in the guest to inject #UD.
1139          */
1140         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1141                 if (!npt_enabled ||
1142                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1143                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1144                 else
1145                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1146         }
1147
1148         if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1149                 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1150                         svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1151                 else
1152                         svm_set_intercept(svm, INTERCEPT_RDTSCP);
1153         }
1154 }
1155
1156 static void init_vmcb(struct kvm_vcpu *vcpu)
1157 {
1158         struct vcpu_svm *svm = to_svm(vcpu);
1159         struct vmcb_control_area *control = &svm->vmcb->control;
1160         struct vmcb_save_area *save = &svm->vmcb->save;
1161
1162         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1163         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1164         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1165         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1166         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1167         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1168         if (!kvm_vcpu_apicv_active(vcpu))
1169                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1170
1171         set_dr_intercepts(svm);
1172
1173         set_exception_intercept(svm, PF_VECTOR);
1174         set_exception_intercept(svm, UD_VECTOR);
1175         set_exception_intercept(svm, MC_VECTOR);
1176         set_exception_intercept(svm, AC_VECTOR);
1177         set_exception_intercept(svm, DB_VECTOR);
1178         /*
1179          * Guest access to VMware backdoor ports could legitimately
1180          * trigger #GP because of TSS I/O permission bitmap.
1181          * We intercept those #GP and allow access to them anyway
1182          * as VMware does.
1183          */
1184         if (enable_vmware_backdoor)
1185                 set_exception_intercept(svm, GP_VECTOR);
1186
1187         svm_set_intercept(svm, INTERCEPT_INTR);
1188         svm_set_intercept(svm, INTERCEPT_NMI);
1189
1190         if (intercept_smi)
1191                 svm_set_intercept(svm, INTERCEPT_SMI);
1192
1193         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1194         svm_set_intercept(svm, INTERCEPT_RDPMC);
1195         svm_set_intercept(svm, INTERCEPT_CPUID);
1196         svm_set_intercept(svm, INTERCEPT_INVD);
1197         svm_set_intercept(svm, INTERCEPT_INVLPG);
1198         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1199         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1200         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1201         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1202         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1203         svm_set_intercept(svm, INTERCEPT_VMRUN);
1204         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1205         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1206         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1207         svm_set_intercept(svm, INTERCEPT_STGI);
1208         svm_set_intercept(svm, INTERCEPT_CLGI);
1209         svm_set_intercept(svm, INTERCEPT_SKINIT);
1210         svm_set_intercept(svm, INTERCEPT_WBINVD);
1211         svm_set_intercept(svm, INTERCEPT_XSETBV);
1212         svm_set_intercept(svm, INTERCEPT_RDPRU);
1213         svm_set_intercept(svm, INTERCEPT_RSM);
1214
1215         if (!kvm_mwait_in_guest(vcpu->kvm)) {
1216                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1217                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1218         }
1219
1220         if (!kvm_hlt_in_guest(vcpu->kvm))
1221                 svm_set_intercept(svm, INTERCEPT_HLT);
1222
1223         control->iopm_base_pa = __sme_set(iopm_base);
1224         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1225         control->int_ctl = V_INTR_MASKING_MASK;
1226
1227         init_seg(&save->es);
1228         init_seg(&save->ss);
1229         init_seg(&save->ds);
1230         init_seg(&save->fs);
1231         init_seg(&save->gs);
1232
1233         save->cs.selector = 0xf000;
1234         save->cs.base = 0xffff0000;
1235         /* Executable/Readable Code Segment */
1236         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1237                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1238         save->cs.limit = 0xffff;
1239
1240         save->gdtr.base = 0;
1241         save->gdtr.limit = 0xffff;
1242         save->idtr.base = 0;
1243         save->idtr.limit = 0xffff;
1244
1245         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1246         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1247
1248         if (npt_enabled) {
1249                 /* Setup VMCB for Nested Paging */
1250                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1251                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1252                 clr_exception_intercept(svm, PF_VECTOR);
1253                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1254                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1255                 save->g_pat = vcpu->arch.pat;
1256                 save->cr3 = 0;
1257         }
1258         svm->current_vmcb->asid_generation = 0;
1259         svm->asid = 0;
1260
1261         svm->nested.vmcb12_gpa = INVALID_GPA;
1262         svm->nested.last_vmcb12_gpa = INVALID_GPA;
1263
1264         if (!kvm_pause_in_guest(vcpu->kvm)) {
1265                 control->pause_filter_count = pause_filter_count;
1266                 if (pause_filter_thresh)
1267                         control->pause_filter_thresh = pause_filter_thresh;
1268                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1269         } else {
1270                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1271         }
1272
1273         svm_recalc_instruction_intercepts(vcpu, svm);
1274
1275         /*
1276          * If the host supports V_SPEC_CTRL then disable the interception
1277          * of MSR_IA32_SPEC_CTRL.
1278          */
1279         if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1280                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1281
1282         if (kvm_vcpu_apicv_active(vcpu))
1283                 avic_init_vmcb(svm);
1284
1285         if (vgif) {
1286                 svm_clr_intercept(svm, INTERCEPT_STGI);
1287                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1288                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1289         }
1290
1291         if (sev_guest(vcpu->kvm)) {
1292                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1293                 clr_exception_intercept(svm, UD_VECTOR);
1294
1295                 if (sev_es_guest(vcpu->kvm)) {
1296                         /* Perform SEV-ES specific VMCB updates */
1297                         sev_es_init_vmcb(svm);
1298                 }
1299         }
1300
1301         svm_hv_init_vmcb(svm->vmcb);
1302
1303         vmcb_mark_all_dirty(svm->vmcb);
1304
1305         enable_gif(svm);
1306
1307 }
1308
1309 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1310 {
1311         struct vcpu_svm *svm = to_svm(vcpu);
1312
1313         svm->spec_ctrl = 0;
1314         svm->virt_spec_ctrl = 0;
1315
1316         init_vmcb(vcpu);
1317
1318         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1319                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1320 }
1321
1322 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1323 {
1324         svm->current_vmcb = target_vmcb;
1325         svm->vmcb = target_vmcb->ptr;
1326 }
1327
1328 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1329 {
1330         struct vcpu_svm *svm;
1331         struct page *vmcb01_page;
1332         struct page *vmsa_page = NULL;
1333         int err;
1334
1335         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1336         svm = to_svm(vcpu);
1337
1338         err = -ENOMEM;
1339         vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1340         if (!vmcb01_page)
1341                 goto out;
1342
1343         if (sev_es_guest(vcpu->kvm)) {
1344                 /*
1345                  * SEV-ES guests require a separate VMSA page used to contain
1346                  * the encrypted register state of the guest.
1347                  */
1348                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1349                 if (!vmsa_page)
1350                         goto error_free_vmcb_page;
1351
1352                 /*
1353                  * SEV-ES guests maintain an encrypted version of their FPU
1354                  * state which is restored and saved on VMRUN and VMEXIT.
1355                  * Free the fpu structure to prevent KVM from attempting to
1356                  * access the FPU state.
1357                  */
1358                 kvm_free_guest_fpu(vcpu);
1359         }
1360
1361         err = avic_init_vcpu(svm);
1362         if (err)
1363                 goto error_free_vmsa_page;
1364
1365         /* We initialize this flag to true to make sure that the is_running
1366          * bit would be set the first time the vcpu is loaded.
1367          */
1368         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1369                 svm->avic_is_running = true;
1370
1371         svm->msrpm = svm_vcpu_alloc_msrpm();
1372         if (!svm->msrpm) {
1373                 err = -ENOMEM;
1374                 goto error_free_vmsa_page;
1375         }
1376
1377         svm->vmcb01.ptr = page_address(vmcb01_page);
1378         svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1379
1380         if (vmsa_page)
1381                 svm->vmsa = page_address(vmsa_page);
1382
1383         svm->guest_state_loaded = false;
1384
1385         svm_switch_vmcb(svm, &svm->vmcb01);
1386         init_vmcb(vcpu);
1387
1388         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1389
1390         svm_init_osvw(vcpu);
1391         vcpu->arch.microcode_version = 0x01000065;
1392
1393         if (sev_es_guest(vcpu->kvm))
1394                 /* Perform SEV-ES specific VMCB creation updates */
1395                 sev_es_create_vcpu(svm);
1396
1397         return 0;
1398
1399 error_free_vmsa_page:
1400         if (vmsa_page)
1401                 __free_page(vmsa_page);
1402 error_free_vmcb_page:
1403         __free_page(vmcb01_page);
1404 out:
1405         return err;
1406 }
1407
1408 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1409 {
1410         int i;
1411
1412         for_each_online_cpu(i)
1413                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1414 }
1415
1416 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1417 {
1418         struct vcpu_svm *svm = to_svm(vcpu);
1419
1420         /*
1421          * The vmcb page can be recycled, causing a false negative in
1422          * svm_vcpu_load(). So, ensure that no logical CPU has this
1423          * vmcb page recorded as its current vmcb.
1424          */
1425         svm_clear_current_vmcb(svm->vmcb);
1426
1427         svm_free_nested(svm);
1428
1429         sev_free_vcpu(vcpu);
1430
1431         __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1432         __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1433 }
1434
1435 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1436 {
1437         struct vcpu_svm *svm = to_svm(vcpu);
1438         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1439
1440         if (sev_es_guest(vcpu->kvm))
1441                 sev_es_unmap_ghcb(svm);
1442
1443         if (svm->guest_state_loaded)
1444                 return;
1445
1446         /*
1447          * Save additional host state that will be restored on VMEXIT (sev-es)
1448          * or subsequent vmload of host save area.
1449          */
1450         if (sev_es_guest(vcpu->kvm)) {
1451                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1452         } else {
1453                 vmsave(__sme_page_pa(sd->save_area));
1454         }
1455
1456         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1457                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1458                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1459                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1460                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1461                 }
1462         }
1463
1464         if (likely(tsc_aux_uret_slot >= 0))
1465                 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1466
1467         svm->guest_state_loaded = true;
1468 }
1469
1470 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1471 {
1472         to_svm(vcpu)->guest_state_loaded = false;
1473 }
1474
1475 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1476 {
1477         struct vcpu_svm *svm = to_svm(vcpu);
1478         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1479
1480         if (sd->current_vmcb != svm->vmcb) {
1481                 sd->current_vmcb = svm->vmcb;
1482                 indirect_branch_prediction_barrier();
1483         }
1484         if (kvm_vcpu_apicv_active(vcpu))
1485                 avic_vcpu_load(vcpu, cpu);
1486 }
1487
1488 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1489 {
1490         if (kvm_vcpu_apicv_active(vcpu))
1491                 avic_vcpu_put(vcpu);
1492
1493         svm_prepare_host_switch(vcpu);
1494
1495         ++vcpu->stat.host_state_reload;
1496 }
1497
1498 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1499 {
1500         struct vcpu_svm *svm = to_svm(vcpu);
1501         unsigned long rflags = svm->vmcb->save.rflags;
1502
1503         if (svm->nmi_singlestep) {
1504                 /* Hide our flags if they were not set by the guest */
1505                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1506                         rflags &= ~X86_EFLAGS_TF;
1507                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1508                         rflags &= ~X86_EFLAGS_RF;
1509         }
1510         return rflags;
1511 }
1512
1513 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1514 {
1515         if (to_svm(vcpu)->nmi_singlestep)
1516                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1517
1518        /*
1519         * Any change of EFLAGS.VM is accompanied by a reload of SS
1520         * (caused by either a task switch or an inter-privilege IRET),
1521         * so we do not need to update the CPL here.
1522         */
1523         to_svm(vcpu)->vmcb->save.rflags = rflags;
1524 }
1525
1526 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1527 {
1528         switch (reg) {
1529         case VCPU_EXREG_PDPTR:
1530                 BUG_ON(!npt_enabled);
1531                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1532                 break;
1533         default:
1534                 KVM_BUG_ON(1, vcpu->kvm);
1535         }
1536 }
1537
1538 static void svm_set_vintr(struct vcpu_svm *svm)
1539 {
1540         struct vmcb_control_area *control;
1541
1542         /*
1543          * The following fields are ignored when AVIC is enabled
1544          */
1545         WARN_ON(kvm_apicv_activated(svm->vcpu.kvm));
1546
1547         svm_set_intercept(svm, INTERCEPT_VINTR);
1548
1549         /*
1550          * This is just a dummy VINTR to actually cause a vmexit to happen.
1551          * Actual injection of virtual interrupts happens through EVENTINJ.
1552          */
1553         control = &svm->vmcb->control;
1554         control->int_vector = 0x0;
1555         control->int_ctl &= ~V_INTR_PRIO_MASK;
1556         control->int_ctl |= V_IRQ_MASK |
1557                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1558         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1559 }
1560
1561 static void svm_clear_vintr(struct vcpu_svm *svm)
1562 {
1563         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1564         svm_clr_intercept(svm, INTERCEPT_VINTR);
1565
1566         /* Drop int_ctl fields related to VINTR injection.  */
1567         svm->vmcb->control.int_ctl &= mask;
1568         if (is_guest_mode(&svm->vcpu)) {
1569                 svm->vmcb01.ptr->control.int_ctl &= mask;
1570
1571                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1572                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1573                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1574         }
1575
1576         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1577 }
1578
1579 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1580 {
1581         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1582         struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1583
1584         switch (seg) {
1585         case VCPU_SREG_CS: return &save->cs;
1586         case VCPU_SREG_DS: return &save->ds;
1587         case VCPU_SREG_ES: return &save->es;
1588         case VCPU_SREG_FS: return &save01->fs;
1589         case VCPU_SREG_GS: return &save01->gs;
1590         case VCPU_SREG_SS: return &save->ss;
1591         case VCPU_SREG_TR: return &save01->tr;
1592         case VCPU_SREG_LDTR: return &save01->ldtr;
1593         }
1594         BUG();
1595         return NULL;
1596 }
1597
1598 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1599 {
1600         struct vmcb_seg *s = svm_seg(vcpu, seg);
1601
1602         return s->base;
1603 }
1604
1605 static void svm_get_segment(struct kvm_vcpu *vcpu,
1606                             struct kvm_segment *var, int seg)
1607 {
1608         struct vmcb_seg *s = svm_seg(vcpu, seg);
1609
1610         var->base = s->base;
1611         var->limit = s->limit;
1612         var->selector = s->selector;
1613         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1614         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1615         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1616         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1617         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1618         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1619         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1620
1621         /*
1622          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1623          * However, the SVM spec states that the G bit is not observed by the
1624          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1625          * So let's synthesize a legal G bit for all segments, this helps
1626          * running KVM nested. It also helps cross-vendor migration, because
1627          * Intel's vmentry has a check on the 'G' bit.
1628          */
1629         var->g = s->limit > 0xfffff;
1630
1631         /*
1632          * AMD's VMCB does not have an explicit unusable field, so emulate it
1633          * for cross vendor migration purposes by "not present"
1634          */
1635         var->unusable = !var->present;
1636
1637         switch (seg) {
1638         case VCPU_SREG_TR:
1639                 /*
1640                  * Work around a bug where the busy flag in the tr selector
1641                  * isn't exposed
1642                  */
1643                 var->type |= 0x2;
1644                 break;
1645         case VCPU_SREG_DS:
1646         case VCPU_SREG_ES:
1647         case VCPU_SREG_FS:
1648         case VCPU_SREG_GS:
1649                 /*
1650                  * The accessed bit must always be set in the segment
1651                  * descriptor cache, although it can be cleared in the
1652                  * descriptor, the cached bit always remains at 1. Since
1653                  * Intel has a check on this, set it here to support
1654                  * cross-vendor migration.
1655                  */
1656                 if (!var->unusable)
1657                         var->type |= 0x1;
1658                 break;
1659         case VCPU_SREG_SS:
1660                 /*
1661                  * On AMD CPUs sometimes the DB bit in the segment
1662                  * descriptor is left as 1, although the whole segment has
1663                  * been made unusable. Clear it here to pass an Intel VMX
1664                  * entry check when cross vendor migrating.
1665                  */
1666                 if (var->unusable)
1667                         var->db = 0;
1668                 /* This is symmetric with svm_set_segment() */
1669                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1670                 break;
1671         }
1672 }
1673
1674 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1675 {
1676         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1677
1678         return save->cpl;
1679 }
1680
1681 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1682 {
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684
1685         dt->size = svm->vmcb->save.idtr.limit;
1686         dt->address = svm->vmcb->save.idtr.base;
1687 }
1688
1689 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1690 {
1691         struct vcpu_svm *svm = to_svm(vcpu);
1692
1693         svm->vmcb->save.idtr.limit = dt->size;
1694         svm->vmcb->save.idtr.base = dt->address ;
1695         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1696 }
1697
1698 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1699 {
1700         struct vcpu_svm *svm = to_svm(vcpu);
1701
1702         dt->size = svm->vmcb->save.gdtr.limit;
1703         dt->address = svm->vmcb->save.gdtr.base;
1704 }
1705
1706 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1707 {
1708         struct vcpu_svm *svm = to_svm(vcpu);
1709
1710         svm->vmcb->save.gdtr.limit = dt->size;
1711         svm->vmcb->save.gdtr.base = dt->address ;
1712         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1713 }
1714
1715 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1716 {
1717         struct vcpu_svm *svm = to_svm(vcpu);
1718         u64 hcr0 = cr0;
1719
1720 #ifdef CONFIG_X86_64
1721         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1722                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1723                         vcpu->arch.efer |= EFER_LMA;
1724                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1725                 }
1726
1727                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1728                         vcpu->arch.efer &= ~EFER_LMA;
1729                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1730                 }
1731         }
1732 #endif
1733         vcpu->arch.cr0 = cr0;
1734
1735         if (!npt_enabled)
1736                 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1737
1738         /*
1739          * re-enable caching here because the QEMU bios
1740          * does not do it - this results in some delay at
1741          * reboot
1742          */
1743         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1744                 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1745
1746         svm->vmcb->save.cr0 = hcr0;
1747         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1748
1749         /*
1750          * SEV-ES guests must always keep the CR intercepts cleared. CR
1751          * tracking is done using the CR write traps.
1752          */
1753         if (sev_es_guest(vcpu->kvm))
1754                 return;
1755
1756         if (hcr0 == cr0) {
1757                 /* Selective CR0 write remains on.  */
1758                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1759                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1760         } else {
1761                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1762                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1763         }
1764 }
1765
1766 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1767 {
1768         return true;
1769 }
1770
1771 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1772 {
1773         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1774         unsigned long old_cr4 = vcpu->arch.cr4;
1775
1776         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1777                 svm_flush_tlb(vcpu);
1778
1779         vcpu->arch.cr4 = cr4;
1780         if (!npt_enabled)
1781                 cr4 |= X86_CR4_PAE;
1782         cr4 |= host_cr4_mce;
1783         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1784         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1785
1786         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1787                 kvm_update_cpuid_runtime(vcpu);
1788 }
1789
1790 static void svm_set_segment(struct kvm_vcpu *vcpu,
1791                             struct kvm_segment *var, int seg)
1792 {
1793         struct vcpu_svm *svm = to_svm(vcpu);
1794         struct vmcb_seg *s = svm_seg(vcpu, seg);
1795
1796         s->base = var->base;
1797         s->limit = var->limit;
1798         s->selector = var->selector;
1799         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1800         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1801         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1802         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1803         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1804         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1805         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1806         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1807
1808         /*
1809          * This is always accurate, except if SYSRET returned to a segment
1810          * with SS.DPL != 3.  Intel does not have this quirk, and always
1811          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1812          * would entail passing the CPL to userspace and back.
1813          */
1814         if (seg == VCPU_SREG_SS)
1815                 /* This is symmetric with svm_get_segment() */
1816                 svm->vmcb->save.cpl = (var->dpl & 3);
1817
1818         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1819 }
1820
1821 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1822 {
1823         struct vcpu_svm *svm = to_svm(vcpu);
1824
1825         clr_exception_intercept(svm, BP_VECTOR);
1826
1827         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1828                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1829                         set_exception_intercept(svm, BP_VECTOR);
1830         }
1831 }
1832
1833 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1834 {
1835         if (sd->next_asid > sd->max_asid) {
1836                 ++sd->asid_generation;
1837                 sd->next_asid = sd->min_asid;
1838                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1839                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1840         }
1841
1842         svm->current_vmcb->asid_generation = sd->asid_generation;
1843         svm->asid = sd->next_asid++;
1844 }
1845
1846 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1847 {
1848         struct vmcb *vmcb = svm->vmcb;
1849
1850         if (svm->vcpu.arch.guest_state_protected)
1851                 return;
1852
1853         if (unlikely(value != vmcb->save.dr6)) {
1854                 vmcb->save.dr6 = value;
1855                 vmcb_mark_dirty(vmcb, VMCB_DR);
1856         }
1857 }
1858
1859 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1860 {
1861         struct vcpu_svm *svm = to_svm(vcpu);
1862
1863         if (vcpu->arch.guest_state_protected)
1864                 return;
1865
1866         get_debugreg(vcpu->arch.db[0], 0);
1867         get_debugreg(vcpu->arch.db[1], 1);
1868         get_debugreg(vcpu->arch.db[2], 2);
1869         get_debugreg(vcpu->arch.db[3], 3);
1870         /*
1871          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1872          * because db_interception might need it.  We can do it before vmentry.
1873          */
1874         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1875         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1876         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1877         set_dr_intercepts(svm);
1878 }
1879
1880 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1881 {
1882         struct vcpu_svm *svm = to_svm(vcpu);
1883
1884         if (vcpu->arch.guest_state_protected)
1885                 return;
1886
1887         svm->vmcb->save.dr7 = value;
1888         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1889 }
1890
1891 static int pf_interception(struct kvm_vcpu *vcpu)
1892 {
1893         struct vcpu_svm *svm = to_svm(vcpu);
1894
1895         u64 fault_address = svm->vmcb->control.exit_info_2;
1896         u64 error_code = svm->vmcb->control.exit_info_1;
1897
1898         return kvm_handle_page_fault(vcpu, error_code, fault_address,
1899                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1900                         svm->vmcb->control.insn_bytes : NULL,
1901                         svm->vmcb->control.insn_len);
1902 }
1903
1904 static int npf_interception(struct kvm_vcpu *vcpu)
1905 {
1906         struct vcpu_svm *svm = to_svm(vcpu);
1907
1908         u64 fault_address = svm->vmcb->control.exit_info_2;
1909         u64 error_code = svm->vmcb->control.exit_info_1;
1910
1911         trace_kvm_page_fault(fault_address, error_code);
1912         return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1913                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1914                         svm->vmcb->control.insn_bytes : NULL,
1915                         svm->vmcb->control.insn_len);
1916 }
1917
1918 static int db_interception(struct kvm_vcpu *vcpu)
1919 {
1920         struct kvm_run *kvm_run = vcpu->run;
1921         struct vcpu_svm *svm = to_svm(vcpu);
1922
1923         if (!(vcpu->guest_debug &
1924               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1925                 !svm->nmi_singlestep) {
1926                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1927                 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1928                 return 1;
1929         }
1930
1931         if (svm->nmi_singlestep) {
1932                 disable_nmi_singlestep(svm);
1933                 /* Make sure we check for pending NMIs upon entry */
1934                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1935         }
1936
1937         if (vcpu->guest_debug &
1938             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1939                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1940                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1941                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1942                 kvm_run->debug.arch.pc =
1943                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1944                 kvm_run->debug.arch.exception = DB_VECTOR;
1945                 return 0;
1946         }
1947
1948         return 1;
1949 }
1950
1951 static int bp_interception(struct kvm_vcpu *vcpu)
1952 {
1953         struct vcpu_svm *svm = to_svm(vcpu);
1954         struct kvm_run *kvm_run = vcpu->run;
1955
1956         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1957         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1958         kvm_run->debug.arch.exception = BP_VECTOR;
1959         return 0;
1960 }
1961
1962 static int ud_interception(struct kvm_vcpu *vcpu)
1963 {
1964         return handle_ud(vcpu);
1965 }
1966
1967 static int ac_interception(struct kvm_vcpu *vcpu)
1968 {
1969         kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1970         return 1;
1971 }
1972
1973 static bool is_erratum_383(void)
1974 {
1975         int err, i;
1976         u64 value;
1977
1978         if (!erratum_383_found)
1979                 return false;
1980
1981         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1982         if (err)
1983                 return false;
1984
1985         /* Bit 62 may or may not be set for this mce */
1986         value &= ~(1ULL << 62);
1987
1988         if (value != 0xb600000000010015ULL)
1989                 return false;
1990
1991         /* Clear MCi_STATUS registers */
1992         for (i = 0; i < 6; ++i)
1993                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1994
1995         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1996         if (!err) {
1997                 u32 low, high;
1998
1999                 value &= ~(1ULL << 2);
2000                 low    = lower_32_bits(value);
2001                 high   = upper_32_bits(value);
2002
2003                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2004         }
2005
2006         /* Flush tlb to evict multi-match entries */
2007         __flush_tlb_all();
2008
2009         return true;
2010 }
2011
2012 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2013 {
2014         if (is_erratum_383()) {
2015                 /*
2016                  * Erratum 383 triggered. Guest state is corrupt so kill the
2017                  * guest.
2018                  */
2019                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2020
2021                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2022
2023                 return;
2024         }
2025
2026         /*
2027          * On an #MC intercept the MCE handler is not called automatically in
2028          * the host. So do it by hand here.
2029          */
2030         kvm_machine_check();
2031 }
2032
2033 static int mc_interception(struct kvm_vcpu *vcpu)
2034 {
2035         return 1;
2036 }
2037
2038 static int shutdown_interception(struct kvm_vcpu *vcpu)
2039 {
2040         struct kvm_run *kvm_run = vcpu->run;
2041         struct vcpu_svm *svm = to_svm(vcpu);
2042
2043         /*
2044          * The VM save area has already been encrypted so it
2045          * cannot be reinitialized - just terminate.
2046          */
2047         if (sev_es_guest(vcpu->kvm))
2048                 return -EINVAL;
2049
2050         /*
2051          * VMCB is undefined after a SHUTDOWN intercept.  INIT the vCPU to put
2052          * the VMCB in a known good state.  Unfortuately, KVM doesn't have
2053          * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2054          * userspace.  At a platform view, INIT is acceptable behavior as
2055          * there exist bare metal platforms that automatically INIT the CPU
2056          * in response to shutdown.
2057          */
2058         clear_page(svm->vmcb);
2059         kvm_vcpu_reset(vcpu, true);
2060
2061         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2062         return 0;
2063 }
2064
2065 static int io_interception(struct kvm_vcpu *vcpu)
2066 {
2067         struct vcpu_svm *svm = to_svm(vcpu);
2068         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2069         int size, in, string;
2070         unsigned port;
2071
2072         ++vcpu->stat.io_exits;
2073         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2074         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2075         port = io_info >> 16;
2076         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2077
2078         if (string) {
2079                 if (sev_es_guest(vcpu->kvm))
2080                         return sev_es_string_io(svm, size, port, in);
2081                 else
2082                         return kvm_emulate_instruction(vcpu, 0);
2083         }
2084
2085         svm->next_rip = svm->vmcb->control.exit_info_2;
2086
2087         return kvm_fast_pio(vcpu, size, port, in);
2088 }
2089
2090 static int nmi_interception(struct kvm_vcpu *vcpu)
2091 {
2092         return 1;
2093 }
2094
2095 static int smi_interception(struct kvm_vcpu *vcpu)
2096 {
2097         return 1;
2098 }
2099
2100 static int intr_interception(struct kvm_vcpu *vcpu)
2101 {
2102         ++vcpu->stat.irq_exits;
2103         return 1;
2104 }
2105
2106 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2107 {
2108         struct vcpu_svm *svm = to_svm(vcpu);
2109         struct vmcb *vmcb12;
2110         struct kvm_host_map map;
2111         int ret;
2112
2113         if (nested_svm_check_permissions(vcpu))
2114                 return 1;
2115
2116         ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2117         if (ret) {
2118                 if (ret == -EINVAL)
2119                         kvm_inject_gp(vcpu, 0);
2120                 return 1;
2121         }
2122
2123         vmcb12 = map.hva;
2124
2125         ret = kvm_skip_emulated_instruction(vcpu);
2126
2127         if (vmload) {
2128                 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2129                 svm->sysenter_eip_hi = 0;
2130                 svm->sysenter_esp_hi = 0;
2131         } else {
2132                 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2133         }
2134
2135         kvm_vcpu_unmap(vcpu, &map, true);
2136
2137         return ret;
2138 }
2139
2140 static int vmload_interception(struct kvm_vcpu *vcpu)
2141 {
2142         return vmload_vmsave_interception(vcpu, true);
2143 }
2144
2145 static int vmsave_interception(struct kvm_vcpu *vcpu)
2146 {
2147         return vmload_vmsave_interception(vcpu, false);
2148 }
2149
2150 static int vmrun_interception(struct kvm_vcpu *vcpu)
2151 {
2152         if (nested_svm_check_permissions(vcpu))
2153                 return 1;
2154
2155         return nested_svm_vmrun(vcpu);
2156 }
2157
2158 enum {
2159         NONE_SVM_INSTR,
2160         SVM_INSTR_VMRUN,
2161         SVM_INSTR_VMLOAD,
2162         SVM_INSTR_VMSAVE,
2163 };
2164
2165 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2166 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2167 {
2168         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2169
2170         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2171                 return NONE_SVM_INSTR;
2172
2173         switch (ctxt->modrm) {
2174         case 0xd8: /* VMRUN */
2175                 return SVM_INSTR_VMRUN;
2176         case 0xda: /* VMLOAD */
2177                 return SVM_INSTR_VMLOAD;
2178         case 0xdb: /* VMSAVE */
2179                 return SVM_INSTR_VMSAVE;
2180         default:
2181                 break;
2182         }
2183
2184         return NONE_SVM_INSTR;
2185 }
2186
2187 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2188 {
2189         const int guest_mode_exit_codes[] = {
2190                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2191                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2192                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2193         };
2194         int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2195                 [SVM_INSTR_VMRUN] = vmrun_interception,
2196                 [SVM_INSTR_VMLOAD] = vmload_interception,
2197                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2198         };
2199         struct vcpu_svm *svm = to_svm(vcpu);
2200         int ret;
2201
2202         if (is_guest_mode(vcpu)) {
2203                 /* Returns '1' or -errno on failure, '0' on success. */
2204                 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2205                 if (ret)
2206                         return ret;
2207                 return 1;
2208         }
2209         return svm_instr_handlers[opcode](vcpu);
2210 }
2211
2212 /*
2213  * #GP handling code. Note that #GP can be triggered under the following two
2214  * cases:
2215  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2216  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2217  *      regions (e.g. SMM memory on host).
2218  *   2) VMware backdoor
2219  */
2220 static int gp_interception(struct kvm_vcpu *vcpu)
2221 {
2222         struct vcpu_svm *svm = to_svm(vcpu);
2223         u32 error_code = svm->vmcb->control.exit_info_1;
2224         int opcode;
2225
2226         /* Both #GP cases have zero error_code */
2227         if (error_code)
2228                 goto reinject;
2229
2230         /* Decode the instruction for usage later */
2231         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2232                 goto reinject;
2233
2234         opcode = svm_instr_opcode(vcpu);
2235
2236         if (opcode == NONE_SVM_INSTR) {
2237                 if (!enable_vmware_backdoor)
2238                         goto reinject;
2239
2240                 /*
2241                  * VMware backdoor emulation on #GP interception only handles
2242                  * IN{S}, OUT{S}, and RDPMC.
2243                  */
2244                 if (!is_guest_mode(vcpu))
2245                         return kvm_emulate_instruction(vcpu,
2246                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2247         } else
2248                 return emulate_svm_instr(vcpu, opcode);
2249
2250 reinject:
2251         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2252         return 1;
2253 }
2254
2255 void svm_set_gif(struct vcpu_svm *svm, bool value)
2256 {
2257         if (value) {
2258                 /*
2259                  * If VGIF is enabled, the STGI intercept is only added to
2260                  * detect the opening of the SMI/NMI window; remove it now.
2261                  * Likewise, clear the VINTR intercept, we will set it
2262                  * again while processing KVM_REQ_EVENT if needed.
2263                  */
2264                 if (vgif_enabled(svm))
2265                         svm_clr_intercept(svm, INTERCEPT_STGI);
2266                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2267                         svm_clear_vintr(svm);
2268
2269                 enable_gif(svm);
2270                 if (svm->vcpu.arch.smi_pending ||
2271                     svm->vcpu.arch.nmi_pending ||
2272                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2273                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2274         } else {
2275                 disable_gif(svm);
2276
2277                 /*
2278                  * After a CLGI no interrupts should come.  But if vGIF is
2279                  * in use, we still rely on the VINTR intercept (rather than
2280                  * STGI) to detect an open interrupt window.
2281                 */
2282                 if (!vgif_enabled(svm))
2283                         svm_clear_vintr(svm);
2284         }
2285 }
2286
2287 static int stgi_interception(struct kvm_vcpu *vcpu)
2288 {
2289         int ret;
2290
2291         if (nested_svm_check_permissions(vcpu))
2292                 return 1;
2293
2294         ret = kvm_skip_emulated_instruction(vcpu);
2295         svm_set_gif(to_svm(vcpu), true);
2296         return ret;
2297 }
2298
2299 static int clgi_interception(struct kvm_vcpu *vcpu)
2300 {
2301         int ret;
2302
2303         if (nested_svm_check_permissions(vcpu))
2304                 return 1;
2305
2306         ret = kvm_skip_emulated_instruction(vcpu);
2307         svm_set_gif(to_svm(vcpu), false);
2308         return ret;
2309 }
2310
2311 static int invlpga_interception(struct kvm_vcpu *vcpu)
2312 {
2313         gva_t gva = kvm_rax_read(vcpu);
2314         u32 asid = kvm_rcx_read(vcpu);
2315
2316         /* FIXME: Handle an address size prefix. */
2317         if (!is_long_mode(vcpu))
2318                 gva = (u32)gva;
2319
2320         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2321
2322         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2323         kvm_mmu_invlpg(vcpu, gva);
2324
2325         return kvm_skip_emulated_instruction(vcpu);
2326 }
2327
2328 static int skinit_interception(struct kvm_vcpu *vcpu)
2329 {
2330         trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2331
2332         kvm_queue_exception(vcpu, UD_VECTOR);
2333         return 1;
2334 }
2335
2336 static int task_switch_interception(struct kvm_vcpu *vcpu)
2337 {
2338         struct vcpu_svm *svm = to_svm(vcpu);
2339         u16 tss_selector;
2340         int reason;
2341         int int_type = svm->vmcb->control.exit_int_info &
2342                 SVM_EXITINTINFO_TYPE_MASK;
2343         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2344         uint32_t type =
2345                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2346         uint32_t idt_v =
2347                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2348         bool has_error_code = false;
2349         u32 error_code = 0;
2350
2351         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2352
2353         if (svm->vmcb->control.exit_info_2 &
2354             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2355                 reason = TASK_SWITCH_IRET;
2356         else if (svm->vmcb->control.exit_info_2 &
2357                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2358                 reason = TASK_SWITCH_JMP;
2359         else if (idt_v)
2360                 reason = TASK_SWITCH_GATE;
2361         else
2362                 reason = TASK_SWITCH_CALL;
2363
2364         if (reason == TASK_SWITCH_GATE) {
2365                 switch (type) {
2366                 case SVM_EXITINTINFO_TYPE_NMI:
2367                         vcpu->arch.nmi_injected = false;
2368                         break;
2369                 case SVM_EXITINTINFO_TYPE_EXEPT:
2370                         if (svm->vmcb->control.exit_info_2 &
2371                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2372                                 has_error_code = true;
2373                                 error_code =
2374                                         (u32)svm->vmcb->control.exit_info_2;
2375                         }
2376                         kvm_clear_exception_queue(vcpu);
2377                         break;
2378                 case SVM_EXITINTINFO_TYPE_INTR:
2379                         kvm_clear_interrupt_queue(vcpu);
2380                         break;
2381                 default:
2382                         break;
2383                 }
2384         }
2385
2386         if (reason != TASK_SWITCH_GATE ||
2387             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2388             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2389              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2390                 if (!skip_emulated_instruction(vcpu))
2391                         return 0;
2392         }
2393
2394         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2395                 int_vec = -1;
2396
2397         return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2398                                has_error_code, error_code);
2399 }
2400
2401 static int iret_interception(struct kvm_vcpu *vcpu)
2402 {
2403         struct vcpu_svm *svm = to_svm(vcpu);
2404
2405         ++vcpu->stat.nmi_window_exits;
2406         vcpu->arch.hflags |= HF_IRET_MASK;
2407         if (!sev_es_guest(vcpu->kvm)) {
2408                 svm_clr_intercept(svm, INTERCEPT_IRET);
2409                 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2410         }
2411         kvm_make_request(KVM_REQ_EVENT, vcpu);
2412         return 1;
2413 }
2414
2415 static int invlpg_interception(struct kvm_vcpu *vcpu)
2416 {
2417         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2418                 return kvm_emulate_instruction(vcpu, 0);
2419
2420         kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2421         return kvm_skip_emulated_instruction(vcpu);
2422 }
2423
2424 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2425 {
2426         return kvm_emulate_instruction(vcpu, 0);
2427 }
2428
2429 static int rsm_interception(struct kvm_vcpu *vcpu)
2430 {
2431         return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2432 }
2433
2434 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2435                                             unsigned long val)
2436 {
2437         struct vcpu_svm *svm = to_svm(vcpu);
2438         unsigned long cr0 = vcpu->arch.cr0;
2439         bool ret = false;
2440
2441         if (!is_guest_mode(vcpu) ||
2442             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2443                 return false;
2444
2445         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2446         val &= ~SVM_CR0_SELECTIVE_MASK;
2447
2448         if (cr0 ^ val) {
2449                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2450                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2451         }
2452
2453         return ret;
2454 }
2455
2456 #define CR_VALID (1ULL << 63)
2457
2458 static int cr_interception(struct kvm_vcpu *vcpu)
2459 {
2460         struct vcpu_svm *svm = to_svm(vcpu);
2461         int reg, cr;
2462         unsigned long val;
2463         int err;
2464
2465         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2466                 return emulate_on_interception(vcpu);
2467
2468         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2469                 return emulate_on_interception(vcpu);
2470
2471         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2472         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2473                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2474         else
2475                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2476
2477         err = 0;
2478         if (cr >= 16) { /* mov to cr */
2479                 cr -= 16;
2480                 val = kvm_register_read(vcpu, reg);
2481                 trace_kvm_cr_write(cr, val);
2482                 switch (cr) {
2483                 case 0:
2484                         if (!check_selective_cr0_intercepted(vcpu, val))
2485                                 err = kvm_set_cr0(vcpu, val);
2486                         else
2487                                 return 1;
2488
2489                         break;
2490                 case 3:
2491                         err = kvm_set_cr3(vcpu, val);
2492                         break;
2493                 case 4:
2494                         err = kvm_set_cr4(vcpu, val);
2495                         break;
2496                 case 8:
2497                         err = kvm_set_cr8(vcpu, val);
2498                         break;
2499                 default:
2500                         WARN(1, "unhandled write to CR%d", cr);
2501                         kvm_queue_exception(vcpu, UD_VECTOR);
2502                         return 1;
2503                 }
2504         } else { /* mov from cr */
2505                 switch (cr) {
2506                 case 0:
2507                         val = kvm_read_cr0(vcpu);
2508                         break;
2509                 case 2:
2510                         val = vcpu->arch.cr2;
2511                         break;
2512                 case 3:
2513                         val = kvm_read_cr3(vcpu);
2514                         break;
2515                 case 4:
2516                         val = kvm_read_cr4(vcpu);
2517                         break;
2518                 case 8:
2519                         val = kvm_get_cr8(vcpu);
2520                         break;
2521                 default:
2522                         WARN(1, "unhandled read from CR%d", cr);
2523                         kvm_queue_exception(vcpu, UD_VECTOR);
2524                         return 1;
2525                 }
2526                 kvm_register_write(vcpu, reg, val);
2527                 trace_kvm_cr_read(cr, val);
2528         }
2529         return kvm_complete_insn_gp(vcpu, err);
2530 }
2531
2532 static int cr_trap(struct kvm_vcpu *vcpu)
2533 {
2534         struct vcpu_svm *svm = to_svm(vcpu);
2535         unsigned long old_value, new_value;
2536         unsigned int cr;
2537         int ret = 0;
2538
2539         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2540
2541         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2542         switch (cr) {
2543         case 0:
2544                 old_value = kvm_read_cr0(vcpu);
2545                 svm_set_cr0(vcpu, new_value);
2546
2547                 kvm_post_set_cr0(vcpu, old_value, new_value);
2548                 break;
2549         case 4:
2550                 old_value = kvm_read_cr4(vcpu);
2551                 svm_set_cr4(vcpu, new_value);
2552
2553                 kvm_post_set_cr4(vcpu, old_value, new_value);
2554                 break;
2555         case 8:
2556                 ret = kvm_set_cr8(vcpu, new_value);
2557                 break;
2558         default:
2559                 WARN(1, "unhandled CR%d write trap", cr);
2560                 kvm_queue_exception(vcpu, UD_VECTOR);
2561                 return 1;
2562         }
2563
2564         return kvm_complete_insn_gp(vcpu, ret);
2565 }
2566
2567 static int dr_interception(struct kvm_vcpu *vcpu)
2568 {
2569         struct vcpu_svm *svm = to_svm(vcpu);
2570         int reg, dr;
2571         unsigned long val;
2572         int err = 0;
2573
2574         if (vcpu->guest_debug == 0) {
2575                 /*
2576                  * No more DR vmexits; force a reload of the debug registers
2577                  * and reenter on this instruction.  The next vmexit will
2578                  * retrieve the full state of the debug registers.
2579                  */
2580                 clr_dr_intercepts(svm);
2581                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2582                 return 1;
2583         }
2584
2585         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2586                 return emulate_on_interception(vcpu);
2587
2588         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2589         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2590         if (dr >= 16) { /* mov to DRn  */
2591                 dr -= 16;
2592                 val = kvm_register_read(vcpu, reg);
2593                 err = kvm_set_dr(vcpu, dr, val);
2594         } else {
2595                 kvm_get_dr(vcpu, dr, &val);
2596                 kvm_register_write(vcpu, reg, val);
2597         }
2598
2599         return kvm_complete_insn_gp(vcpu, err);
2600 }
2601
2602 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2603 {
2604         int r;
2605
2606         u8 cr8_prev = kvm_get_cr8(vcpu);
2607         /* instruction emulation calls kvm_set_cr8() */
2608         r = cr_interception(vcpu);
2609         if (lapic_in_kernel(vcpu))
2610                 return r;
2611         if (cr8_prev <= kvm_get_cr8(vcpu))
2612                 return r;
2613         vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2614         return 0;
2615 }
2616
2617 static int efer_trap(struct kvm_vcpu *vcpu)
2618 {
2619         struct msr_data msr_info;
2620         int ret;
2621
2622         /*
2623          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2624          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2625          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2626          * the guest doesn't have X86_FEATURE_SVM.
2627          */
2628         msr_info.host_initiated = false;
2629         msr_info.index = MSR_EFER;
2630         msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2631         ret = kvm_set_msr_common(vcpu, &msr_info);
2632
2633         return kvm_complete_insn_gp(vcpu, ret);
2634 }
2635
2636 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2637 {
2638         msr->data = 0;
2639
2640         switch (msr->index) {
2641         case MSR_F10H_DECFG:
2642                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2643                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2644                 break;
2645         case MSR_IA32_PERF_CAPABILITIES:
2646                 return 0;
2647         default:
2648                 return KVM_MSR_RET_INVALID;
2649         }
2650
2651         return 0;
2652 }
2653
2654 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2655 {
2656         struct vcpu_svm *svm = to_svm(vcpu);
2657
2658         switch (msr_info->index) {
2659         case MSR_STAR:
2660                 msr_info->data = svm->vmcb01.ptr->save.star;
2661                 break;
2662 #ifdef CONFIG_X86_64
2663         case MSR_LSTAR:
2664                 msr_info->data = svm->vmcb01.ptr->save.lstar;
2665                 break;
2666         case MSR_CSTAR:
2667                 msr_info->data = svm->vmcb01.ptr->save.cstar;
2668                 break;
2669         case MSR_KERNEL_GS_BASE:
2670                 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2671                 break;
2672         case MSR_SYSCALL_MASK:
2673                 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2674                 break;
2675 #endif
2676         case MSR_IA32_SYSENTER_CS:
2677                 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2678                 break;
2679         case MSR_IA32_SYSENTER_EIP:
2680                 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2681                 if (guest_cpuid_is_intel(vcpu))
2682                         msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2683                 break;
2684         case MSR_IA32_SYSENTER_ESP:
2685                 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2686                 if (guest_cpuid_is_intel(vcpu))
2687                         msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2688                 break;
2689         case MSR_TSC_AUX:
2690                 msr_info->data = svm->tsc_aux;
2691                 break;
2692         /*
2693          * Nobody will change the following 5 values in the VMCB so we can
2694          * safely return them on rdmsr. They will always be 0 until LBRV is
2695          * implemented.
2696          */
2697         case MSR_IA32_DEBUGCTLMSR:
2698                 msr_info->data = svm->vmcb->save.dbgctl;
2699                 break;
2700         case MSR_IA32_LASTBRANCHFROMIP:
2701                 msr_info->data = svm->vmcb->save.br_from;
2702                 break;
2703         case MSR_IA32_LASTBRANCHTOIP:
2704                 msr_info->data = svm->vmcb->save.br_to;
2705                 break;
2706         case MSR_IA32_LASTINTFROMIP:
2707                 msr_info->data = svm->vmcb->save.last_excp_from;
2708                 break;
2709         case MSR_IA32_LASTINTTOIP:
2710                 msr_info->data = svm->vmcb->save.last_excp_to;
2711                 break;
2712         case MSR_VM_HSAVE_PA:
2713                 msr_info->data = svm->nested.hsave_msr;
2714                 break;
2715         case MSR_VM_CR:
2716                 msr_info->data = svm->nested.vm_cr_msr;
2717                 break;
2718         case MSR_IA32_SPEC_CTRL:
2719                 if (!msr_info->host_initiated &&
2720                     !guest_has_spec_ctrl_msr(vcpu))
2721                         return 1;
2722
2723                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2724                         msr_info->data = svm->vmcb->save.spec_ctrl;
2725                 else
2726                         msr_info->data = svm->spec_ctrl;
2727                 break;
2728         case MSR_AMD64_VIRT_SPEC_CTRL:
2729                 if (!msr_info->host_initiated &&
2730                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2731                         return 1;
2732
2733                 msr_info->data = svm->virt_spec_ctrl;
2734                 break;
2735         case MSR_F15H_IC_CFG: {
2736
2737                 int family, model;
2738
2739                 family = guest_cpuid_family(vcpu);
2740                 model  = guest_cpuid_model(vcpu);
2741
2742                 if (family < 0 || model < 0)
2743                         return kvm_get_msr_common(vcpu, msr_info);
2744
2745                 msr_info->data = 0;
2746
2747                 if (family == 0x15 &&
2748                     (model >= 0x2 && model < 0x20))
2749                         msr_info->data = 0x1E;
2750                 }
2751                 break;
2752         case MSR_F10H_DECFG:
2753                 msr_info->data = svm->msr_decfg;
2754                 break;
2755         default:
2756                 return kvm_get_msr_common(vcpu, msr_info);
2757         }
2758         return 0;
2759 }
2760
2761 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2762 {
2763         struct vcpu_svm *svm = to_svm(vcpu);
2764         if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2765                 return kvm_complete_insn_gp(vcpu, err);
2766
2767         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2768         ghcb_set_sw_exit_info_2(svm->ghcb,
2769                                 X86_TRAP_GP |
2770                                 SVM_EVTINJ_TYPE_EXEPT |
2771                                 SVM_EVTINJ_VALID);
2772         return 1;
2773 }
2774
2775 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2776 {
2777         struct vcpu_svm *svm = to_svm(vcpu);
2778         int svm_dis, chg_mask;
2779
2780         if (data & ~SVM_VM_CR_VALID_MASK)
2781                 return 1;
2782
2783         chg_mask = SVM_VM_CR_VALID_MASK;
2784
2785         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2786                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2787
2788         svm->nested.vm_cr_msr &= ~chg_mask;
2789         svm->nested.vm_cr_msr |= (data & chg_mask);
2790
2791         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2792
2793         /* check for svm_disable while efer.svme is set */
2794         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2795                 return 1;
2796
2797         return 0;
2798 }
2799
2800 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2801 {
2802         struct vcpu_svm *svm = to_svm(vcpu);
2803         int r;
2804
2805         u32 ecx = msr->index;
2806         u64 data = msr->data;
2807         switch (ecx) {
2808         case MSR_IA32_CR_PAT:
2809                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2810                         return 1;
2811                 vcpu->arch.pat = data;
2812                 svm->vmcb01.ptr->save.g_pat = data;
2813                 if (is_guest_mode(vcpu))
2814                         nested_vmcb02_compute_g_pat(svm);
2815                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2816                 break;
2817         case MSR_IA32_SPEC_CTRL:
2818                 if (!msr->host_initiated &&
2819                     !guest_has_spec_ctrl_msr(vcpu))
2820                         return 1;
2821
2822                 if (kvm_spec_ctrl_test_value(data))
2823                         return 1;
2824
2825                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2826                         svm->vmcb->save.spec_ctrl = data;
2827                 else
2828                         svm->spec_ctrl = data;
2829                 if (!data)
2830                         break;
2831
2832                 /*
2833                  * For non-nested:
2834                  * When it's written (to non-zero) for the first time, pass
2835                  * it through.
2836                  *
2837                  * For nested:
2838                  * The handling of the MSR bitmap for L2 guests is done in
2839                  * nested_svm_vmrun_msrpm.
2840                  * We update the L1 MSR bit as well since it will end up
2841                  * touching the MSR anyway now.
2842                  */
2843                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2844                 break;
2845         case MSR_IA32_PRED_CMD:
2846                 if (!msr->host_initiated &&
2847                     !guest_has_pred_cmd_msr(vcpu))
2848                         return 1;
2849
2850                 if (data & ~PRED_CMD_IBPB)
2851                         return 1;
2852                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2853                         return 1;
2854                 if (!data)
2855                         break;
2856
2857                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2858                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2859                 break;
2860         case MSR_AMD64_VIRT_SPEC_CTRL:
2861                 if (!msr->host_initiated &&
2862                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2863                         return 1;
2864
2865                 if (data & ~SPEC_CTRL_SSBD)
2866                         return 1;
2867
2868                 svm->virt_spec_ctrl = data;
2869                 break;
2870         case MSR_STAR:
2871                 svm->vmcb01.ptr->save.star = data;
2872                 break;
2873 #ifdef CONFIG_X86_64
2874         case MSR_LSTAR:
2875                 svm->vmcb01.ptr->save.lstar = data;
2876                 break;
2877         case MSR_CSTAR:
2878                 svm->vmcb01.ptr->save.cstar = data;
2879                 break;
2880         case MSR_KERNEL_GS_BASE:
2881                 svm->vmcb01.ptr->save.kernel_gs_base = data;
2882                 break;
2883         case MSR_SYSCALL_MASK:
2884                 svm->vmcb01.ptr->save.sfmask = data;
2885                 break;
2886 #endif
2887         case MSR_IA32_SYSENTER_CS:
2888                 svm->vmcb01.ptr->save.sysenter_cs = data;
2889                 break;
2890         case MSR_IA32_SYSENTER_EIP:
2891                 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2892                 /*
2893                  * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2894                  * when we spoof an Intel vendor ID (for cross vendor migration).
2895                  * In this case we use this intercept to track the high
2896                  * 32 bit part of these msrs to support Intel's
2897                  * implementation of SYSENTER/SYSEXIT.
2898                  */
2899                 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2900                 break;
2901         case MSR_IA32_SYSENTER_ESP:
2902                 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2903                 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2904                 break;
2905         case MSR_TSC_AUX:
2906                 /*
2907                  * TSC_AUX is usually changed only during boot and never read
2908                  * directly.  Intercept TSC_AUX instead of exposing it to the
2909                  * guest via direct_access_msrs, and switch it via user return.
2910                  */
2911                 preempt_disable();
2912                 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2913                 preempt_enable();
2914                 if (r)
2915                         return 1;
2916
2917                 svm->tsc_aux = data;
2918                 break;
2919         case MSR_IA32_DEBUGCTLMSR:
2920                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2921                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2922                                     __func__, data);
2923                         break;
2924                 }
2925                 if (data & DEBUGCTL_RESERVED_BITS)
2926                         return 1;
2927
2928                 svm->vmcb->save.dbgctl = data;
2929                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2930                 if (data & (1ULL<<0))
2931                         svm_enable_lbrv(vcpu);
2932                 else
2933                         svm_disable_lbrv(vcpu);
2934                 break;
2935         case MSR_VM_HSAVE_PA:
2936                 /*
2937                  * Old kernels did not validate the value written to
2938                  * MSR_VM_HSAVE_PA.  Allow KVM_SET_MSR to set an invalid
2939                  * value to allow live migrating buggy or malicious guests
2940                  * originating from those kernels.
2941                  */
2942                 if (!msr->host_initiated && !page_address_valid(vcpu, data))
2943                         return 1;
2944
2945                 svm->nested.hsave_msr = data & PAGE_MASK;
2946                 break;
2947         case MSR_VM_CR:
2948                 return svm_set_vm_cr(vcpu, data);
2949         case MSR_VM_IGNNE:
2950                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2951                 break;
2952         case MSR_F10H_DECFG: {
2953                 struct kvm_msr_entry msr_entry;
2954
2955                 msr_entry.index = msr->index;
2956                 if (svm_get_msr_feature(&msr_entry))
2957                         return 1;
2958
2959                 /* Check the supported bits */
2960                 if (data & ~msr_entry.data)
2961                         return 1;
2962
2963                 /* Don't allow the guest to change a bit, #GP */
2964                 if (!msr->host_initiated && (data ^ msr_entry.data))
2965                         return 1;
2966
2967                 svm->msr_decfg = data;
2968                 break;
2969         }
2970         case MSR_IA32_APICBASE:
2971                 if (kvm_vcpu_apicv_active(vcpu))
2972                         avic_update_vapic_bar(to_svm(vcpu), data);
2973                 fallthrough;
2974         default:
2975                 return kvm_set_msr_common(vcpu, msr);
2976         }
2977         return 0;
2978 }
2979
2980 static int msr_interception(struct kvm_vcpu *vcpu)
2981 {
2982         if (to_svm(vcpu)->vmcb->control.exit_info_1)
2983                 return kvm_emulate_wrmsr(vcpu);
2984         else
2985                 return kvm_emulate_rdmsr(vcpu);
2986 }
2987
2988 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2989 {
2990         kvm_make_request(KVM_REQ_EVENT, vcpu);
2991         svm_clear_vintr(to_svm(vcpu));
2992
2993         /*
2994          * For AVIC, the only reason to end up here is ExtINTs.
2995          * In this case AVIC was temporarily disabled for
2996          * requesting the IRQ window and we have to re-enable it.
2997          */
2998         kvm_request_apicv_update(vcpu->kvm, true, APICV_INHIBIT_REASON_IRQWIN);
2999
3000         ++vcpu->stat.irq_window_exits;
3001         return 1;
3002 }
3003
3004 static int pause_interception(struct kvm_vcpu *vcpu)
3005 {
3006         bool in_kernel;
3007
3008         /*
3009          * CPL is not made available for an SEV-ES guest, therefore
3010          * vcpu->arch.preempted_in_kernel can never be true.  Just
3011          * set in_kernel to false as well.
3012          */
3013         in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3014
3015         if (!kvm_pause_in_guest(vcpu->kvm))
3016                 grow_ple_window(vcpu);
3017
3018         kvm_vcpu_on_spin(vcpu, in_kernel);
3019         return kvm_skip_emulated_instruction(vcpu);
3020 }
3021
3022 static int invpcid_interception(struct kvm_vcpu *vcpu)
3023 {
3024         struct vcpu_svm *svm = to_svm(vcpu);
3025         unsigned long type;
3026         gva_t gva;
3027
3028         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3029                 kvm_queue_exception(vcpu, UD_VECTOR);
3030                 return 1;
3031         }
3032
3033         /*
3034          * For an INVPCID intercept:
3035          * EXITINFO1 provides the linear address of the memory operand.
3036          * EXITINFO2 provides the contents of the register operand.
3037          */
3038         type = svm->vmcb->control.exit_info_2;
3039         gva = svm->vmcb->control.exit_info_1;
3040
3041         if (type > 3) {
3042                 kvm_inject_gp(vcpu, 0);
3043                 return 1;
3044         }
3045
3046         return kvm_handle_invpcid(vcpu, type, gva);
3047 }
3048
3049 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3050         [SVM_EXIT_READ_CR0]                     = cr_interception,
3051         [SVM_EXIT_READ_CR3]                     = cr_interception,
3052         [SVM_EXIT_READ_CR4]                     = cr_interception,
3053         [SVM_EXIT_READ_CR8]                     = cr_interception,
3054         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3055         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3056         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3057         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3058         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3059         [SVM_EXIT_READ_DR0]                     = dr_interception,
3060         [SVM_EXIT_READ_DR1]                     = dr_interception,
3061         [SVM_EXIT_READ_DR2]                     = dr_interception,
3062         [SVM_EXIT_READ_DR3]                     = dr_interception,
3063         [SVM_EXIT_READ_DR4]                     = dr_interception,
3064         [SVM_EXIT_READ_DR5]                     = dr_interception,
3065         [SVM_EXIT_READ_DR6]                     = dr_interception,
3066         [SVM_EXIT_READ_DR7]                     = dr_interception,
3067         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3068         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3069         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3070         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3071         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3072         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3073         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3074         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3075         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3076         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3077         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3078         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3079         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3080         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3081         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3082         [SVM_EXIT_INTR]                         = intr_interception,
3083         [SVM_EXIT_NMI]                          = nmi_interception,
3084         [SVM_EXIT_SMI]                          = smi_interception,
3085         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3086         [SVM_EXIT_RDPMC]                        = kvm_emulate_rdpmc,
3087         [SVM_EXIT_CPUID]                        = kvm_emulate_cpuid,
3088         [SVM_EXIT_IRET]                         = iret_interception,
3089         [SVM_EXIT_INVD]                         = kvm_emulate_invd,
3090         [SVM_EXIT_PAUSE]                        = pause_interception,
3091         [SVM_EXIT_HLT]                          = kvm_emulate_halt,
3092         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3093         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3094         [SVM_EXIT_IOIO]                         = io_interception,
3095         [SVM_EXIT_MSR]                          = msr_interception,
3096         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3097         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3098         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3099         [SVM_EXIT_VMMCALL]                      = kvm_emulate_hypercall,
3100         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3101         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3102         [SVM_EXIT_STGI]                         = stgi_interception,
3103         [SVM_EXIT_CLGI]                         = clgi_interception,
3104         [SVM_EXIT_SKINIT]                       = skinit_interception,
3105         [SVM_EXIT_RDTSCP]                       = kvm_handle_invalid_op,
3106         [SVM_EXIT_WBINVD]                       = kvm_emulate_wbinvd,
3107         [SVM_EXIT_MONITOR]                      = kvm_emulate_monitor,
3108         [SVM_EXIT_MWAIT]                        = kvm_emulate_mwait,
3109         [SVM_EXIT_XSETBV]                       = kvm_emulate_xsetbv,
3110         [SVM_EXIT_RDPRU]                        = kvm_handle_invalid_op,
3111         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3112         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3113         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3114         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3115         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3116         [SVM_EXIT_NPF]                          = npf_interception,
3117         [SVM_EXIT_RSM]                          = rsm_interception,
3118         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3119         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3120         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3121 };
3122
3123 static void dump_vmcb(struct kvm_vcpu *vcpu)
3124 {
3125         struct vcpu_svm *svm = to_svm(vcpu);
3126         struct vmcb_control_area *control = &svm->vmcb->control;
3127         struct vmcb_save_area *save = &svm->vmcb->save;
3128         struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3129
3130         if (!dump_invalid_vmcb) {
3131                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3132                 return;
3133         }
3134
3135         pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3136                svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3137         pr_err("VMCB Control Area:\n");
3138         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3139         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3140         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3141         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3142         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3143         pr_err("%-20s%08x %08x\n", "intercepts:",
3144               control->intercepts[INTERCEPT_WORD3],
3145                control->intercepts[INTERCEPT_WORD4]);
3146         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3147         pr_err("%-20s%d\n", "pause filter threshold:",
3148                control->pause_filter_thresh);
3149         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3150         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3151         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3152         pr_err("%-20s%d\n", "asid:", control->asid);
3153         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3154         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3155         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3156         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3157         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3158         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3159         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3160         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3161         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3162         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3163         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3164         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3165         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3166         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3167         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3168         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3169         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3170         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3171         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3172         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3173         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3174         pr_err("VMCB State Save Area:\n");
3175         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3176                "es:",
3177                save->es.selector, save->es.attrib,
3178                save->es.limit, save->es.base);
3179         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3180                "cs:",
3181                save->cs.selector, save->cs.attrib,
3182                save->cs.limit, save->cs.base);
3183         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3184                "ss:",
3185                save->ss.selector, save->ss.attrib,
3186                save->ss.limit, save->ss.base);
3187         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3188                "ds:",
3189                save->ds.selector, save->ds.attrib,
3190                save->ds.limit, save->ds.base);
3191         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3192                "fs:",
3193                save01->fs.selector, save01->fs.attrib,
3194                save01->fs.limit, save01->fs.base);
3195         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3196                "gs:",
3197                save01->gs.selector, save01->gs.attrib,
3198                save01->gs.limit, save01->gs.base);
3199         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3200                "gdtr:",
3201                save->gdtr.selector, save->gdtr.attrib,
3202                save->gdtr.limit, save->gdtr.base);
3203         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3204                "ldtr:",
3205                save01->ldtr.selector, save01->ldtr.attrib,
3206                save01->ldtr.limit, save01->ldtr.base);
3207         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3208                "idtr:",
3209                save->idtr.selector, save->idtr.attrib,
3210                save->idtr.limit, save->idtr.base);
3211         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3212                "tr:",
3213                save01->tr.selector, save01->tr.attrib,
3214                save01->tr.limit, save01->tr.base);
3215         pr_err("cpl:            %d                efer:         %016llx\n",
3216                 save->cpl, save->efer);
3217         pr_err("%-15s %016llx %-13s %016llx\n",
3218                "cr0:", save->cr0, "cr2:", save->cr2);
3219         pr_err("%-15s %016llx %-13s %016llx\n",
3220                "cr3:", save->cr3, "cr4:", save->cr4);
3221         pr_err("%-15s %016llx %-13s %016llx\n",
3222                "dr6:", save->dr6, "dr7:", save->dr7);
3223         pr_err("%-15s %016llx %-13s %016llx\n",
3224                "rip:", save->rip, "rflags:", save->rflags);
3225         pr_err("%-15s %016llx %-13s %016llx\n",
3226                "rsp:", save->rsp, "rax:", save->rax);
3227         pr_err("%-15s %016llx %-13s %016llx\n",
3228                "star:", save01->star, "lstar:", save01->lstar);
3229         pr_err("%-15s %016llx %-13s %016llx\n",
3230                "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3231         pr_err("%-15s %016llx %-13s %016llx\n",
3232                "kernel_gs_base:", save01->kernel_gs_base,
3233                "sysenter_cs:", save01->sysenter_cs);
3234         pr_err("%-15s %016llx %-13s %016llx\n",
3235                "sysenter_esp:", save01->sysenter_esp,
3236                "sysenter_eip:", save01->sysenter_eip);
3237         pr_err("%-15s %016llx %-13s %016llx\n",
3238                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3239         pr_err("%-15s %016llx %-13s %016llx\n",
3240                "br_from:", save->br_from, "br_to:", save->br_to);
3241         pr_err("%-15s %016llx %-13s %016llx\n",
3242                "excp_from:", save->last_excp_from,
3243                "excp_to:", save->last_excp_to);
3244 }
3245
3246 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3247 {
3248         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3249             svm_exit_handlers[exit_code])
3250                 return 0;
3251
3252         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3253         dump_vmcb(vcpu);
3254         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3255         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3256         vcpu->run->internal.ndata = 2;
3257         vcpu->run->internal.data[0] = exit_code;
3258         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3259
3260         return -EINVAL;
3261 }
3262
3263 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3264 {
3265         if (svm_handle_invalid_exit(vcpu, exit_code))
3266                 return 0;
3267
3268 #ifdef CONFIG_RETPOLINE
3269         if (exit_code == SVM_EXIT_MSR)
3270                 return msr_interception(vcpu);
3271         else if (exit_code == SVM_EXIT_VINTR)
3272                 return interrupt_window_interception(vcpu);
3273         else if (exit_code == SVM_EXIT_INTR)
3274                 return intr_interception(vcpu);
3275         else if (exit_code == SVM_EXIT_HLT)
3276                 return kvm_emulate_halt(vcpu);
3277         else if (exit_code == SVM_EXIT_NPF)
3278                 return npf_interception(vcpu);
3279 #endif
3280         return svm_exit_handlers[exit_code](vcpu);
3281 }
3282
3283 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3284                               u32 *intr_info, u32 *error_code)
3285 {
3286         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3287
3288         *info1 = control->exit_info_1;
3289         *info2 = control->exit_info_2;
3290         *intr_info = control->exit_int_info;
3291         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3292             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3293                 *error_code = control->exit_int_info_err;
3294         else
3295                 *error_code = 0;
3296 }
3297
3298 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3299 {
3300         struct vcpu_svm *svm = to_svm(vcpu);
3301         struct kvm_run *kvm_run = vcpu->run;
3302         u32 exit_code = svm->vmcb->control.exit_code;
3303
3304         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3305
3306         /* SEV-ES guests must use the CR write traps to track CR registers. */
3307         if (!sev_es_guest(vcpu->kvm)) {
3308                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3309                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3310                 if (npt_enabled)
3311                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3312         }
3313
3314         if (is_guest_mode(vcpu)) {
3315                 int vmexit;
3316
3317                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3318
3319                 vmexit = nested_svm_exit_special(svm);
3320
3321                 if (vmexit == NESTED_EXIT_CONTINUE)
3322                         vmexit = nested_svm_exit_handled(svm);
3323
3324                 if (vmexit == NESTED_EXIT_DONE)
3325                         return 1;
3326         }
3327
3328         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3329                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3330                 kvm_run->fail_entry.hardware_entry_failure_reason
3331                         = svm->vmcb->control.exit_code;
3332                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3333                 dump_vmcb(vcpu);
3334                 return 0;
3335         }
3336
3337         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3338             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3339             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3340             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3341                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3342                        "exit_code 0x%x\n",
3343                        __func__, svm->vmcb->control.exit_int_info,
3344                        exit_code);
3345
3346         if (exit_fastpath != EXIT_FASTPATH_NONE)
3347                 return 1;
3348
3349         return svm_invoke_exit_handler(vcpu, exit_code);
3350 }
3351
3352 static void reload_tss(struct kvm_vcpu *vcpu)
3353 {
3354         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3355
3356         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3357         load_TR_desc();
3358 }
3359
3360 static void pre_svm_run(struct kvm_vcpu *vcpu)
3361 {
3362         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3363         struct vcpu_svm *svm = to_svm(vcpu);
3364
3365         /*
3366          * If the previous vmrun of the vmcb occurred on a different physical
3367          * cpu, then mark the vmcb dirty and assign a new asid.  Hardware's
3368          * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3369          */
3370         if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3371                 svm->current_vmcb->asid_generation = 0;
3372                 vmcb_mark_all_dirty(svm->vmcb);
3373                 svm->current_vmcb->cpu = vcpu->cpu;
3374         }
3375
3376         if (sev_guest(vcpu->kvm))
3377                 return pre_sev_run(svm, vcpu->cpu);
3378
3379         /* FIXME: handle wraparound of asid_generation */
3380         if (svm->current_vmcb->asid_generation != sd->asid_generation)
3381                 new_asid(svm, sd);
3382 }
3383
3384 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3385 {
3386         struct vcpu_svm *svm = to_svm(vcpu);
3387
3388         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3389         vcpu->arch.hflags |= HF_NMI_MASK;
3390         if (!sev_es_guest(vcpu->kvm))
3391                 svm_set_intercept(svm, INTERCEPT_IRET);
3392         ++vcpu->stat.nmi_injections;
3393 }
3394
3395 static void svm_set_irq(struct kvm_vcpu *vcpu)
3396 {
3397         struct vcpu_svm *svm = to_svm(vcpu);
3398
3399         BUG_ON(!(gif_set(svm)));
3400
3401         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3402         ++vcpu->stat.irq_injections;
3403
3404         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3405                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3406 }
3407
3408 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3409 {
3410         struct vcpu_svm *svm = to_svm(vcpu);
3411
3412         /*
3413          * SEV-ES guests must always keep the CR intercepts cleared. CR
3414          * tracking is done using the CR write traps.
3415          */
3416         if (sev_es_guest(vcpu->kvm))
3417                 return;
3418
3419         if (nested_svm_virtualize_tpr(vcpu))
3420                 return;
3421
3422         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3423
3424         if (irr == -1)
3425                 return;
3426
3427         if (tpr >= irr)
3428                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3429 }
3430
3431 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3432 {
3433         struct vcpu_svm *svm = to_svm(vcpu);
3434         struct vmcb *vmcb = svm->vmcb;
3435         bool ret;
3436
3437         if (!gif_set(svm))
3438                 return true;
3439
3440         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3441                 return false;
3442
3443         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3444               (vcpu->arch.hflags & HF_NMI_MASK);
3445
3446         return ret;
3447 }
3448
3449 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3450 {
3451         struct vcpu_svm *svm = to_svm(vcpu);
3452         if (svm->nested.nested_run_pending)
3453                 return -EBUSY;
3454
3455         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3456         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3457                 return -EBUSY;
3458
3459         return !svm_nmi_blocked(vcpu);
3460 }
3461
3462 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3463 {
3464         return !!(vcpu->arch.hflags & HF_NMI_MASK);
3465 }
3466
3467 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3468 {
3469         struct vcpu_svm *svm = to_svm(vcpu);
3470
3471         if (masked) {
3472                 vcpu->arch.hflags |= HF_NMI_MASK;
3473                 if (!sev_es_guest(vcpu->kvm))
3474                         svm_set_intercept(svm, INTERCEPT_IRET);
3475         } else {
3476                 vcpu->arch.hflags &= ~HF_NMI_MASK;
3477                 if (!sev_es_guest(vcpu->kvm))
3478                         svm_clr_intercept(svm, INTERCEPT_IRET);
3479         }
3480 }
3481
3482 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3483 {
3484         struct vcpu_svm *svm = to_svm(vcpu);
3485         struct vmcb *vmcb = svm->vmcb;
3486
3487         if (!gif_set(svm))
3488                 return true;
3489
3490         if (sev_es_guest(vcpu->kvm)) {
3491                 /*
3492                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3493                  * bit to determine the state of the IF flag.
3494                  */
3495                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3496                         return true;
3497         } else if (is_guest_mode(vcpu)) {
3498                 /* As long as interrupts are being delivered...  */
3499                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3500                     ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3501                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3502                         return true;
3503
3504                 /* ... vmexits aren't blocked by the interrupt shadow  */
3505                 if (nested_exit_on_intr(svm))
3506                         return false;
3507         } else {
3508                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3509                         return true;
3510         }
3511
3512         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3513 }
3514
3515 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3516 {
3517         struct vcpu_svm *svm = to_svm(vcpu);
3518         if (svm->nested.nested_run_pending)
3519                 return -EBUSY;
3520
3521         /*
3522          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3523          * e.g. if the IRQ arrived asynchronously after checking nested events.
3524          */
3525         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3526                 return -EBUSY;
3527
3528         return !svm_interrupt_blocked(vcpu);
3529 }
3530
3531 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3532 {
3533         struct vcpu_svm *svm = to_svm(vcpu);
3534
3535         /*
3536          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3537          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3538          * get that intercept, this function will be called again though and
3539          * we'll get the vintr intercept. However, if the vGIF feature is
3540          * enabled, the STGI interception will not occur. Enable the irq
3541          * window under the assumption that the hardware will set the GIF.
3542          */
3543         if (vgif_enabled(svm) || gif_set(svm)) {
3544                 /*
3545                  * IRQ window is not needed when AVIC is enabled,
3546                  * unless we have pending ExtINT since it cannot be injected
3547                  * via AVIC. In such case, we need to temporarily disable AVIC,
3548                  * and fallback to injecting IRQ via V_IRQ.
3549                  */
3550                 kvm_request_apicv_update(vcpu->kvm, false, APICV_INHIBIT_REASON_IRQWIN);
3551                 svm_set_vintr(svm);
3552         }
3553 }
3554
3555 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3556 {
3557         struct vcpu_svm *svm = to_svm(vcpu);
3558
3559         if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3560                 return; /* IRET will cause a vm exit */
3561
3562         if (!gif_set(svm)) {
3563                 if (vgif_enabled(svm))
3564                         svm_set_intercept(svm, INTERCEPT_STGI);
3565                 return; /* STGI will cause a vm exit */
3566         }
3567
3568         /*
3569          * Something prevents NMI from been injected. Single step over possible
3570          * problem (IRET or exception injection or interrupt shadow)
3571          */
3572         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3573         svm->nmi_singlestep = true;
3574         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3575 }
3576
3577 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3578 {
3579         return 0;
3580 }
3581
3582 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3583 {
3584         return 0;
3585 }
3586
3587 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3588 {
3589         struct vcpu_svm *svm = to_svm(vcpu);
3590
3591         /*
3592          * Flush only the current ASID even if the TLB flush was invoked via
3593          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3594          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3595          * unconditionally does a TLB flush on both nested VM-Enter and nested
3596          * VM-Exit (via kvm_mmu_reset_context()).
3597          */
3598         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3599                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3600         else
3601                 svm->current_vmcb->asid_generation--;
3602 }
3603
3604 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3605 {
3606         struct vcpu_svm *svm = to_svm(vcpu);
3607
3608         invlpga(gva, svm->vmcb->control.asid);
3609 }
3610
3611 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3612 {
3613         struct vcpu_svm *svm = to_svm(vcpu);
3614
3615         if (nested_svm_virtualize_tpr(vcpu))
3616                 return;
3617
3618         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3619                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3620                 kvm_set_cr8(vcpu, cr8);
3621         }
3622 }
3623
3624 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3625 {
3626         struct vcpu_svm *svm = to_svm(vcpu);
3627         u64 cr8;
3628
3629         if (nested_svm_virtualize_tpr(vcpu) ||
3630             kvm_vcpu_apicv_active(vcpu))
3631                 return;
3632
3633         cr8 = kvm_get_cr8(vcpu);
3634         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3635         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3636 }
3637
3638 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3639 {
3640         struct vcpu_svm *svm = to_svm(vcpu);
3641         u8 vector;
3642         int type;
3643         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3644         unsigned int3_injected = svm->int3_injected;
3645
3646         svm->int3_injected = 0;
3647
3648         /*
3649          * If we've made progress since setting HF_IRET_MASK, we've
3650          * executed an IRET and can allow NMI injection.
3651          */
3652         if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3653             (sev_es_guest(vcpu->kvm) ||
3654              kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3655                 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3656                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3657         }
3658
3659         vcpu->arch.nmi_injected = false;
3660         kvm_clear_exception_queue(vcpu);
3661         kvm_clear_interrupt_queue(vcpu);
3662
3663         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3664                 return;
3665
3666         kvm_make_request(KVM_REQ_EVENT, vcpu);
3667
3668         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3669         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3670
3671         switch (type) {
3672         case SVM_EXITINTINFO_TYPE_NMI:
3673                 vcpu->arch.nmi_injected = true;
3674                 break;
3675         case SVM_EXITINTINFO_TYPE_EXEPT:
3676                 /*
3677                  * Never re-inject a #VC exception.
3678                  */
3679                 if (vector == X86_TRAP_VC)
3680                         break;
3681
3682                 /*
3683                  * In case of software exceptions, do not reinject the vector,
3684                  * but re-execute the instruction instead. Rewind RIP first
3685                  * if we emulated INT3 before.
3686                  */
3687                 if (kvm_exception_is_soft(vector)) {
3688                         if (vector == BP_VECTOR && int3_injected &&
3689                             kvm_is_linear_rip(vcpu, svm->int3_rip))
3690                                 kvm_rip_write(vcpu,
3691                                               kvm_rip_read(vcpu) - int3_injected);
3692                         break;
3693                 }
3694                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3695                         u32 err = svm->vmcb->control.exit_int_info_err;
3696                         kvm_requeue_exception_e(vcpu, vector, err);
3697
3698                 } else
3699                         kvm_requeue_exception(vcpu, vector);
3700                 break;
3701         case SVM_EXITINTINFO_TYPE_INTR:
3702                 kvm_queue_interrupt(vcpu, vector, false);
3703                 break;
3704         default:
3705                 break;
3706         }
3707 }
3708
3709 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3710 {
3711         struct vcpu_svm *svm = to_svm(vcpu);
3712         struct vmcb_control_area *control = &svm->vmcb->control;
3713
3714         control->exit_int_info = control->event_inj;
3715         control->exit_int_info_err = control->event_inj_err;
3716         control->event_inj = 0;
3717         svm_complete_interrupts(vcpu);
3718 }
3719
3720 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3721 {
3722         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3723             to_svm(vcpu)->vmcb->control.exit_info_1)
3724                 return handle_fastpath_set_msr_irqoff(vcpu);
3725
3726         return EXIT_FASTPATH_NONE;
3727 }
3728
3729 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3730 {
3731         struct vcpu_svm *svm = to_svm(vcpu);
3732         unsigned long vmcb_pa = svm->current_vmcb->pa;
3733
3734         kvm_guest_enter_irqoff();
3735
3736         if (sev_es_guest(vcpu->kvm)) {
3737                 __svm_sev_es_vcpu_run(vmcb_pa);
3738         } else {
3739                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3740
3741                 /*
3742                  * Use a single vmcb (vmcb01 because it's always valid) for
3743                  * context switching guest state via VMLOAD/VMSAVE, that way
3744                  * the state doesn't need to be copied between vmcb01 and
3745                  * vmcb02 when switching vmcbs for nested virtualization.
3746                  */
3747                 vmload(svm->vmcb01.pa);
3748                 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3749                 vmsave(svm->vmcb01.pa);
3750
3751                 vmload(__sme_page_pa(sd->save_area));
3752         }
3753
3754         kvm_guest_exit_irqoff();
3755 }
3756
3757 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3758 {
3759         struct vcpu_svm *svm = to_svm(vcpu);
3760
3761         trace_kvm_entry(vcpu);
3762
3763         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3764         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3765         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3766
3767         /*
3768          * Disable singlestep if we're injecting an interrupt/exception.
3769          * We don't want our modified rflags to be pushed on the stack where
3770          * we might not be able to easily reset them if we disabled NMI
3771          * singlestep later.
3772          */
3773         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3774                 /*
3775                  * Event injection happens before external interrupts cause a
3776                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3777                  * is enough to force an immediate vmexit.
3778                  */
3779                 disable_nmi_singlestep(svm);
3780                 smp_send_reschedule(vcpu->cpu);
3781         }
3782
3783         pre_svm_run(vcpu);
3784
3785         WARN_ON_ONCE(kvm_apicv_activated(vcpu->kvm) != kvm_vcpu_apicv_active(vcpu));
3786
3787         sync_lapic_to_cr8(vcpu);
3788
3789         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3790                 svm->vmcb->control.asid = svm->asid;
3791                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3792         }
3793         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3794
3795         svm_hv_update_vp_id(svm->vmcb, vcpu);
3796
3797         /*
3798          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3799          * of a #DB.
3800          */
3801         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3802                 svm_set_dr6(svm, vcpu->arch.dr6);
3803         else
3804                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3805
3806         clgi();
3807         kvm_load_guest_xsave_state(vcpu);
3808
3809         kvm_wait_lapic_expire(vcpu);
3810
3811         /*
3812          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3813          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3814          * is no need to worry about the conditional branch over the wrmsr
3815          * being speculatively taken.
3816          */
3817         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3818                 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3819
3820         svm_vcpu_enter_exit(vcpu);
3821
3822         /*
3823          * We do not use IBRS in the kernel. If this vCPU has used the
3824          * SPEC_CTRL MSR it may have left it on; save the value and
3825          * turn it off. This is much more efficient than blindly adding
3826          * it to the atomic save/restore list. Especially as the former
3827          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3828          *
3829          * For non-nested case:
3830          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3831          * save it.
3832          *
3833          * For nested case:
3834          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3835          * save it.
3836          */
3837         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3838             unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3839                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3840
3841         if (!sev_es_guest(vcpu->kvm))
3842                 reload_tss(vcpu);
3843
3844         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3845                 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3846
3847         if (!sev_es_guest(vcpu->kvm)) {
3848                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3849                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3850                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3851                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3852         }
3853
3854         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3855                 kvm_before_interrupt(vcpu);
3856
3857         kvm_load_host_xsave_state(vcpu);
3858         stgi();
3859
3860         /* Any pending NMI will happen here */
3861
3862         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3863                 kvm_after_interrupt(vcpu);
3864
3865         sync_cr8_to_lapic(vcpu);
3866
3867         svm->next_rip = 0;
3868         if (is_guest_mode(vcpu)) {
3869                 nested_sync_control_from_vmcb02(svm);
3870
3871                 /* Track VMRUNs that have made past consistency checking */
3872                 if (svm->nested.nested_run_pending &&
3873                     svm->vmcb->control.exit_code != SVM_EXIT_ERR)
3874                         ++vcpu->stat.nested_run;
3875
3876                 svm->nested.nested_run_pending = 0;
3877         }
3878
3879         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3880         vmcb_mark_all_clean(svm->vmcb);
3881
3882         /* if exit due to PF check for async PF */
3883         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3884                 vcpu->arch.apf.host_apf_flags =
3885                         kvm_read_and_reset_apf_flags();
3886
3887         if (npt_enabled)
3888                 kvm_register_clear_available(vcpu, VCPU_EXREG_PDPTR);
3889
3890         /*
3891          * We need to handle MC intercepts here before the vcpu has a chance to
3892          * change the physical cpu
3893          */
3894         if (unlikely(svm->vmcb->control.exit_code ==
3895                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3896                 svm_handle_mce(vcpu);
3897
3898         svm_complete_interrupts(vcpu);
3899
3900         if (is_guest_mode(vcpu))
3901                 return EXIT_FASTPATH_NONE;
3902
3903         return svm_exit_handlers_fastpath(vcpu);
3904 }
3905
3906 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3907                              int root_level)
3908 {
3909         struct vcpu_svm *svm = to_svm(vcpu);
3910         unsigned long cr3;
3911
3912         if (npt_enabled) {
3913                 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3914                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3915
3916                 hv_track_root_tdp(vcpu, root_hpa);
3917
3918                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3919                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3920                         return;
3921                 cr3 = vcpu->arch.cr3;
3922         } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3923                 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3924         } else {
3925                 /* PCID in the guest should be impossible with a 32-bit MMU. */
3926                 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3927                 cr3 = root_hpa;
3928         }
3929
3930         svm->vmcb->save.cr3 = cr3;
3931         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3932 }
3933
3934 static int is_disabled(void)
3935 {
3936         u64 vm_cr;
3937
3938         rdmsrl(MSR_VM_CR, vm_cr);
3939         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3940                 return 1;
3941
3942         return 0;
3943 }
3944
3945 static void
3946 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3947 {
3948         /*
3949          * Patch in the VMMCALL instruction:
3950          */
3951         hypercall[0] = 0x0f;
3952         hypercall[1] = 0x01;
3953         hypercall[2] = 0xd9;
3954 }
3955
3956 static int __init svm_check_processor_compat(void)
3957 {
3958         return 0;
3959 }
3960
3961 static bool svm_cpu_has_accelerated_tpr(void)
3962 {
3963         return false;
3964 }
3965
3966 /*
3967  * The kvm parameter can be NULL (module initialization, or invocation before
3968  * VM creation). Be sure to check the kvm parameter before using it.
3969  */
3970 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3971 {
3972         switch (index) {
3973         case MSR_IA32_MCG_EXT_CTL:
3974         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3975                 return false;
3976         case MSR_IA32_SMBASE:
3977                 /* SEV-ES guests do not support SMM, so report false */
3978                 if (kvm && sev_es_guest(kvm))
3979                         return false;
3980                 break;
3981         default:
3982                 break;
3983         }
3984
3985         return true;
3986 }
3987
3988 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3989 {
3990         return 0;
3991 }
3992
3993 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3994 {
3995         struct vcpu_svm *svm = to_svm(vcpu);
3996         struct kvm_cpuid_entry2 *best;
3997
3998         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3999                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
4000                                     boot_cpu_has(X86_FEATURE_XSAVES);
4001
4002         /* Update nrips enabled cache */
4003         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4004                              guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4005
4006         svm_recalc_instruction_intercepts(vcpu, svm);
4007
4008         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
4009         if (sev_guest(vcpu->kvm)) {
4010                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4011                 if (best)
4012                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4013         }
4014
4015         if (kvm_vcpu_apicv_active(vcpu)) {
4016                 /*
4017                  * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4018                  * is exposed to the guest, disable AVIC.
4019                  */
4020                 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4021                         kvm_request_apicv_update(vcpu->kvm, false,
4022                                                  APICV_INHIBIT_REASON_X2APIC);
4023
4024                 /*
4025                  * Currently, AVIC does not work with nested virtualization.
4026                  * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4027                  */
4028                 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4029                         kvm_request_apicv_update(vcpu->kvm, false,
4030                                                  APICV_INHIBIT_REASON_NESTED);
4031         }
4032
4033         if (guest_cpuid_is_intel(vcpu)) {
4034                 /*
4035                  * We must intercept SYSENTER_EIP and SYSENTER_ESP
4036                  * accesses because the processor only stores 32 bits.
4037                  * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4038                  */
4039                 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4040                 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4041                 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4042
4043                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4044                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4045         } else {
4046                 /*
4047                  * If hardware supports Virtual VMLOAD VMSAVE then enable it
4048                  * in VMCB and clear intercepts to avoid #VMEXIT.
4049                  */
4050                 if (vls) {
4051                         svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4052                         svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4053                         svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4054                 }
4055                 /* No need to intercept these MSRs */
4056                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4057                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4058         }
4059 }
4060
4061 static bool svm_has_wbinvd_exit(void)
4062 {
4063         return true;
4064 }
4065
4066 #define PRE_EX(exit)  { .exit_code = (exit), \
4067                         .stage = X86_ICPT_PRE_EXCEPT, }
4068 #define POST_EX(exit) { .exit_code = (exit), \
4069                         .stage = X86_ICPT_POST_EXCEPT, }
4070 #define POST_MEM(exit) { .exit_code = (exit), \
4071                         .stage = X86_ICPT_POST_MEMACCESS, }
4072
4073 static const struct __x86_intercept {
4074         u32 exit_code;
4075         enum x86_intercept_stage stage;
4076 } x86_intercept_map[] = {
4077         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4078         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4079         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4080         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4081         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4082         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4083         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4084         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4085         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4086         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4087         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4088         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4089         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4090         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4091         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4092         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4093         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4094         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4095         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4096         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4097         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4098         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4099         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4100         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4101         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4102         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4103         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4104         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4105         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4106         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4107         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4108         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4109         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4110         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4111         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4112         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4113         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4114         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4115         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4116         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4117         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4118         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4119         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4120         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4121         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4122         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4123         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4124 };
4125
4126 #undef PRE_EX
4127 #undef POST_EX
4128 #undef POST_MEM
4129
4130 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4131                                struct x86_instruction_info *info,
4132                                enum x86_intercept_stage stage,
4133                                struct x86_exception *exception)
4134 {
4135         struct vcpu_svm *svm = to_svm(vcpu);
4136         int vmexit, ret = X86EMUL_CONTINUE;
4137         struct __x86_intercept icpt_info;
4138         struct vmcb *vmcb = svm->vmcb;
4139
4140         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4141                 goto out;
4142
4143         icpt_info = x86_intercept_map[info->intercept];
4144
4145         if (stage != icpt_info.stage)
4146                 goto out;
4147
4148         switch (icpt_info.exit_code) {
4149         case SVM_EXIT_READ_CR0:
4150                 if (info->intercept == x86_intercept_cr_read)
4151                         icpt_info.exit_code += info->modrm_reg;
4152                 break;
4153         case SVM_EXIT_WRITE_CR0: {
4154                 unsigned long cr0, val;
4155
4156                 if (info->intercept == x86_intercept_cr_write)
4157                         icpt_info.exit_code += info->modrm_reg;
4158
4159                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4160                     info->intercept == x86_intercept_clts)
4161                         break;
4162
4163                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4164                                         INTERCEPT_SELECTIVE_CR0)))
4165                         break;
4166
4167                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4168                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4169
4170                 if (info->intercept == x86_intercept_lmsw) {
4171                         cr0 &= 0xfUL;
4172                         val &= 0xfUL;
4173                         /* lmsw can't clear PE - catch this here */
4174                         if (cr0 & X86_CR0_PE)
4175                                 val |= X86_CR0_PE;
4176                 }
4177
4178                 if (cr0 ^ val)
4179                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4180
4181                 break;
4182         }
4183         case SVM_EXIT_READ_DR0:
4184         case SVM_EXIT_WRITE_DR0:
4185                 icpt_info.exit_code += info->modrm_reg;
4186                 break;
4187         case SVM_EXIT_MSR:
4188                 if (info->intercept == x86_intercept_wrmsr)
4189                         vmcb->control.exit_info_1 = 1;
4190                 else
4191                         vmcb->control.exit_info_1 = 0;
4192                 break;
4193         case SVM_EXIT_PAUSE:
4194                 /*
4195                  * We get this for NOP only, but pause
4196                  * is rep not, check this here
4197                  */
4198                 if (info->rep_prefix != REPE_PREFIX)
4199                         goto out;
4200                 break;
4201         case SVM_EXIT_IOIO: {
4202                 u64 exit_info;
4203                 u32 bytes;
4204
4205                 if (info->intercept == x86_intercept_in ||
4206                     info->intercept == x86_intercept_ins) {
4207                         exit_info = ((info->src_val & 0xffff) << 16) |
4208                                 SVM_IOIO_TYPE_MASK;
4209                         bytes = info->dst_bytes;
4210                 } else {
4211                         exit_info = (info->dst_val & 0xffff) << 16;
4212                         bytes = info->src_bytes;
4213                 }
4214
4215                 if (info->intercept == x86_intercept_outs ||
4216                     info->intercept == x86_intercept_ins)
4217                         exit_info |= SVM_IOIO_STR_MASK;
4218
4219                 if (info->rep_prefix)
4220                         exit_info |= SVM_IOIO_REP_MASK;
4221
4222                 bytes = min(bytes, 4u);
4223
4224                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4225
4226                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4227
4228                 vmcb->control.exit_info_1 = exit_info;
4229                 vmcb->control.exit_info_2 = info->next_rip;
4230
4231                 break;
4232         }
4233         default:
4234                 break;
4235         }
4236
4237         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4238         if (static_cpu_has(X86_FEATURE_NRIPS))
4239                 vmcb->control.next_rip  = info->next_rip;
4240         vmcb->control.exit_code = icpt_info.exit_code;
4241         vmexit = nested_svm_exit_handled(svm);
4242
4243         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4244                                            : X86EMUL_CONTINUE;
4245
4246 out:
4247         return ret;
4248 }
4249
4250 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4251 {
4252 }
4253
4254 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4255 {
4256         if (!kvm_pause_in_guest(vcpu->kvm))
4257                 shrink_ple_window(vcpu);
4258 }
4259
4260 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4261 {
4262         /* [63:9] are reserved. */
4263         vcpu->arch.mcg_cap &= 0x1ff;
4264 }
4265
4266 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4267 {
4268         struct vcpu_svm *svm = to_svm(vcpu);
4269
4270         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4271         if (!gif_set(svm))
4272                 return true;
4273
4274         return is_smm(vcpu);
4275 }
4276
4277 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4278 {
4279         struct vcpu_svm *svm = to_svm(vcpu);
4280         if (svm->nested.nested_run_pending)
4281                 return -EBUSY;
4282
4283         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4284         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4285                 return -EBUSY;
4286
4287         return !svm_smi_blocked(vcpu);
4288 }
4289
4290 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4291 {
4292         struct vcpu_svm *svm = to_svm(vcpu);
4293         struct kvm_host_map map_save;
4294         int ret;
4295
4296         if (is_guest_mode(vcpu)) {
4297                 /* FED8h - SVM Guest */
4298                 put_smstate(u64, smstate, 0x7ed8, 1);
4299                 /* FEE0h - SVM Guest VMCB Physical Address */
4300                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4301
4302                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4303                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4304                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4305
4306                 ret = nested_svm_vmexit(svm);
4307                 if (ret)
4308                         return ret;
4309
4310                 /*
4311                  * KVM uses VMCB01 to store L1 host state while L2 runs but
4312                  * VMCB01 is going to be used during SMM and thus the state will
4313                  * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4314                  * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4315                  * format of the area is identical to guest save area offsetted
4316                  * by 0x400 (matches the offset of 'struct vmcb_save_area'
4317                  * within 'struct vmcb'). Note: HSAVE area may also be used by
4318                  * L1 hypervisor to save additional host context (e.g. KVM does
4319                  * that, see svm_prepare_guest_switch()) which must be
4320                  * preserved.
4321                  */
4322                 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4323                                  &map_save) == -EINVAL)
4324                         return 1;
4325
4326                 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4327
4328                 svm_copy_vmrun_state(map_save.hva + 0x400,
4329                                      &svm->vmcb01.ptr->save);
4330
4331                 kvm_vcpu_unmap(vcpu, &map_save, true);
4332         }
4333         return 0;
4334 }
4335
4336 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4337 {
4338         struct vcpu_svm *svm = to_svm(vcpu);
4339         struct kvm_host_map map, map_save;
4340         int ret = 0;
4341
4342         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4343                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4344                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4345                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4346                 struct vmcb *vmcb12;
4347
4348                 if (guest) {
4349                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4350                                 return 1;
4351
4352                         if (!(saved_efer & EFER_SVME))
4353                                 return 1;
4354
4355                         if (kvm_vcpu_map(vcpu,
4356                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4357                                 return 1;
4358
4359                         if (svm_allocate_nested(svm))
4360                                 return 1;
4361
4362                         vmcb12 = map.hva;
4363
4364                         nested_load_control_from_vmcb12(svm, &vmcb12->control);
4365
4366                         ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12);
4367                         kvm_vcpu_unmap(vcpu, &map, true);
4368
4369                         /*
4370                          * Restore L1 host state from L1 HSAVE area as VMCB01 was
4371                          * used during SMM (see svm_enter_smm())
4372                          */
4373                         if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4374                                          &map_save) == -EINVAL)
4375                                 return 1;
4376
4377                         svm_copy_vmrun_state(&svm->vmcb01.ptr->save,
4378                                              map_save.hva + 0x400);
4379
4380                         kvm_vcpu_unmap(vcpu, &map_save, true);
4381                 }
4382         }
4383
4384         return ret;
4385 }
4386
4387 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4388 {
4389         struct vcpu_svm *svm = to_svm(vcpu);
4390
4391         if (!gif_set(svm)) {
4392                 if (vgif_enabled(svm))
4393                         svm_set_intercept(svm, INTERCEPT_STGI);
4394                 /* STGI will cause a vm exit */
4395         } else {
4396                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4397         }
4398 }
4399
4400 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4401 {
4402         bool smep, smap, is_user;
4403         unsigned long cr4;
4404
4405         /*
4406          * When the guest is an SEV-ES guest, emulation is not possible.
4407          */
4408         if (sev_es_guest(vcpu->kvm))
4409                 return false;
4410
4411         /*
4412          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4413          *
4414          * Errata:
4415          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4416          * possible that CPU microcode implementing DecodeAssist will fail
4417          * to read bytes of instruction which caused #NPF. In this case,
4418          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4419          * return 0 instead of the correct guest instruction bytes.
4420          *
4421          * This happens because CPU microcode reading instruction bytes
4422          * uses a special opcode which attempts to read data using CPL=0
4423          * privileges. The microcode reads CS:RIP and if it hits a SMAP
4424          * fault, it gives up and returns no instruction bytes.
4425          *
4426          * Detection:
4427          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4428          * returned 0 in GuestIntrBytes field of the VMCB.
4429          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4430          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4431          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4432          * a SMEP fault instead of #NPF).
4433          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4434          * As most guests enable SMAP if they have also enabled SMEP, use above
4435          * logic in order to attempt minimize false-positive of detecting errata
4436          * while still preserving all cases semantic correctness.
4437          *
4438          * Workaround:
4439          * To determine what instruction the guest was executing, the hypervisor
4440          * will have to decode the instruction at the instruction pointer.
4441          *
4442          * In non SEV guest, hypervisor will be able to read the guest
4443          * memory to decode the instruction pointer when insn_len is zero
4444          * so we return true to indicate that decoding is possible.
4445          *
4446          * But in the SEV guest, the guest memory is encrypted with the
4447          * guest specific key and hypervisor will not be able to decode the
4448          * instruction pointer so we will not able to workaround it. Lets
4449          * print the error and request to kill the guest.
4450          */
4451         if (likely(!insn || insn_len))
4452                 return true;
4453
4454         /*
4455          * If RIP is invalid, go ahead with emulation which will cause an
4456          * internal error exit.
4457          */
4458         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4459                 return true;
4460
4461         cr4 = kvm_read_cr4(vcpu);
4462         smep = cr4 & X86_CR4_SMEP;
4463         smap = cr4 & X86_CR4_SMAP;
4464         is_user = svm_get_cpl(vcpu) == 3;
4465         if (smap && (!smep || is_user)) {
4466                 if (!sev_guest(vcpu->kvm))
4467                         return true;
4468
4469                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4470                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4471         }
4472
4473         return false;
4474 }
4475
4476 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4477 {
4478         struct vcpu_svm *svm = to_svm(vcpu);
4479
4480         /*
4481          * TODO: Last condition latch INIT signals on vCPU when
4482          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4483          * To properly emulate the INIT intercept,
4484          * svm_check_nested_events() should call nested_svm_vmexit()
4485          * if an INIT signal is pending.
4486          */
4487         return !gif_set(svm) ||
4488                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4489 }
4490
4491 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4492 {
4493         if (!sev_es_guest(vcpu->kvm))
4494                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4495
4496         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4497 }
4498
4499 static void svm_vm_destroy(struct kvm *kvm)
4500 {
4501         avic_vm_destroy(kvm);
4502         sev_vm_destroy(kvm);
4503 }
4504
4505 static int svm_vm_init(struct kvm *kvm)
4506 {
4507         if (!pause_filter_count || !pause_filter_thresh)
4508                 kvm->arch.pause_in_guest = true;
4509
4510         if (enable_apicv) {
4511                 int ret = avic_vm_init(kvm);
4512                 if (ret)
4513                         return ret;
4514         }
4515
4516         return 0;
4517 }
4518
4519 static struct kvm_x86_ops svm_x86_ops __initdata = {
4520         .hardware_unsetup = svm_hardware_teardown,
4521         .hardware_enable = svm_hardware_enable,
4522         .hardware_disable = svm_hardware_disable,
4523         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4524         .has_emulated_msr = svm_has_emulated_msr,
4525
4526         .vcpu_create = svm_create_vcpu,
4527         .vcpu_free = svm_free_vcpu,
4528         .vcpu_reset = svm_vcpu_reset,
4529
4530         .vm_size = sizeof(struct kvm_svm),
4531         .vm_init = svm_vm_init,
4532         .vm_destroy = svm_vm_destroy,
4533
4534         .prepare_guest_switch = svm_prepare_guest_switch,
4535         .vcpu_load = svm_vcpu_load,
4536         .vcpu_put = svm_vcpu_put,
4537         .vcpu_blocking = svm_vcpu_blocking,
4538         .vcpu_unblocking = svm_vcpu_unblocking,
4539
4540         .update_exception_bitmap = svm_update_exception_bitmap,
4541         .get_msr_feature = svm_get_msr_feature,
4542         .get_msr = svm_get_msr,
4543         .set_msr = svm_set_msr,
4544         .get_segment_base = svm_get_segment_base,
4545         .get_segment = svm_get_segment,
4546         .set_segment = svm_set_segment,
4547         .get_cpl = svm_get_cpl,
4548         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4549         .set_cr0 = svm_set_cr0,
4550         .is_valid_cr4 = svm_is_valid_cr4,
4551         .set_cr4 = svm_set_cr4,
4552         .set_efer = svm_set_efer,
4553         .get_idt = svm_get_idt,
4554         .set_idt = svm_set_idt,
4555         .get_gdt = svm_get_gdt,
4556         .set_gdt = svm_set_gdt,
4557         .set_dr7 = svm_set_dr7,
4558         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4559         .cache_reg = svm_cache_reg,
4560         .get_rflags = svm_get_rflags,
4561         .set_rflags = svm_set_rflags,
4562
4563         .tlb_flush_all = svm_flush_tlb,
4564         .tlb_flush_current = svm_flush_tlb,
4565         .tlb_flush_gva = svm_flush_tlb_gva,
4566         .tlb_flush_guest = svm_flush_tlb,
4567
4568         .run = svm_vcpu_run,
4569         .handle_exit = handle_exit,
4570         .skip_emulated_instruction = skip_emulated_instruction,
4571         .update_emulated_instruction = NULL,
4572         .set_interrupt_shadow = svm_set_interrupt_shadow,
4573         .get_interrupt_shadow = svm_get_interrupt_shadow,
4574         .patch_hypercall = svm_patch_hypercall,
4575         .set_irq = svm_set_irq,
4576         .set_nmi = svm_inject_nmi,
4577         .queue_exception = svm_queue_exception,
4578         .cancel_injection = svm_cancel_injection,
4579         .interrupt_allowed = svm_interrupt_allowed,
4580         .nmi_allowed = svm_nmi_allowed,
4581         .get_nmi_mask = svm_get_nmi_mask,
4582         .set_nmi_mask = svm_set_nmi_mask,
4583         .enable_nmi_window = svm_enable_nmi_window,
4584         .enable_irq_window = svm_enable_irq_window,
4585         .update_cr8_intercept = svm_update_cr8_intercept,
4586         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4587         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4588         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4589         .load_eoi_exitmap = svm_load_eoi_exitmap,
4590         .hwapic_irr_update = svm_hwapic_irr_update,
4591         .hwapic_isr_update = svm_hwapic_isr_update,
4592         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4593         .apicv_post_state_restore = avic_post_state_restore,
4594
4595         .set_tss_addr = svm_set_tss_addr,
4596         .set_identity_map_addr = svm_set_identity_map_addr,
4597         .get_mt_mask = svm_get_mt_mask,
4598
4599         .get_exit_info = svm_get_exit_info,
4600
4601         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4602
4603         .has_wbinvd_exit = svm_has_wbinvd_exit,
4604
4605         .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4606         .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4607         .write_tsc_offset = svm_write_tsc_offset,
4608         .write_tsc_multiplier = svm_write_tsc_multiplier,
4609
4610         .load_mmu_pgd = svm_load_mmu_pgd,
4611
4612         .check_intercept = svm_check_intercept,
4613         .handle_exit_irqoff = svm_handle_exit_irqoff,
4614
4615         .request_immediate_exit = __kvm_request_immediate_exit,
4616
4617         .sched_in = svm_sched_in,
4618
4619         .pmu_ops = &amd_pmu_ops,
4620         .nested_ops = &svm_nested_ops,
4621
4622         .deliver_posted_interrupt = svm_deliver_avic_intr,
4623         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4624         .update_pi_irte = svm_update_pi_irte,
4625         .setup_mce = svm_setup_mce,
4626
4627         .smi_allowed = svm_smi_allowed,
4628         .enter_smm = svm_enter_smm,
4629         .leave_smm = svm_leave_smm,
4630         .enable_smi_window = svm_enable_smi_window,
4631
4632         .mem_enc_op = svm_mem_enc_op,
4633         .mem_enc_reg_region = svm_register_enc_region,
4634         .mem_enc_unreg_region = svm_unregister_enc_region,
4635
4636         .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4637
4638         .can_emulate_instruction = svm_can_emulate_instruction,
4639
4640         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4641
4642         .msr_filter_changed = svm_msr_filter_changed,
4643         .complete_emulated_msr = svm_complete_emulated_msr,
4644
4645         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4646 };
4647
4648 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4649         .cpu_has_kvm_support = has_svm,
4650         .disabled_by_bios = is_disabled,
4651         .hardware_setup = svm_hardware_setup,
4652         .check_processor_compatibility = svm_check_processor_compat,
4653
4654         .runtime_ops = &svm_x86_ops,
4655 };
4656
4657 static int __init svm_init(void)
4658 {
4659         __unused_size_checks();
4660
4661         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4662                         __alignof__(struct vcpu_svm), THIS_MODULE);
4663 }
4664
4665 static void __exit svm_exit(void)
4666 {
4667         kvm_exit();
4668 }
4669
4670 module_init(svm_init)
4671 module_exit(svm_exit)