1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
13 #include <linux/module.h>
14 #include <linux/mod_devicetable.h>
15 #include <linux/kernel.h>
16 #include <linux/vmalloc.h>
17 #include <linux/highmem.h>
18 #include <linux/amd-iommu.h>
19 #include <linux/sched.h>
20 #include <linux/trace_events.h>
21 #include <linux/slab.h>
22 #include <linux/hashtable.h>
23 #include <linux/objtool.h>
24 #include <linux/psp-sev.h>
25 #include <linux/file.h>
26 #include <linux/pagemap.h>
27 #include <linux/swap.h>
28 #include <linux/rwsem.h>
29 #include <linux/cc_platform.h>
30 #include <linux/smp.h>
33 #include <asm/perf_event.h>
34 #include <asm/tlbflush.h>
36 #include <asm/debugreg.h>
37 #include <asm/kvm_para.h>
38 #include <asm/irq_remapping.h>
39 #include <asm/spec-ctrl.h>
40 #include <asm/cpu_device_id.h>
41 #include <asm/traps.h>
42 #include <asm/reboot.h>
43 #include <asm/fpu/api.h>
45 #include <trace/events/ipi.h>
52 #include "kvm_onhyperv.h"
53 #include "svm_onhyperv.h"
55 MODULE_AUTHOR("Qumranet");
56 MODULE_LICENSE("GPL");
59 static const struct x86_cpu_id svm_cpu_id[] = {
60 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
63 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
66 #define SEG_TYPE_LDT 2
67 #define SEG_TYPE_BUSY_TSS16 3
69 static bool erratum_383_found __read_mostly;
71 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
74 * Set osvw_len to higher value when updated Revision Guides
75 * are published and we know what the new status bits are
77 static uint64_t osvw_len = 4, osvw_status;
79 static DEFINE_PER_CPU(u64, current_tsc_ratio);
81 #define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
83 static const struct svm_direct_access_msrs {
84 u32 index; /* Index of the MSR */
85 bool always; /* True if intercept is initially cleared */
86 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
87 { .index = MSR_STAR, .always = true },
88 { .index = MSR_IA32_SYSENTER_CS, .always = true },
89 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
90 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
92 { .index = MSR_GS_BASE, .always = true },
93 { .index = MSR_FS_BASE, .always = true },
94 { .index = MSR_KERNEL_GS_BASE, .always = true },
95 { .index = MSR_LSTAR, .always = true },
96 { .index = MSR_CSTAR, .always = true },
97 { .index = MSR_SYSCALL_MASK, .always = true },
99 { .index = MSR_IA32_SPEC_CTRL, .always = false },
100 { .index = MSR_IA32_PRED_CMD, .always = false },
101 { .index = MSR_IA32_FLUSH_CMD, .always = false },
102 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
103 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
104 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
105 { .index = MSR_IA32_LASTINTTOIP, .always = false },
106 { .index = MSR_EFER, .always = false },
107 { .index = MSR_IA32_CR_PAT, .always = false },
108 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
109 { .index = MSR_TSC_AUX, .always = false },
110 { .index = X2APIC_MSR(APIC_ID), .always = false },
111 { .index = X2APIC_MSR(APIC_LVR), .always = false },
112 { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
113 { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
114 { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
115 { .index = X2APIC_MSR(APIC_EOI), .always = false },
116 { .index = X2APIC_MSR(APIC_RRR), .always = false },
117 { .index = X2APIC_MSR(APIC_LDR), .always = false },
118 { .index = X2APIC_MSR(APIC_DFR), .always = false },
119 { .index = X2APIC_MSR(APIC_SPIV), .always = false },
120 { .index = X2APIC_MSR(APIC_ISR), .always = false },
121 { .index = X2APIC_MSR(APIC_TMR), .always = false },
122 { .index = X2APIC_MSR(APIC_IRR), .always = false },
123 { .index = X2APIC_MSR(APIC_ESR), .always = false },
124 { .index = X2APIC_MSR(APIC_ICR), .always = false },
125 { .index = X2APIC_MSR(APIC_ICR2), .always = false },
129 * AMD does not virtualize APIC TSC-deadline timer mode, but it is
130 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18,
131 * the AVIC hardware would generate GP fault. Therefore, always
132 * intercept the MSR 0x832, and do not setup direct_access_msr.
134 { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
135 { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
136 { .index = X2APIC_MSR(APIC_LVT0), .always = false },
137 { .index = X2APIC_MSR(APIC_LVT1), .always = false },
138 { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
139 { .index = X2APIC_MSR(APIC_TMICT), .always = false },
140 { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
141 { .index = X2APIC_MSR(APIC_TDCR), .always = false },
142 { .index = MSR_INVALID, .always = false },
146 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
147 * pause_filter_count: On processors that support Pause filtering(indicated
148 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
149 * count value. On VMRUN this value is loaded into an internal counter.
150 * Each time a pause instruction is executed, this counter is decremented
151 * until it reaches zero at which time a #VMEXIT is generated if pause
152 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
153 * Intercept Filtering for more details.
154 * This also indicate if ple logic enabled.
156 * pause_filter_thresh: In addition, some processor families support advanced
157 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
158 * the amount of time a guest is allowed to execute in a pause loop.
159 * In this mode, a 16-bit pause filter threshold field is added in the
160 * VMCB. The threshold value is a cycle count that is used to reset the
161 * pause counter. As with simple pause filtering, VMRUN loads the pause
162 * count value from VMCB into an internal counter. Then, on each pause
163 * instruction the hardware checks the elapsed number of cycles since
164 * the most recent pause instruction against the pause filter threshold.
165 * If the elapsed cycle count is greater than the pause filter threshold,
166 * then the internal pause count is reloaded from the VMCB and execution
167 * continues. If the elapsed cycle count is less than the pause filter
168 * threshold, then the internal pause count is decremented. If the count
169 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
170 * triggered. If advanced pause filtering is supported and pause filter
171 * threshold field is set to zero, the filter will operate in the simpler,
175 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
176 module_param(pause_filter_thresh, ushort, 0444);
178 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
179 module_param(pause_filter_count, ushort, 0444);
181 /* Default doubles per-vcpu window every exit. */
182 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
183 module_param(pause_filter_count_grow, ushort, 0444);
185 /* Default resets per-vcpu window every exit to pause_filter_count. */
186 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
187 module_param(pause_filter_count_shrink, ushort, 0444);
189 /* Default is to compute the maximum so we can never overflow. */
190 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
191 module_param(pause_filter_count_max, ushort, 0444);
194 * Use nested page tables by default. Note, NPT may get forced off by
195 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
197 bool npt_enabled = true;
198 module_param_named(npt, npt_enabled, bool, 0444);
200 /* allow nested virtualization in KVM/SVM */
201 static int nested = true;
202 module_param(nested, int, S_IRUGO);
204 /* enable/disable Next RIP Save */
206 module_param(nrips, int, 0444);
208 /* enable/disable Virtual VMLOAD VMSAVE */
209 static int vls = true;
210 module_param(vls, int, 0444);
212 /* enable/disable Virtual GIF */
214 module_param(vgif, int, 0444);
216 /* enable/disable LBR virtualization */
217 static int lbrv = true;
218 module_param(lbrv, int, 0444);
220 static int tsc_scaling = true;
221 module_param(tsc_scaling, int, 0444);
224 * enable / disable AVIC. Because the defaults differ for APICv
225 * support between VMX and SVM we cannot use module_param_named.
228 module_param(avic, bool, 0444);
230 bool __read_mostly dump_invalid_vmcb;
231 module_param(dump_invalid_vmcb, bool, 0644);
234 bool intercept_smi = true;
235 module_param(intercept_smi, bool, 0444);
238 module_param(vnmi, bool, 0444);
240 static bool svm_gp_erratum_intercept = true;
242 static u8 rsm_ins_bytes[] = "\x0f\xaa";
244 static unsigned long iopm_base;
246 DEFINE_PER_CPU(struct svm_cpu_data, svm_data);
249 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
250 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
252 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
253 * defer the restoration of TSC_AUX until the CPU returns to userspace.
255 static int tsc_aux_uret_slot __read_mostly = -1;
257 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
259 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
260 #define MSRS_RANGE_SIZE 2048
261 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
263 u32 svm_msrpm_offset(u32 msr)
268 for (i = 0; i < NUM_MSR_MAPS; i++) {
269 if (msr < msrpm_ranges[i] ||
270 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
273 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
274 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
276 /* Now we have the u8 offset - but need the u32 offset */
280 /* MSR not in any range */
284 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu);
286 static int get_npt_level(void)
289 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
291 return PT32E_ROOT_LEVEL;
295 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
297 struct vcpu_svm *svm = to_svm(vcpu);
298 u64 old_efer = vcpu->arch.efer;
299 vcpu->arch.efer = efer;
302 /* Shadow paging assumes NX to be available. */
305 if (!(efer & EFER_LMA))
309 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
310 if (!(efer & EFER_SVME)) {
311 svm_leave_nested(vcpu);
312 svm_set_gif(svm, true);
313 /* #GP intercept is still needed for vmware backdoor */
314 if (!enable_vmware_backdoor)
315 clr_exception_intercept(svm, GP_VECTOR);
318 * Free the nested guest state, unless we are in SMM.
319 * In this case we will return to the nested guest
320 * as soon as we leave SMM.
323 svm_free_nested(svm);
326 int ret = svm_allocate_nested(svm);
329 vcpu->arch.efer = old_efer;
334 * Never intercept #GP for SEV guests, KVM can't
335 * decrypt guest memory to workaround the erratum.
337 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm))
338 set_exception_intercept(svm, GP_VECTOR);
342 svm->vmcb->save.efer = efer | EFER_SVME;
343 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
347 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
349 struct vcpu_svm *svm = to_svm(vcpu);
352 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
353 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
357 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
359 struct vcpu_svm *svm = to_svm(vcpu);
362 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
364 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
367 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
368 void *insn, int insn_len);
370 static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu,
371 bool commit_side_effects)
373 struct vcpu_svm *svm = to_svm(vcpu);
374 unsigned long old_rflags;
377 * SEV-ES does not expose the next RIP. The RIP update is controlled by
378 * the type of exit and the #VC handler in the guest.
380 if (sev_es_guest(vcpu->kvm))
383 if (nrips && svm->vmcb->control.next_rip != 0) {
384 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
385 svm->next_rip = svm->vmcb->control.next_rip;
388 if (!svm->next_rip) {
390 * FIXME: Drop this when kvm_emulate_instruction() does the
391 * right thing and treats "can't emulate" as outright failure
394 if (!svm_can_emulate_instruction(vcpu, EMULTYPE_SKIP, NULL, 0))
397 if (unlikely(!commit_side_effects))
398 old_rflags = svm->vmcb->save.rflags;
400 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
403 if (unlikely(!commit_side_effects))
404 svm->vmcb->save.rflags = old_rflags;
406 kvm_rip_write(vcpu, svm->next_rip);
410 if (likely(commit_side_effects))
411 svm_set_interrupt_shadow(vcpu, 0);
416 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
418 return __svm_skip_emulated_instruction(vcpu, true);
421 static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu)
423 unsigned long rip, old_rip = kvm_rip_read(vcpu);
424 struct vcpu_svm *svm = to_svm(vcpu);
427 * Due to architectural shortcomings, the CPU doesn't always provide
428 * NextRIP, e.g. if KVM intercepted an exception that occurred while
429 * the CPU was vectoring an INTO/INT3 in the guest. Temporarily skip
430 * the instruction even if NextRIP is supported to acquire the next
431 * RIP so that it can be shoved into the NextRIP field, otherwise
432 * hardware will fail to advance guest RIP during event injection.
433 * Drop the exception/interrupt if emulation fails and effectively
434 * retry the instruction, it's the least awful option. If NRIPS is
435 * in use, the skip must not commit any side effects such as clearing
436 * the interrupt shadow or RFLAGS.RF.
438 if (!__svm_skip_emulated_instruction(vcpu, !nrips))
441 rip = kvm_rip_read(vcpu);
444 * Save the injection information, even when using next_rip, as the
445 * VMCB's next_rip will be lost (cleared on VM-Exit) if the injection
446 * doesn't complete due to a VM-Exit occurring while the CPU is
447 * vectoring the event. Decoding the instruction isn't guaranteed to
448 * work as there may be no backing instruction, e.g. if the event is
449 * being injected by L1 for L2, or if the guest is patching INT3 into
450 * a different instruction.
452 svm->soft_int_injected = true;
453 svm->soft_int_csbase = svm->vmcb->save.cs.base;
454 svm->soft_int_old_rip = old_rip;
455 svm->soft_int_next_rip = rip;
458 kvm_rip_write(vcpu, old_rip);
460 if (static_cpu_has(X86_FEATURE_NRIPS))
461 svm->vmcb->control.next_rip = rip;
466 static void svm_inject_exception(struct kvm_vcpu *vcpu)
468 struct kvm_queued_exception *ex = &vcpu->arch.exception;
469 struct vcpu_svm *svm = to_svm(vcpu);
471 kvm_deliver_exception_payload(vcpu, ex);
473 if (kvm_exception_is_soft(ex->vector) &&
474 svm_update_soft_interrupt_rip(vcpu))
477 svm->vmcb->control.event_inj = ex->vector
479 | (ex->has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
480 | SVM_EVTINJ_TYPE_EXEPT;
481 svm->vmcb->control.event_inj_err = ex->error_code;
484 static void svm_init_erratum_383(void)
490 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
493 /* Use _safe variants to not break nested virtualization */
494 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
500 low = lower_32_bits(val);
501 high = upper_32_bits(val);
503 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
505 erratum_383_found = true;
508 static void svm_init_osvw(struct kvm_vcpu *vcpu)
511 * Guests should see errata 400 and 415 as fixed (assuming that
512 * HLT and IO instructions are intercepted).
514 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
515 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
518 * By increasing VCPU's osvw.length to 3 we are telling the guest that
519 * all osvw.status bits inside that length, including bit 0 (which is
520 * reserved for erratum 298), are valid. However, if host processor's
521 * osvw_len is 0 then osvw_status[0] carries no information. We need to
522 * be conservative here and therefore we tell the guest that erratum 298
523 * is present (because we really don't know).
525 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
526 vcpu->arch.osvw.status |= 1;
529 static bool __kvm_is_svm_supported(void)
531 int cpu = smp_processor_id();
532 struct cpuinfo_x86 *c = &cpu_data(cpu);
534 if (c->x86_vendor != X86_VENDOR_AMD &&
535 c->x86_vendor != X86_VENDOR_HYGON) {
536 pr_err("CPU %d isn't AMD or Hygon\n", cpu);
540 if (!cpu_has(c, X86_FEATURE_SVM)) {
541 pr_err("SVM not supported by CPU %d\n", cpu);
545 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
546 pr_info("KVM is unsupported when running as an SEV guest\n");
553 static bool kvm_is_svm_supported(void)
558 supported = __kvm_is_svm_supported();
564 static int svm_check_processor_compat(void)
566 if (!__kvm_is_svm_supported())
572 static void __svm_write_tsc_multiplier(u64 multiplier)
574 if (multiplier == __this_cpu_read(current_tsc_ratio))
577 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
578 __this_cpu_write(current_tsc_ratio, multiplier);
581 static inline void kvm_cpu_svm_disable(void)
585 wrmsrl(MSR_VM_HSAVE_PA, 0);
586 rdmsrl(MSR_EFER, efer);
587 if (efer & EFER_SVME) {
589 * Force GIF=1 prior to disabling SVM, e.g. to ensure INIT and
590 * NMI aren't blocked.
593 wrmsrl(MSR_EFER, efer & ~EFER_SVME);
597 static void svm_emergency_disable(void)
599 kvm_rebooting = true;
601 kvm_cpu_svm_disable();
604 static void svm_hardware_disable(void)
606 /* Make sure we clean up behind us */
608 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
610 kvm_cpu_svm_disable();
612 amd_pmu_disable_virt();
615 static int svm_hardware_enable(void)
618 struct svm_cpu_data *sd;
620 int me = raw_smp_processor_id();
622 rdmsrl(MSR_EFER, efer);
623 if (efer & EFER_SVME)
626 sd = per_cpu_ptr(&svm_data, me);
627 sd->asid_generation = 1;
628 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
629 sd->next_asid = sd->max_asid + 1;
630 sd->min_asid = max_sev_asid + 1;
632 wrmsrl(MSR_EFER, efer | EFER_SVME);
634 wrmsrl(MSR_VM_HSAVE_PA, sd->save_area_pa);
636 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
638 * Set the default value, even if we don't use TSC scaling
639 * to avoid having stale value in the msr
641 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
648 * Note that it is possible to have a system with mixed processor
649 * revisions and therefore different OSVW bits. If bits are not the same
650 * on different processors then choose the worst case (i.e. if erratum
651 * is present on one processor and not on another then assume that the
652 * erratum is present everywhere).
654 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
655 uint64_t len, status = 0;
658 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
660 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
664 osvw_status = osvw_len = 0;
668 osvw_status |= status;
669 osvw_status &= (1ULL << osvw_len) - 1;
672 osvw_status = osvw_len = 0;
674 svm_init_erratum_383();
676 amd_pmu_enable_virt();
679 * If TSC_AUX virtualization is supported, TSC_AUX becomes a swap type
680 * "B" field (see sev_es_prepare_switch_to_guest()) for SEV-ES guests.
681 * Since Linux does not change the value of TSC_AUX once set, prime the
682 * TSC_AUX field now to avoid a RDMSR on every vCPU run.
684 if (boot_cpu_has(X86_FEATURE_V_TSC_AUX)) {
685 struct sev_es_save_area *hostsa;
686 u32 __maybe_unused msr_hi;
688 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
690 rdmsr(MSR_TSC_AUX, hostsa->tsc_aux, msr_hi);
696 static void svm_cpu_uninit(int cpu)
698 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
703 kfree(sd->sev_vmcbs);
704 __free_page(sd->save_area);
705 sd->save_area_pa = 0;
706 sd->save_area = NULL;
709 static int svm_cpu_init(int cpu)
711 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
714 memset(sd, 0, sizeof(struct svm_cpu_data));
715 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
719 ret = sev_cpu_init(sd);
723 sd->save_area_pa = __sme_page_pa(sd->save_area);
727 __free_page(sd->save_area);
728 sd->save_area = NULL;
733 static void set_dr_intercepts(struct vcpu_svm *svm)
735 struct vmcb *vmcb = svm->vmcb01.ptr;
737 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_READ);
738 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_READ);
739 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_READ);
740 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_READ);
741 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_READ);
742 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_READ);
743 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_READ);
744 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR0_WRITE);
745 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR1_WRITE);
746 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR2_WRITE);
747 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR3_WRITE);
748 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR4_WRITE);
749 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR5_WRITE);
750 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR6_WRITE);
751 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_READ);
752 vmcb_set_intercept(&vmcb->control, INTERCEPT_DR7_WRITE);
754 recalc_intercepts(svm);
757 static void clr_dr_intercepts(struct vcpu_svm *svm)
759 struct vmcb *vmcb = svm->vmcb01.ptr;
761 vmcb->control.intercepts[INTERCEPT_DR] = 0;
763 recalc_intercepts(svm);
766 static int direct_access_msr_slot(u32 msr)
770 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
771 if (direct_access_msrs[i].index == msr)
777 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
780 struct vcpu_svm *svm = to_svm(vcpu);
781 int slot = direct_access_msr_slot(msr);
786 /* Set the shadow bitmaps to the desired intercept states */
788 set_bit(slot, svm->shadow_msr_intercept.read);
790 clear_bit(slot, svm->shadow_msr_intercept.read);
793 set_bit(slot, svm->shadow_msr_intercept.write);
795 clear_bit(slot, svm->shadow_msr_intercept.write);
798 static bool valid_msr_intercept(u32 index)
800 return direct_access_msr_slot(index) != -ENOENT;
803 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
811 * For non-nested case:
812 * If the L01 MSR bitmap does not intercept the MSR, then we need to
816 * If the L02 MSR bitmap does not intercept the MSR, then we need to
819 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
822 offset = svm_msrpm_offset(msr);
823 bit_write = 2 * (msr & 0x0f) + 1;
826 BUG_ON(offset == MSR_INVALID);
828 return test_bit(bit_write, &tmp);
831 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
832 u32 msr, int read, int write)
834 struct vcpu_svm *svm = to_svm(vcpu);
835 u8 bit_read, bit_write;
840 * If this warning triggers extend the direct_access_msrs list at the
841 * beginning of the file
843 WARN_ON(!valid_msr_intercept(msr));
845 /* Enforce non allowed MSRs to trap */
846 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
849 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
852 offset = svm_msrpm_offset(msr);
853 bit_read = 2 * (msr & 0x0f);
854 bit_write = 2 * (msr & 0x0f) + 1;
857 BUG_ON(offset == MSR_INVALID);
859 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
860 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
864 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
865 svm->nested.force_msr_bitmap_recalc = true;
868 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
871 set_shadow_msr_intercept(vcpu, msr, read, write);
872 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
875 u32 *svm_vcpu_alloc_msrpm(void)
877 unsigned int order = get_order(MSRPM_SIZE);
878 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
884 msrpm = page_address(pages);
885 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
890 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
894 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
895 if (!direct_access_msrs[i].always)
897 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
901 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept)
905 if (intercept == svm->x2avic_msrs_intercepted)
911 for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) {
912 int index = direct_access_msrs[i].index;
914 if ((index < APIC_BASE_MSR) ||
915 (index > APIC_BASE_MSR + 0xff))
917 set_msr_interception(&svm->vcpu, svm->msrpm, index,
918 !intercept, !intercept);
921 svm->x2avic_msrs_intercepted = intercept;
924 void svm_vcpu_free_msrpm(u32 *msrpm)
926 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
929 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
931 struct vcpu_svm *svm = to_svm(vcpu);
935 * Set intercept permissions for all direct access MSRs again. They
936 * will automatically get filtered through the MSR filter, so we are
937 * back in sync after this.
939 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
940 u32 msr = direct_access_msrs[i].index;
941 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
942 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
944 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
948 static void add_msr_offset(u32 offset)
952 for (i = 0; i < MSRPM_OFFSETS; ++i) {
954 /* Offset already in list? */
955 if (msrpm_offsets[i] == offset)
958 /* Slot used by another offset? */
959 if (msrpm_offsets[i] != MSR_INVALID)
962 /* Add offset to list */
963 msrpm_offsets[i] = offset;
969 * If this BUG triggers the msrpm_offsets table has an overflow. Just
970 * increase MSRPM_OFFSETS in this case.
975 static void init_msrpm_offsets(void)
979 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
981 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
984 offset = svm_msrpm_offset(direct_access_msrs[i].index);
985 BUG_ON(offset == MSR_INVALID);
987 add_msr_offset(offset);
991 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb)
993 to_vmcb->save.dbgctl = from_vmcb->save.dbgctl;
994 to_vmcb->save.br_from = from_vmcb->save.br_from;
995 to_vmcb->save.br_to = from_vmcb->save.br_to;
996 to_vmcb->save.last_excp_from = from_vmcb->save.last_excp_from;
997 to_vmcb->save.last_excp_to = from_vmcb->save.last_excp_to;
999 vmcb_mark_dirty(to_vmcb, VMCB_LBR);
1002 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
1004 struct vcpu_svm *svm = to_svm(vcpu);
1006 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
1007 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
1008 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
1009 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
1010 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
1012 /* Move the LBR msrs to the vmcb02 so that the guest can see them. */
1013 if (is_guest_mode(vcpu))
1014 svm_copy_lbrs(svm->vmcb, svm->vmcb01.ptr);
1017 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
1019 struct vcpu_svm *svm = to_svm(vcpu);
1021 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
1022 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
1023 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
1024 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
1025 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
1028 * Move the LBR msrs back to the vmcb01 to avoid copying them
1029 * on nested guest entries.
1031 if (is_guest_mode(vcpu))
1032 svm_copy_lbrs(svm->vmcb01.ptr, svm->vmcb);
1035 static struct vmcb *svm_get_lbr_vmcb(struct vcpu_svm *svm)
1038 * If LBR virtualization is disabled, the LBR MSRs are always kept in
1039 * vmcb01. If LBR virtualization is enabled and L1 is running VMs of
1040 * its own, the MSRs are moved between vmcb01 and vmcb02 as needed.
1042 return svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK ? svm->vmcb :
1046 void svm_update_lbrv(struct kvm_vcpu *vcpu)
1048 struct vcpu_svm *svm = to_svm(vcpu);
1049 bool current_enable_lbrv = svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK;
1050 bool enable_lbrv = (svm_get_lbr_vmcb(svm)->save.dbgctl & DEBUGCTLMSR_LBR) ||
1051 (is_guest_mode(vcpu) && guest_can_use(vcpu, X86_FEATURE_LBRV) &&
1052 (svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK));
1054 if (enable_lbrv == current_enable_lbrv)
1058 svm_enable_lbrv(vcpu);
1060 svm_disable_lbrv(vcpu);
1063 void disable_nmi_singlestep(struct vcpu_svm *svm)
1065 svm->nmi_singlestep = false;
1067 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1068 /* Clear our flags if they were not set by the guest */
1069 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1070 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1071 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1072 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1076 static void grow_ple_window(struct kvm_vcpu *vcpu)
1078 struct vcpu_svm *svm = to_svm(vcpu);
1079 struct vmcb_control_area *control = &svm->vmcb->control;
1080 int old = control->pause_filter_count;
1082 if (kvm_pause_in_guest(vcpu->kvm))
1085 control->pause_filter_count = __grow_ple_window(old,
1087 pause_filter_count_grow,
1088 pause_filter_count_max);
1090 if (control->pause_filter_count != old) {
1091 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1092 trace_kvm_ple_window_update(vcpu->vcpu_id,
1093 control->pause_filter_count, old);
1097 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1099 struct vcpu_svm *svm = to_svm(vcpu);
1100 struct vmcb_control_area *control = &svm->vmcb->control;
1101 int old = control->pause_filter_count;
1103 if (kvm_pause_in_guest(vcpu->kvm))
1106 control->pause_filter_count =
1107 __shrink_ple_window(old,
1109 pause_filter_count_shrink,
1110 pause_filter_count);
1111 if (control->pause_filter_count != old) {
1112 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1113 trace_kvm_ple_window_update(vcpu->vcpu_id,
1114 control->pause_filter_count, old);
1118 static void svm_hardware_unsetup(void)
1122 sev_hardware_unsetup();
1124 for_each_possible_cpu(cpu)
1125 svm_cpu_uninit(cpu);
1127 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
1128 get_order(IOPM_SIZE));
1132 static void init_seg(struct vmcb_seg *seg)
1135 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1136 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1137 seg->limit = 0xffff;
1141 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1144 seg->attrib = SVM_SELECTOR_P_MASK | type;
1145 seg->limit = 0xffff;
1149 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1151 struct vcpu_svm *svm = to_svm(vcpu);
1153 return svm->nested.ctl.tsc_offset;
1156 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1158 struct vcpu_svm *svm = to_svm(vcpu);
1160 return svm->tsc_ratio_msr;
1163 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu)
1165 struct vcpu_svm *svm = to_svm(vcpu);
1167 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1168 svm->vmcb->control.tsc_offset = vcpu->arch.tsc_offset;
1169 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1172 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu)
1175 if (to_svm(vcpu)->guest_state_loaded)
1176 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
1180 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1181 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1182 struct vcpu_svm *svm)
1185 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1186 * roots, or if INVPCID is disabled in the guest to inject #UD.
1188 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1190 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1191 svm_set_intercept(svm, INTERCEPT_INVPCID);
1193 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1196 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1197 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1198 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1200 svm_set_intercept(svm, INTERCEPT_RDTSCP);
1204 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
1206 struct vcpu_svm *svm = to_svm(vcpu);
1208 if (guest_cpuid_is_intel(vcpu)) {
1210 * We must intercept SYSENTER_EIP and SYSENTER_ESP
1211 * accesses because the processor only stores 32 bits.
1212 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
1214 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1215 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1216 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1218 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
1219 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
1222 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1223 * in VMCB and clear intercepts to avoid #VMEXIT.
1226 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1227 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1228 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1230 /* No need to intercept these MSRs */
1231 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
1232 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
1236 static void init_vmcb(struct kvm_vcpu *vcpu)
1238 struct vcpu_svm *svm = to_svm(vcpu);
1239 struct vmcb *vmcb = svm->vmcb01.ptr;
1240 struct vmcb_control_area *control = &vmcb->control;
1241 struct vmcb_save_area *save = &vmcb->save;
1243 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1244 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1245 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1246 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1247 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1248 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1249 if (!kvm_vcpu_apicv_active(vcpu))
1250 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1252 set_dr_intercepts(svm);
1254 set_exception_intercept(svm, PF_VECTOR);
1255 set_exception_intercept(svm, UD_VECTOR);
1256 set_exception_intercept(svm, MC_VECTOR);
1257 set_exception_intercept(svm, AC_VECTOR);
1258 set_exception_intercept(svm, DB_VECTOR);
1260 * Guest access to VMware backdoor ports could legitimately
1261 * trigger #GP because of TSS I/O permission bitmap.
1262 * We intercept those #GP and allow access to them anyway
1265 if (enable_vmware_backdoor)
1266 set_exception_intercept(svm, GP_VECTOR);
1268 svm_set_intercept(svm, INTERCEPT_INTR);
1269 svm_set_intercept(svm, INTERCEPT_NMI);
1272 svm_set_intercept(svm, INTERCEPT_SMI);
1274 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1275 svm_set_intercept(svm, INTERCEPT_RDPMC);
1276 svm_set_intercept(svm, INTERCEPT_CPUID);
1277 svm_set_intercept(svm, INTERCEPT_INVD);
1278 svm_set_intercept(svm, INTERCEPT_INVLPG);
1279 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1280 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1281 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1282 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1283 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1284 svm_set_intercept(svm, INTERCEPT_VMRUN);
1285 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1286 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1287 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1288 svm_set_intercept(svm, INTERCEPT_STGI);
1289 svm_set_intercept(svm, INTERCEPT_CLGI);
1290 svm_set_intercept(svm, INTERCEPT_SKINIT);
1291 svm_set_intercept(svm, INTERCEPT_WBINVD);
1292 svm_set_intercept(svm, INTERCEPT_XSETBV);
1293 svm_set_intercept(svm, INTERCEPT_RDPRU);
1294 svm_set_intercept(svm, INTERCEPT_RSM);
1296 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1297 svm_set_intercept(svm, INTERCEPT_MONITOR);
1298 svm_set_intercept(svm, INTERCEPT_MWAIT);
1301 if (!kvm_hlt_in_guest(vcpu->kvm))
1302 svm_set_intercept(svm, INTERCEPT_HLT);
1304 control->iopm_base_pa = __sme_set(iopm_base);
1305 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1306 control->int_ctl = V_INTR_MASKING_MASK;
1308 init_seg(&save->es);
1309 init_seg(&save->ss);
1310 init_seg(&save->ds);
1311 init_seg(&save->fs);
1312 init_seg(&save->gs);
1314 save->cs.selector = 0xf000;
1315 save->cs.base = 0xffff0000;
1316 /* Executable/Readable Code Segment */
1317 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1318 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1319 save->cs.limit = 0xffff;
1321 save->gdtr.base = 0;
1322 save->gdtr.limit = 0xffff;
1323 save->idtr.base = 0;
1324 save->idtr.limit = 0xffff;
1326 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1327 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1330 /* Setup VMCB for Nested Paging */
1331 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1332 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1333 clr_exception_intercept(svm, PF_VECTOR);
1334 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1335 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1336 save->g_pat = vcpu->arch.pat;
1339 svm->current_vmcb->asid_generation = 0;
1342 svm->nested.vmcb12_gpa = INVALID_GPA;
1343 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1345 if (!kvm_pause_in_guest(vcpu->kvm)) {
1346 control->pause_filter_count = pause_filter_count;
1347 if (pause_filter_thresh)
1348 control->pause_filter_thresh = pause_filter_thresh;
1349 svm_set_intercept(svm, INTERCEPT_PAUSE);
1351 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1354 svm_recalc_instruction_intercepts(vcpu, svm);
1357 * If the host supports V_SPEC_CTRL then disable the interception
1358 * of MSR_IA32_SPEC_CTRL.
1360 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1361 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1363 if (kvm_vcpu_apicv_active(vcpu))
1364 avic_init_vmcb(svm, vmcb);
1367 svm->vmcb->control.int_ctl |= V_NMI_ENABLE_MASK;
1370 svm_clr_intercept(svm, INTERCEPT_STGI);
1371 svm_clr_intercept(svm, INTERCEPT_CLGI);
1372 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1375 if (sev_guest(vcpu->kvm))
1378 svm_hv_init_vmcb(vmcb);
1379 init_vmcb_after_set_cpuid(vcpu);
1381 vmcb_mark_all_dirty(vmcb);
1386 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
1388 struct vcpu_svm *svm = to_svm(vcpu);
1390 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1392 svm_init_osvw(vcpu);
1393 vcpu->arch.microcode_version = 0x01000065;
1394 svm->tsc_ratio_msr = kvm_caps.default_tsc_scaling_ratio;
1396 svm->nmi_masked = false;
1397 svm->awaiting_iret_completion = false;
1399 if (sev_es_guest(vcpu->kvm))
1400 sev_es_vcpu_reset(svm);
1403 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1405 struct vcpu_svm *svm = to_svm(vcpu);
1408 svm->virt_spec_ctrl = 0;
1413 __svm_vcpu_reset(vcpu);
1416 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1418 svm->current_vmcb = target_vmcb;
1419 svm->vmcb = target_vmcb->ptr;
1422 static int svm_vcpu_create(struct kvm_vcpu *vcpu)
1424 struct vcpu_svm *svm;
1425 struct page *vmcb01_page;
1426 struct page *vmsa_page = NULL;
1429 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1433 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1437 if (sev_es_guest(vcpu->kvm)) {
1439 * SEV-ES guests require a separate VMSA page used to contain
1440 * the encrypted register state of the guest.
1442 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1444 goto error_free_vmcb_page;
1447 * SEV-ES guests maintain an encrypted version of their FPU
1448 * state which is restored and saved on VMRUN and VMEXIT.
1449 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't
1450 * do xsave/xrstor on it.
1452 fpstate_set_confidential(&vcpu->arch.guest_fpu);
1455 err = avic_init_vcpu(svm);
1457 goto error_free_vmsa_page;
1459 svm->msrpm = svm_vcpu_alloc_msrpm();
1462 goto error_free_vmsa_page;
1465 svm->x2avic_msrs_intercepted = true;
1467 svm->vmcb01.ptr = page_address(vmcb01_page);
1468 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1469 svm_switch_vmcb(svm, &svm->vmcb01);
1472 svm->sev_es.vmsa = page_address(vmsa_page);
1474 svm->guest_state_loaded = false;
1478 error_free_vmsa_page:
1480 __free_page(vmsa_page);
1481 error_free_vmcb_page:
1482 __free_page(vmcb01_page);
1487 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1491 for_each_online_cpu(i)
1492 cmpxchg(per_cpu_ptr(&svm_data.current_vmcb, i), vmcb, NULL);
1495 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
1497 struct vcpu_svm *svm = to_svm(vcpu);
1500 * The vmcb page can be recycled, causing a false negative in
1501 * svm_vcpu_load(). So, ensure that no logical CPU has this
1502 * vmcb page recorded as its current vmcb.
1504 svm_clear_current_vmcb(svm->vmcb);
1506 svm_leave_nested(vcpu);
1507 svm_free_nested(svm);
1509 sev_free_vcpu(vcpu);
1511 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1512 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1515 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1517 struct vcpu_svm *svm = to_svm(vcpu);
1518 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
1520 if (sev_es_guest(vcpu->kvm))
1521 sev_es_unmap_ghcb(svm);
1523 if (svm->guest_state_loaded)
1527 * Save additional host state that will be restored on VMEXIT (sev-es)
1528 * or subsequent vmload of host save area.
1530 vmsave(sd->save_area_pa);
1531 if (sev_es_guest(vcpu->kvm)) {
1532 struct sev_es_save_area *hostsa;
1533 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
1535 sev_es_prepare_switch_to_guest(hostsa);
1539 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
1542 * TSC_AUX is always virtualized for SEV-ES guests when the feature is
1543 * available. The user return MSR support is not required in this case
1544 * because TSC_AUX is restored on #VMEXIT from the host save area
1545 * (which has been initialized in svm_hardware_enable()).
1547 if (likely(tsc_aux_uret_slot >= 0) &&
1548 (!boot_cpu_has(X86_FEATURE_V_TSC_AUX) || !sev_es_guest(vcpu->kvm)))
1549 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1551 svm->guest_state_loaded = true;
1554 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1556 to_svm(vcpu)->guest_state_loaded = false;
1559 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1561 struct vcpu_svm *svm = to_svm(vcpu);
1562 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, cpu);
1564 if (sd->current_vmcb != svm->vmcb) {
1565 sd->current_vmcb = svm->vmcb;
1567 if (!cpu_feature_enabled(X86_FEATURE_IBPB_ON_VMEXIT))
1568 indirect_branch_prediction_barrier();
1570 if (kvm_vcpu_apicv_active(vcpu))
1571 avic_vcpu_load(vcpu, cpu);
1574 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1576 if (kvm_vcpu_apicv_active(vcpu))
1577 avic_vcpu_put(vcpu);
1579 svm_prepare_host_switch(vcpu);
1581 ++vcpu->stat.host_state_reload;
1584 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1586 struct vcpu_svm *svm = to_svm(vcpu);
1587 unsigned long rflags = svm->vmcb->save.rflags;
1589 if (svm->nmi_singlestep) {
1590 /* Hide our flags if they were not set by the guest */
1591 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1592 rflags &= ~X86_EFLAGS_TF;
1593 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1594 rflags &= ~X86_EFLAGS_RF;
1599 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1601 if (to_svm(vcpu)->nmi_singlestep)
1602 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1605 * Any change of EFLAGS.VM is accompanied by a reload of SS
1606 * (caused by either a task switch or an inter-privilege IRET),
1607 * so we do not need to update the CPL here.
1609 to_svm(vcpu)->vmcb->save.rflags = rflags;
1612 static bool svm_get_if_flag(struct kvm_vcpu *vcpu)
1614 struct vmcb *vmcb = to_svm(vcpu)->vmcb;
1616 return sev_es_guest(vcpu->kvm)
1617 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK
1618 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF;
1621 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1623 kvm_register_mark_available(vcpu, reg);
1626 case VCPU_EXREG_PDPTR:
1628 * When !npt_enabled, mmu->pdptrs[] is already available since
1629 * it is always updated per SDM when moving to CRs.
1632 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
1635 KVM_BUG_ON(1, vcpu->kvm);
1639 static void svm_set_vintr(struct vcpu_svm *svm)
1641 struct vmcb_control_area *control;
1644 * The following fields are ignored when AVIC is enabled
1646 WARN_ON(kvm_vcpu_apicv_activated(&svm->vcpu));
1648 svm_set_intercept(svm, INTERCEPT_VINTR);
1651 * Recalculating intercepts may have cleared the VINTR intercept. If
1652 * V_INTR_MASKING is enabled in vmcb12, then the effective RFLAGS.IF
1653 * for L1 physical interrupts is L1's RFLAGS.IF at the time of VMRUN.
1654 * Requesting an interrupt window if save.RFLAGS.IF=0 is pointless as
1655 * interrupts will never be unblocked while L2 is running.
1657 if (!svm_is_intercept(svm, INTERCEPT_VINTR))
1661 * This is just a dummy VINTR to actually cause a vmexit to happen.
1662 * Actual injection of virtual interrupts happens through EVENTINJ.
1664 control = &svm->vmcb->control;
1665 control->int_vector = 0x0;
1666 control->int_ctl &= ~V_INTR_PRIO_MASK;
1667 control->int_ctl |= V_IRQ_MASK |
1668 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1669 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1672 static void svm_clear_vintr(struct vcpu_svm *svm)
1674 svm_clr_intercept(svm, INTERCEPT_VINTR);
1676 /* Drop int_ctl fields related to VINTR injection. */
1677 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1678 if (is_guest_mode(&svm->vcpu)) {
1679 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1681 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1682 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1684 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1685 V_IRQ_INJECTION_BITS_MASK;
1687 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1690 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1693 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1695 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1696 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1699 case VCPU_SREG_CS: return &save->cs;
1700 case VCPU_SREG_DS: return &save->ds;
1701 case VCPU_SREG_ES: return &save->es;
1702 case VCPU_SREG_FS: return &save01->fs;
1703 case VCPU_SREG_GS: return &save01->gs;
1704 case VCPU_SREG_SS: return &save->ss;
1705 case VCPU_SREG_TR: return &save01->tr;
1706 case VCPU_SREG_LDTR: return &save01->ldtr;
1712 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1714 struct vmcb_seg *s = svm_seg(vcpu, seg);
1719 static void svm_get_segment(struct kvm_vcpu *vcpu,
1720 struct kvm_segment *var, int seg)
1722 struct vmcb_seg *s = svm_seg(vcpu, seg);
1724 var->base = s->base;
1725 var->limit = s->limit;
1726 var->selector = s->selector;
1727 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1728 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1729 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1730 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1731 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1732 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1733 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1736 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1737 * However, the SVM spec states that the G bit is not observed by the
1738 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1739 * So let's synthesize a legal G bit for all segments, this helps
1740 * running KVM nested. It also helps cross-vendor migration, because
1741 * Intel's vmentry has a check on the 'G' bit.
1743 var->g = s->limit > 0xfffff;
1746 * AMD's VMCB does not have an explicit unusable field, so emulate it
1747 * for cross vendor migration purposes by "not present"
1749 var->unusable = !var->present;
1754 * Work around a bug where the busy flag in the tr selector
1764 * The accessed bit must always be set in the segment
1765 * descriptor cache, although it can be cleared in the
1766 * descriptor, the cached bit always remains at 1. Since
1767 * Intel has a check on this, set it here to support
1768 * cross-vendor migration.
1775 * On AMD CPUs sometimes the DB bit in the segment
1776 * descriptor is left as 1, although the whole segment has
1777 * been made unusable. Clear it here to pass an Intel VMX
1778 * entry check when cross vendor migrating.
1782 /* This is symmetric with svm_set_segment() */
1783 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1788 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1790 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1795 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1797 struct kvm_segment cs;
1799 svm_get_segment(vcpu, &cs, VCPU_SREG_CS);
1804 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1806 struct vcpu_svm *svm = to_svm(vcpu);
1808 dt->size = svm->vmcb->save.idtr.limit;
1809 dt->address = svm->vmcb->save.idtr.base;
1812 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1814 struct vcpu_svm *svm = to_svm(vcpu);
1816 svm->vmcb->save.idtr.limit = dt->size;
1817 svm->vmcb->save.idtr.base = dt->address ;
1818 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1821 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1823 struct vcpu_svm *svm = to_svm(vcpu);
1825 dt->size = svm->vmcb->save.gdtr.limit;
1826 dt->address = svm->vmcb->save.gdtr.base;
1829 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1831 struct vcpu_svm *svm = to_svm(vcpu);
1833 svm->vmcb->save.gdtr.limit = dt->size;
1834 svm->vmcb->save.gdtr.base = dt->address ;
1835 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1838 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1840 struct vcpu_svm *svm = to_svm(vcpu);
1843 * For guests that don't set guest_state_protected, the cr3 update is
1844 * handled via kvm_mmu_load() while entering the guest. For guests
1845 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to
1846 * VMCB save area now, since the save area will become the initial
1847 * contents of the VMSA, and future VMCB save area updates won't be
1850 if (sev_es_guest(vcpu->kvm)) {
1851 svm->vmcb->save.cr3 = cr3;
1852 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1856 static bool svm_is_valid_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1861 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1863 struct vcpu_svm *svm = to_svm(vcpu);
1865 bool old_paging = is_paging(vcpu);
1867 #ifdef CONFIG_X86_64
1868 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1869 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1870 vcpu->arch.efer |= EFER_LMA;
1871 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1874 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1875 vcpu->arch.efer &= ~EFER_LMA;
1876 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1880 vcpu->arch.cr0 = cr0;
1883 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1884 if (old_paging != is_paging(vcpu))
1885 svm_set_cr4(vcpu, kvm_read_cr4(vcpu));
1889 * re-enable caching here because the QEMU bios
1890 * does not do it - this results in some delay at
1893 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1894 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1896 svm->vmcb->save.cr0 = hcr0;
1897 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1900 * SEV-ES guests must always keep the CR intercepts cleared. CR
1901 * tracking is done using the CR write traps.
1903 if (sev_es_guest(vcpu->kvm))
1907 /* Selective CR0 write remains on. */
1908 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1909 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1911 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1912 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1916 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1921 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1923 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1924 unsigned long old_cr4 = vcpu->arch.cr4;
1926 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1927 svm_flush_tlb_current(vcpu);
1929 vcpu->arch.cr4 = cr4;
1933 if (!is_paging(vcpu))
1934 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
1936 cr4 |= host_cr4_mce;
1937 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1938 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1940 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1941 kvm_update_cpuid_runtime(vcpu);
1944 static void svm_set_segment(struct kvm_vcpu *vcpu,
1945 struct kvm_segment *var, int seg)
1947 struct vcpu_svm *svm = to_svm(vcpu);
1948 struct vmcb_seg *s = svm_seg(vcpu, seg);
1950 s->base = var->base;
1951 s->limit = var->limit;
1952 s->selector = var->selector;
1953 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1954 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1955 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1956 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1957 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1958 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1959 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1960 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1963 * This is always accurate, except if SYSRET returned to a segment
1964 * with SS.DPL != 3. Intel does not have this quirk, and always
1965 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1966 * would entail passing the CPL to userspace and back.
1968 if (seg == VCPU_SREG_SS)
1969 /* This is symmetric with svm_get_segment() */
1970 svm->vmcb->save.cpl = (var->dpl & 3);
1972 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1975 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1977 struct vcpu_svm *svm = to_svm(vcpu);
1979 clr_exception_intercept(svm, BP_VECTOR);
1981 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1982 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1983 set_exception_intercept(svm, BP_VECTOR);
1987 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1989 if (sd->next_asid > sd->max_asid) {
1990 ++sd->asid_generation;
1991 sd->next_asid = sd->min_asid;
1992 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1993 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1996 svm->current_vmcb->asid_generation = sd->asid_generation;
1997 svm->asid = sd->next_asid++;
2000 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
2002 struct vmcb *vmcb = svm->vmcb;
2004 if (svm->vcpu.arch.guest_state_protected)
2007 if (unlikely(value != vmcb->save.dr6)) {
2008 vmcb->save.dr6 = value;
2009 vmcb_mark_dirty(vmcb, VMCB_DR);
2013 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
2015 struct vcpu_svm *svm = to_svm(vcpu);
2017 if (WARN_ON_ONCE(sev_es_guest(vcpu->kvm)))
2020 get_debugreg(vcpu->arch.db[0], 0);
2021 get_debugreg(vcpu->arch.db[1], 1);
2022 get_debugreg(vcpu->arch.db[2], 2);
2023 get_debugreg(vcpu->arch.db[3], 3);
2025 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
2026 * because db_interception might need it. We can do it before vmentry.
2028 vcpu->arch.dr6 = svm->vmcb->save.dr6;
2029 vcpu->arch.dr7 = svm->vmcb->save.dr7;
2030 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
2031 set_dr_intercepts(svm);
2034 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
2036 struct vcpu_svm *svm = to_svm(vcpu);
2038 if (vcpu->arch.guest_state_protected)
2041 svm->vmcb->save.dr7 = value;
2042 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
2045 static int pf_interception(struct kvm_vcpu *vcpu)
2047 struct vcpu_svm *svm = to_svm(vcpu);
2049 u64 fault_address = svm->vmcb->control.exit_info_2;
2050 u64 error_code = svm->vmcb->control.exit_info_1;
2052 return kvm_handle_page_fault(vcpu, error_code, fault_address,
2053 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2054 svm->vmcb->control.insn_bytes : NULL,
2055 svm->vmcb->control.insn_len);
2058 static int npf_interception(struct kvm_vcpu *vcpu)
2060 struct vcpu_svm *svm = to_svm(vcpu);
2062 u64 fault_address = svm->vmcb->control.exit_info_2;
2063 u64 error_code = svm->vmcb->control.exit_info_1;
2065 trace_kvm_page_fault(vcpu, fault_address, error_code);
2066 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
2067 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
2068 svm->vmcb->control.insn_bytes : NULL,
2069 svm->vmcb->control.insn_len);
2072 static int db_interception(struct kvm_vcpu *vcpu)
2074 struct kvm_run *kvm_run = vcpu->run;
2075 struct vcpu_svm *svm = to_svm(vcpu);
2077 if (!(vcpu->guest_debug &
2078 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
2079 !svm->nmi_singlestep) {
2080 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
2081 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
2085 if (svm->nmi_singlestep) {
2086 disable_nmi_singlestep(svm);
2087 /* Make sure we check for pending NMIs upon entry */
2088 kvm_make_request(KVM_REQ_EVENT, vcpu);
2091 if (vcpu->guest_debug &
2092 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2093 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2094 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
2095 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
2096 kvm_run->debug.arch.pc =
2097 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2098 kvm_run->debug.arch.exception = DB_VECTOR;
2105 static int bp_interception(struct kvm_vcpu *vcpu)
2107 struct vcpu_svm *svm = to_svm(vcpu);
2108 struct kvm_run *kvm_run = vcpu->run;
2110 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2111 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2112 kvm_run->debug.arch.exception = BP_VECTOR;
2116 static int ud_interception(struct kvm_vcpu *vcpu)
2118 return handle_ud(vcpu);
2121 static int ac_interception(struct kvm_vcpu *vcpu)
2123 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
2127 static bool is_erratum_383(void)
2132 if (!erratum_383_found)
2135 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2139 /* Bit 62 may or may not be set for this mce */
2140 value &= ~(1ULL << 62);
2142 if (value != 0xb600000000010015ULL)
2145 /* Clear MCi_STATUS registers */
2146 for (i = 0; i < 6; ++i)
2147 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2149 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2153 value &= ~(1ULL << 2);
2154 low = lower_32_bits(value);
2155 high = upper_32_bits(value);
2157 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2160 /* Flush tlb to evict multi-match entries */
2166 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2168 if (is_erratum_383()) {
2170 * Erratum 383 triggered. Guest state is corrupt so kill the
2173 pr_err("Guest triggered AMD Erratum 383\n");
2175 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2181 * On an #MC intercept the MCE handler is not called automatically in
2182 * the host. So do it by hand here.
2184 kvm_machine_check();
2187 static int mc_interception(struct kvm_vcpu *vcpu)
2192 static int shutdown_interception(struct kvm_vcpu *vcpu)
2194 struct kvm_run *kvm_run = vcpu->run;
2195 struct vcpu_svm *svm = to_svm(vcpu);
2198 * The VM save area has already been encrypted so it
2199 * cannot be reinitialized - just terminate.
2201 if (sev_es_guest(vcpu->kvm))
2205 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
2206 * the VMCB in a known good state. Unfortuately, KVM doesn't have
2207 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2208 * userspace. At a platform view, INIT is acceptable behavior as
2209 * there exist bare metal platforms that automatically INIT the CPU
2210 * in response to shutdown.
2212 clear_page(svm->vmcb);
2213 kvm_vcpu_reset(vcpu, true);
2215 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2219 static int io_interception(struct kvm_vcpu *vcpu)
2221 struct vcpu_svm *svm = to_svm(vcpu);
2222 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2223 int size, in, string;
2226 ++vcpu->stat.io_exits;
2227 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2228 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2229 port = io_info >> 16;
2230 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2233 if (sev_es_guest(vcpu->kvm))
2234 return sev_es_string_io(svm, size, port, in);
2236 return kvm_emulate_instruction(vcpu, 0);
2239 svm->next_rip = svm->vmcb->control.exit_info_2;
2241 return kvm_fast_pio(vcpu, size, port, in);
2244 static int nmi_interception(struct kvm_vcpu *vcpu)
2249 static int smi_interception(struct kvm_vcpu *vcpu)
2254 static int intr_interception(struct kvm_vcpu *vcpu)
2256 ++vcpu->stat.irq_exits;
2260 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2262 struct vcpu_svm *svm = to_svm(vcpu);
2263 struct vmcb *vmcb12;
2264 struct kvm_host_map map;
2267 if (nested_svm_check_permissions(vcpu))
2270 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2273 kvm_inject_gp(vcpu, 0);
2279 ret = kvm_skip_emulated_instruction(vcpu);
2282 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2283 svm->sysenter_eip_hi = 0;
2284 svm->sysenter_esp_hi = 0;
2286 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2289 kvm_vcpu_unmap(vcpu, &map, true);
2294 static int vmload_interception(struct kvm_vcpu *vcpu)
2296 return vmload_vmsave_interception(vcpu, true);
2299 static int vmsave_interception(struct kvm_vcpu *vcpu)
2301 return vmload_vmsave_interception(vcpu, false);
2304 static int vmrun_interception(struct kvm_vcpu *vcpu)
2306 if (nested_svm_check_permissions(vcpu))
2309 return nested_svm_vmrun(vcpu);
2319 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2320 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2322 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2324 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2325 return NONE_SVM_INSTR;
2327 switch (ctxt->modrm) {
2328 case 0xd8: /* VMRUN */
2329 return SVM_INSTR_VMRUN;
2330 case 0xda: /* VMLOAD */
2331 return SVM_INSTR_VMLOAD;
2332 case 0xdb: /* VMSAVE */
2333 return SVM_INSTR_VMSAVE;
2338 return NONE_SVM_INSTR;
2341 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2343 const int guest_mode_exit_codes[] = {
2344 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2345 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2346 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2348 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2349 [SVM_INSTR_VMRUN] = vmrun_interception,
2350 [SVM_INSTR_VMLOAD] = vmload_interception,
2351 [SVM_INSTR_VMSAVE] = vmsave_interception,
2353 struct vcpu_svm *svm = to_svm(vcpu);
2356 if (is_guest_mode(vcpu)) {
2357 /* Returns '1' or -errno on failure, '0' on success. */
2358 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2363 return svm_instr_handlers[opcode](vcpu);
2367 * #GP handling code. Note that #GP can be triggered under the following two
2369 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2370 * some AMD CPUs when EAX of these instructions are in the reserved memory
2371 * regions (e.g. SMM memory on host).
2372 * 2) VMware backdoor
2374 static int gp_interception(struct kvm_vcpu *vcpu)
2376 struct vcpu_svm *svm = to_svm(vcpu);
2377 u32 error_code = svm->vmcb->control.exit_info_1;
2380 /* Both #GP cases have zero error_code */
2384 /* Decode the instruction for usage later */
2385 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2388 opcode = svm_instr_opcode(vcpu);
2390 if (opcode == NONE_SVM_INSTR) {
2391 if (!enable_vmware_backdoor)
2395 * VMware backdoor emulation on #GP interception only handles
2396 * IN{S}, OUT{S}, and RDPMC.
2398 if (!is_guest_mode(vcpu))
2399 return kvm_emulate_instruction(vcpu,
2400 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2402 /* All SVM instructions expect page aligned RAX */
2403 if (svm->vmcb->save.rax & ~PAGE_MASK)
2406 return emulate_svm_instr(vcpu, opcode);
2410 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2414 void svm_set_gif(struct vcpu_svm *svm, bool value)
2418 * If VGIF is enabled, the STGI intercept is only added to
2419 * detect the opening of the SMI/NMI window; remove it now.
2420 * Likewise, clear the VINTR intercept, we will set it
2421 * again while processing KVM_REQ_EVENT if needed.
2424 svm_clr_intercept(svm, INTERCEPT_STGI);
2425 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2426 svm_clear_vintr(svm);
2429 if (svm->vcpu.arch.smi_pending ||
2430 svm->vcpu.arch.nmi_pending ||
2431 kvm_cpu_has_injectable_intr(&svm->vcpu) ||
2432 kvm_apic_has_pending_init_or_sipi(&svm->vcpu))
2433 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2438 * After a CLGI no interrupts should come. But if vGIF is
2439 * in use, we still rely on the VINTR intercept (rather than
2440 * STGI) to detect an open interrupt window.
2443 svm_clear_vintr(svm);
2447 static int stgi_interception(struct kvm_vcpu *vcpu)
2451 if (nested_svm_check_permissions(vcpu))
2454 ret = kvm_skip_emulated_instruction(vcpu);
2455 svm_set_gif(to_svm(vcpu), true);
2459 static int clgi_interception(struct kvm_vcpu *vcpu)
2463 if (nested_svm_check_permissions(vcpu))
2466 ret = kvm_skip_emulated_instruction(vcpu);
2467 svm_set_gif(to_svm(vcpu), false);
2471 static int invlpga_interception(struct kvm_vcpu *vcpu)
2473 gva_t gva = kvm_rax_read(vcpu);
2474 u32 asid = kvm_rcx_read(vcpu);
2476 /* FIXME: Handle an address size prefix. */
2477 if (!is_long_mode(vcpu))
2480 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2482 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2483 kvm_mmu_invlpg(vcpu, gva);
2485 return kvm_skip_emulated_instruction(vcpu);
2488 static int skinit_interception(struct kvm_vcpu *vcpu)
2490 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2492 kvm_queue_exception(vcpu, UD_VECTOR);
2496 static int task_switch_interception(struct kvm_vcpu *vcpu)
2498 struct vcpu_svm *svm = to_svm(vcpu);
2501 int int_type = svm->vmcb->control.exit_int_info &
2502 SVM_EXITINTINFO_TYPE_MASK;
2503 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2505 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2507 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2508 bool has_error_code = false;
2511 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2513 if (svm->vmcb->control.exit_info_2 &
2514 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2515 reason = TASK_SWITCH_IRET;
2516 else if (svm->vmcb->control.exit_info_2 &
2517 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2518 reason = TASK_SWITCH_JMP;
2520 reason = TASK_SWITCH_GATE;
2522 reason = TASK_SWITCH_CALL;
2524 if (reason == TASK_SWITCH_GATE) {
2526 case SVM_EXITINTINFO_TYPE_NMI:
2527 vcpu->arch.nmi_injected = false;
2529 case SVM_EXITINTINFO_TYPE_EXEPT:
2530 if (svm->vmcb->control.exit_info_2 &
2531 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2532 has_error_code = true;
2534 (u32)svm->vmcb->control.exit_info_2;
2536 kvm_clear_exception_queue(vcpu);
2538 case SVM_EXITINTINFO_TYPE_INTR:
2539 case SVM_EXITINTINFO_TYPE_SOFT:
2540 kvm_clear_interrupt_queue(vcpu);
2547 if (reason != TASK_SWITCH_GATE ||
2548 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2549 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2550 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2551 if (!svm_skip_emulated_instruction(vcpu))
2555 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2558 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2559 has_error_code, error_code);
2562 static void svm_clr_iret_intercept(struct vcpu_svm *svm)
2564 if (!sev_es_guest(svm->vcpu.kvm))
2565 svm_clr_intercept(svm, INTERCEPT_IRET);
2568 static void svm_set_iret_intercept(struct vcpu_svm *svm)
2570 if (!sev_es_guest(svm->vcpu.kvm))
2571 svm_set_intercept(svm, INTERCEPT_IRET);
2574 static int iret_interception(struct kvm_vcpu *vcpu)
2576 struct vcpu_svm *svm = to_svm(vcpu);
2578 WARN_ON_ONCE(sev_es_guest(vcpu->kvm));
2580 ++vcpu->stat.nmi_window_exits;
2581 svm->awaiting_iret_completion = true;
2583 svm_clr_iret_intercept(svm);
2584 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2586 kvm_make_request(KVM_REQ_EVENT, vcpu);
2590 static int invlpg_interception(struct kvm_vcpu *vcpu)
2592 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2593 return kvm_emulate_instruction(vcpu, 0);
2595 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2596 return kvm_skip_emulated_instruction(vcpu);
2599 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2601 return kvm_emulate_instruction(vcpu, 0);
2604 static int rsm_interception(struct kvm_vcpu *vcpu)
2606 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2609 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2612 struct vcpu_svm *svm = to_svm(vcpu);
2613 unsigned long cr0 = vcpu->arch.cr0;
2616 if (!is_guest_mode(vcpu) ||
2617 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2620 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2621 val &= ~SVM_CR0_SELECTIVE_MASK;
2624 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2625 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2631 #define CR_VALID (1ULL << 63)
2633 static int cr_interception(struct kvm_vcpu *vcpu)
2635 struct vcpu_svm *svm = to_svm(vcpu);
2640 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2641 return emulate_on_interception(vcpu);
2643 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2644 return emulate_on_interception(vcpu);
2646 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2647 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2648 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2650 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2653 if (cr >= 16) { /* mov to cr */
2655 val = kvm_register_read(vcpu, reg);
2656 trace_kvm_cr_write(cr, val);
2659 if (!check_selective_cr0_intercepted(vcpu, val))
2660 err = kvm_set_cr0(vcpu, val);
2666 err = kvm_set_cr3(vcpu, val);
2669 err = kvm_set_cr4(vcpu, val);
2672 err = kvm_set_cr8(vcpu, val);
2675 WARN(1, "unhandled write to CR%d", cr);
2676 kvm_queue_exception(vcpu, UD_VECTOR);
2679 } else { /* mov from cr */
2682 val = kvm_read_cr0(vcpu);
2685 val = vcpu->arch.cr2;
2688 val = kvm_read_cr3(vcpu);
2691 val = kvm_read_cr4(vcpu);
2694 val = kvm_get_cr8(vcpu);
2697 WARN(1, "unhandled read from CR%d", cr);
2698 kvm_queue_exception(vcpu, UD_VECTOR);
2701 kvm_register_write(vcpu, reg, val);
2702 trace_kvm_cr_read(cr, val);
2704 return kvm_complete_insn_gp(vcpu, err);
2707 static int cr_trap(struct kvm_vcpu *vcpu)
2709 struct vcpu_svm *svm = to_svm(vcpu);
2710 unsigned long old_value, new_value;
2714 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2716 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2719 old_value = kvm_read_cr0(vcpu);
2720 svm_set_cr0(vcpu, new_value);
2722 kvm_post_set_cr0(vcpu, old_value, new_value);
2725 old_value = kvm_read_cr4(vcpu);
2726 svm_set_cr4(vcpu, new_value);
2728 kvm_post_set_cr4(vcpu, old_value, new_value);
2731 ret = kvm_set_cr8(vcpu, new_value);
2734 WARN(1, "unhandled CR%d write trap", cr);
2735 kvm_queue_exception(vcpu, UD_VECTOR);
2739 return kvm_complete_insn_gp(vcpu, ret);
2742 static int dr_interception(struct kvm_vcpu *vcpu)
2744 struct vcpu_svm *svm = to_svm(vcpu);
2750 * SEV-ES intercepts DR7 only to disable guest debugging and the guest issues a VMGEXIT
2751 * for DR7 write only. KVM cannot change DR7 (always swapped as type 'A') so return early.
2753 if (sev_es_guest(vcpu->kvm))
2756 if (vcpu->guest_debug == 0) {
2758 * No more DR vmexits; force a reload of the debug registers
2759 * and reenter on this instruction. The next vmexit will
2760 * retrieve the full state of the debug registers.
2762 clr_dr_intercepts(svm);
2763 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2767 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2768 return emulate_on_interception(vcpu);
2770 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2771 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2772 if (dr >= 16) { /* mov to DRn */
2774 val = kvm_register_read(vcpu, reg);
2775 err = kvm_set_dr(vcpu, dr, val);
2777 kvm_get_dr(vcpu, dr, &val);
2778 kvm_register_write(vcpu, reg, val);
2781 return kvm_complete_insn_gp(vcpu, err);
2784 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2788 u8 cr8_prev = kvm_get_cr8(vcpu);
2789 /* instruction emulation calls kvm_set_cr8() */
2790 r = cr_interception(vcpu);
2791 if (lapic_in_kernel(vcpu))
2793 if (cr8_prev <= kvm_get_cr8(vcpu))
2795 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2799 static int efer_trap(struct kvm_vcpu *vcpu)
2801 struct msr_data msr_info;
2805 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2806 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2807 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2808 * the guest doesn't have X86_FEATURE_SVM.
2810 msr_info.host_initiated = false;
2811 msr_info.index = MSR_EFER;
2812 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2813 ret = kvm_set_msr_common(vcpu, &msr_info);
2815 return kvm_complete_insn_gp(vcpu, ret);
2818 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2822 switch (msr->index) {
2823 case MSR_AMD64_DE_CFG:
2824 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
2825 msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
2828 return KVM_MSR_RET_INVALID;
2834 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2836 struct vcpu_svm *svm = to_svm(vcpu);
2838 switch (msr_info->index) {
2839 case MSR_AMD64_TSC_RATIO:
2840 if (!msr_info->host_initiated &&
2841 !guest_can_use(vcpu, X86_FEATURE_TSCRATEMSR))
2843 msr_info->data = svm->tsc_ratio_msr;
2846 msr_info->data = svm->vmcb01.ptr->save.star;
2848 #ifdef CONFIG_X86_64
2850 msr_info->data = svm->vmcb01.ptr->save.lstar;
2853 msr_info->data = svm->vmcb01.ptr->save.cstar;
2855 case MSR_KERNEL_GS_BASE:
2856 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2858 case MSR_SYSCALL_MASK:
2859 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2862 case MSR_IA32_SYSENTER_CS:
2863 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2865 case MSR_IA32_SYSENTER_EIP:
2866 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2867 if (guest_cpuid_is_intel(vcpu))
2868 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2870 case MSR_IA32_SYSENTER_ESP:
2871 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2872 if (guest_cpuid_is_intel(vcpu))
2873 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2876 msr_info->data = svm->tsc_aux;
2878 case MSR_IA32_DEBUGCTLMSR:
2879 msr_info->data = svm_get_lbr_vmcb(svm)->save.dbgctl;
2881 case MSR_IA32_LASTBRANCHFROMIP:
2882 msr_info->data = svm_get_lbr_vmcb(svm)->save.br_from;
2884 case MSR_IA32_LASTBRANCHTOIP:
2885 msr_info->data = svm_get_lbr_vmcb(svm)->save.br_to;
2887 case MSR_IA32_LASTINTFROMIP:
2888 msr_info->data = svm_get_lbr_vmcb(svm)->save.last_excp_from;
2890 case MSR_IA32_LASTINTTOIP:
2891 msr_info->data = svm_get_lbr_vmcb(svm)->save.last_excp_to;
2893 case MSR_VM_HSAVE_PA:
2894 msr_info->data = svm->nested.hsave_msr;
2897 msr_info->data = svm->nested.vm_cr_msr;
2899 case MSR_IA32_SPEC_CTRL:
2900 if (!msr_info->host_initiated &&
2901 !guest_has_spec_ctrl_msr(vcpu))
2904 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2905 msr_info->data = svm->vmcb->save.spec_ctrl;
2907 msr_info->data = svm->spec_ctrl;
2909 case MSR_AMD64_VIRT_SPEC_CTRL:
2910 if (!msr_info->host_initiated &&
2911 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2914 msr_info->data = svm->virt_spec_ctrl;
2916 case MSR_F15H_IC_CFG: {
2920 family = guest_cpuid_family(vcpu);
2921 model = guest_cpuid_model(vcpu);
2923 if (family < 0 || model < 0)
2924 return kvm_get_msr_common(vcpu, msr_info);
2928 if (family == 0x15 &&
2929 (model >= 0x2 && model < 0x20))
2930 msr_info->data = 0x1E;
2933 case MSR_AMD64_DE_CFG:
2934 msr_info->data = svm->msr_decfg;
2937 return kvm_get_msr_common(vcpu, msr_info);
2942 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2944 struct vcpu_svm *svm = to_svm(vcpu);
2945 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb))
2946 return kvm_complete_insn_gp(vcpu, err);
2948 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1);
2949 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
2951 SVM_EVTINJ_TYPE_EXEPT |
2956 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2958 struct vcpu_svm *svm = to_svm(vcpu);
2959 int svm_dis, chg_mask;
2961 if (data & ~SVM_VM_CR_VALID_MASK)
2964 chg_mask = SVM_VM_CR_VALID_MASK;
2966 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2967 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2969 svm->nested.vm_cr_msr &= ~chg_mask;
2970 svm->nested.vm_cr_msr |= (data & chg_mask);
2972 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2974 /* check for svm_disable while efer.svme is set */
2975 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2981 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2983 struct vcpu_svm *svm = to_svm(vcpu);
2986 u32 ecx = msr->index;
2987 u64 data = msr->data;
2989 case MSR_AMD64_TSC_RATIO:
2991 if (!guest_can_use(vcpu, X86_FEATURE_TSCRATEMSR)) {
2993 if (!msr->host_initiated)
2996 * In case TSC scaling is not enabled, always
2997 * leave this MSR at the default value.
2999 * Due to bug in qemu 6.2.0, it would try to set
3000 * this msr to 0 if tsc scaling is not enabled.
3001 * Ignore this value as well.
3003 if (data != 0 && data != svm->tsc_ratio_msr)
3008 if (data & SVM_TSC_RATIO_RSVD)
3011 svm->tsc_ratio_msr = data;
3013 if (guest_can_use(vcpu, X86_FEATURE_TSCRATEMSR) &&
3014 is_guest_mode(vcpu))
3015 nested_svm_update_tsc_ratio_msr(vcpu);
3018 case MSR_IA32_CR_PAT:
3019 ret = kvm_set_msr_common(vcpu, msr);
3023 svm->vmcb01.ptr->save.g_pat = data;
3024 if (is_guest_mode(vcpu))
3025 nested_vmcb02_compute_g_pat(svm);
3026 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3028 case MSR_IA32_SPEC_CTRL:
3029 if (!msr->host_initiated &&
3030 !guest_has_spec_ctrl_msr(vcpu))
3033 if (kvm_spec_ctrl_test_value(data))
3036 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3037 svm->vmcb->save.spec_ctrl = data;
3039 svm->spec_ctrl = data;
3045 * When it's written (to non-zero) for the first time, pass
3049 * The handling of the MSR bitmap for L2 guests is done in
3050 * nested_svm_vmrun_msrpm.
3051 * We update the L1 MSR bit as well since it will end up
3052 * touching the MSR anyway now.
3054 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
3056 case MSR_AMD64_VIRT_SPEC_CTRL:
3057 if (!msr->host_initiated &&
3058 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
3061 if (data & ~SPEC_CTRL_SSBD)
3064 svm->virt_spec_ctrl = data;
3067 svm->vmcb01.ptr->save.star = data;
3069 #ifdef CONFIG_X86_64
3071 svm->vmcb01.ptr->save.lstar = data;
3074 svm->vmcb01.ptr->save.cstar = data;
3076 case MSR_KERNEL_GS_BASE:
3077 svm->vmcb01.ptr->save.kernel_gs_base = data;
3079 case MSR_SYSCALL_MASK:
3080 svm->vmcb01.ptr->save.sfmask = data;
3083 case MSR_IA32_SYSENTER_CS:
3084 svm->vmcb01.ptr->save.sysenter_cs = data;
3086 case MSR_IA32_SYSENTER_EIP:
3087 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
3089 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
3090 * when we spoof an Intel vendor ID (for cross vendor migration).
3091 * In this case we use this intercept to track the high
3092 * 32 bit part of these msrs to support Intel's
3093 * implementation of SYSENTER/SYSEXIT.
3095 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
3097 case MSR_IA32_SYSENTER_ESP:
3098 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
3099 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
3103 * TSC_AUX is always virtualized for SEV-ES guests when the
3104 * feature is available. The user return MSR support is not
3105 * required in this case because TSC_AUX is restored on #VMEXIT
3106 * from the host save area (which has been initialized in
3107 * svm_hardware_enable()).
3109 if (boot_cpu_has(X86_FEATURE_V_TSC_AUX) && sev_es_guest(vcpu->kvm))
3113 * TSC_AUX is usually changed only during boot and never read
3114 * directly. Intercept TSC_AUX instead of exposing it to the
3115 * guest via direct_access_msrs, and switch it via user return.
3118 ret = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
3123 svm->tsc_aux = data;
3125 case MSR_IA32_DEBUGCTLMSR:
3127 kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
3130 if (data & DEBUGCTL_RESERVED_BITS)
3133 svm_get_lbr_vmcb(svm)->save.dbgctl = data;
3134 svm_update_lbrv(vcpu);
3136 case MSR_VM_HSAVE_PA:
3138 * Old kernels did not validate the value written to
3139 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
3140 * value to allow live migrating buggy or malicious guests
3141 * originating from those kernels.
3143 if (!msr->host_initiated && !page_address_valid(vcpu, data))
3146 svm->nested.hsave_msr = data & PAGE_MASK;
3149 return svm_set_vm_cr(vcpu, data);
3151 kvm_pr_unimpl_wrmsr(vcpu, ecx, data);
3153 case MSR_AMD64_DE_CFG: {
3154 struct kvm_msr_entry msr_entry;
3156 msr_entry.index = msr->index;
3157 if (svm_get_msr_feature(&msr_entry))
3160 /* Check the supported bits */
3161 if (data & ~msr_entry.data)
3164 /* Don't allow the guest to change a bit, #GP */
3165 if (!msr->host_initiated && (data ^ msr_entry.data))
3168 svm->msr_decfg = data;
3172 return kvm_set_msr_common(vcpu, msr);
3177 static int msr_interception(struct kvm_vcpu *vcpu)
3179 if (to_svm(vcpu)->vmcb->control.exit_info_1)
3180 return kvm_emulate_wrmsr(vcpu);
3182 return kvm_emulate_rdmsr(vcpu);
3185 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
3187 kvm_make_request(KVM_REQ_EVENT, vcpu);
3188 svm_clear_vintr(to_svm(vcpu));
3191 * If not running nested, for AVIC, the only reason to end up here is ExtINTs.
3192 * In this case AVIC was temporarily disabled for
3193 * requesting the IRQ window and we have to re-enable it.
3195 * If running nested, still remove the VM wide AVIC inhibit to
3196 * support case in which the interrupt window was requested when the
3197 * vCPU was not running nested.
3199 * All vCPUs which run still run nested, will remain to have their
3200 * AVIC still inhibited due to per-cpu AVIC inhibition.
3202 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3204 ++vcpu->stat.irq_window_exits;
3208 static int pause_interception(struct kvm_vcpu *vcpu)
3212 * CPL is not made available for an SEV-ES guest, therefore
3213 * vcpu->arch.preempted_in_kernel can never be true. Just
3214 * set in_kernel to false as well.
3216 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3218 grow_ple_window(vcpu);
3220 kvm_vcpu_on_spin(vcpu, in_kernel);
3221 return kvm_skip_emulated_instruction(vcpu);
3224 static int invpcid_interception(struct kvm_vcpu *vcpu)
3226 struct vcpu_svm *svm = to_svm(vcpu);
3230 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3231 kvm_queue_exception(vcpu, UD_VECTOR);
3236 * For an INVPCID intercept:
3237 * EXITINFO1 provides the linear address of the memory operand.
3238 * EXITINFO2 provides the contents of the register operand.
3240 type = svm->vmcb->control.exit_info_2;
3241 gva = svm->vmcb->control.exit_info_1;
3243 return kvm_handle_invpcid(vcpu, type, gva);
3246 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3247 [SVM_EXIT_READ_CR0] = cr_interception,
3248 [SVM_EXIT_READ_CR3] = cr_interception,
3249 [SVM_EXIT_READ_CR4] = cr_interception,
3250 [SVM_EXIT_READ_CR8] = cr_interception,
3251 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3252 [SVM_EXIT_WRITE_CR0] = cr_interception,
3253 [SVM_EXIT_WRITE_CR3] = cr_interception,
3254 [SVM_EXIT_WRITE_CR4] = cr_interception,
3255 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3256 [SVM_EXIT_READ_DR0] = dr_interception,
3257 [SVM_EXIT_READ_DR1] = dr_interception,
3258 [SVM_EXIT_READ_DR2] = dr_interception,
3259 [SVM_EXIT_READ_DR3] = dr_interception,
3260 [SVM_EXIT_READ_DR4] = dr_interception,
3261 [SVM_EXIT_READ_DR5] = dr_interception,
3262 [SVM_EXIT_READ_DR6] = dr_interception,
3263 [SVM_EXIT_READ_DR7] = dr_interception,
3264 [SVM_EXIT_WRITE_DR0] = dr_interception,
3265 [SVM_EXIT_WRITE_DR1] = dr_interception,
3266 [SVM_EXIT_WRITE_DR2] = dr_interception,
3267 [SVM_EXIT_WRITE_DR3] = dr_interception,
3268 [SVM_EXIT_WRITE_DR4] = dr_interception,
3269 [SVM_EXIT_WRITE_DR5] = dr_interception,
3270 [SVM_EXIT_WRITE_DR6] = dr_interception,
3271 [SVM_EXIT_WRITE_DR7] = dr_interception,
3272 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3273 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3274 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3275 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3276 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3277 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3278 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3279 [SVM_EXIT_INTR] = intr_interception,
3280 [SVM_EXIT_NMI] = nmi_interception,
3281 [SVM_EXIT_SMI] = smi_interception,
3282 [SVM_EXIT_VINTR] = interrupt_window_interception,
3283 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
3284 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
3285 [SVM_EXIT_IRET] = iret_interception,
3286 [SVM_EXIT_INVD] = kvm_emulate_invd,
3287 [SVM_EXIT_PAUSE] = pause_interception,
3288 [SVM_EXIT_HLT] = kvm_emulate_halt,
3289 [SVM_EXIT_INVLPG] = invlpg_interception,
3290 [SVM_EXIT_INVLPGA] = invlpga_interception,
3291 [SVM_EXIT_IOIO] = io_interception,
3292 [SVM_EXIT_MSR] = msr_interception,
3293 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3294 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3295 [SVM_EXIT_VMRUN] = vmrun_interception,
3296 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3297 [SVM_EXIT_VMLOAD] = vmload_interception,
3298 [SVM_EXIT_VMSAVE] = vmsave_interception,
3299 [SVM_EXIT_STGI] = stgi_interception,
3300 [SVM_EXIT_CLGI] = clgi_interception,
3301 [SVM_EXIT_SKINIT] = skinit_interception,
3302 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3303 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3304 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3305 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3306 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3307 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3308 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3309 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3310 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3311 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3312 [SVM_EXIT_INVPCID] = invpcid_interception,
3313 [SVM_EXIT_NPF] = npf_interception,
3314 [SVM_EXIT_RSM] = rsm_interception,
3315 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3316 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3317 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3320 static void dump_vmcb(struct kvm_vcpu *vcpu)
3322 struct vcpu_svm *svm = to_svm(vcpu);
3323 struct vmcb_control_area *control = &svm->vmcb->control;
3324 struct vmcb_save_area *save = &svm->vmcb->save;
3325 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3327 if (!dump_invalid_vmcb) {
3328 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3332 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3333 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3334 pr_err("VMCB Control Area:\n");
3335 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3336 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3337 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3338 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3339 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3340 pr_err("%-20s%08x %08x\n", "intercepts:",
3341 control->intercepts[INTERCEPT_WORD3],
3342 control->intercepts[INTERCEPT_WORD4]);
3343 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3344 pr_err("%-20s%d\n", "pause filter threshold:",
3345 control->pause_filter_thresh);
3346 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3347 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3348 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3349 pr_err("%-20s%d\n", "asid:", control->asid);
3350 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3351 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3352 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3353 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3354 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3355 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3356 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3357 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3358 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3359 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3360 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3361 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3362 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3363 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3364 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3365 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3366 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3367 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3368 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3369 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3370 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3371 pr_err("VMCB State Save Area:\n");
3372 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3374 save->es.selector, save->es.attrib,
3375 save->es.limit, save->es.base);
3376 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3378 save->cs.selector, save->cs.attrib,
3379 save->cs.limit, save->cs.base);
3380 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3382 save->ss.selector, save->ss.attrib,
3383 save->ss.limit, save->ss.base);
3384 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3386 save->ds.selector, save->ds.attrib,
3387 save->ds.limit, save->ds.base);
3388 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3390 save01->fs.selector, save01->fs.attrib,
3391 save01->fs.limit, save01->fs.base);
3392 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3394 save01->gs.selector, save01->gs.attrib,
3395 save01->gs.limit, save01->gs.base);
3396 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3398 save->gdtr.selector, save->gdtr.attrib,
3399 save->gdtr.limit, save->gdtr.base);
3400 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3402 save01->ldtr.selector, save01->ldtr.attrib,
3403 save01->ldtr.limit, save01->ldtr.base);
3404 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3406 save->idtr.selector, save->idtr.attrib,
3407 save->idtr.limit, save->idtr.base);
3408 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3410 save01->tr.selector, save01->tr.attrib,
3411 save01->tr.limit, save01->tr.base);
3412 pr_err("vmpl: %d cpl: %d efer: %016llx\n",
3413 save->vmpl, save->cpl, save->efer);
3414 pr_err("%-15s %016llx %-13s %016llx\n",
3415 "cr0:", save->cr0, "cr2:", save->cr2);
3416 pr_err("%-15s %016llx %-13s %016llx\n",
3417 "cr3:", save->cr3, "cr4:", save->cr4);
3418 pr_err("%-15s %016llx %-13s %016llx\n",
3419 "dr6:", save->dr6, "dr7:", save->dr7);
3420 pr_err("%-15s %016llx %-13s %016llx\n",
3421 "rip:", save->rip, "rflags:", save->rflags);
3422 pr_err("%-15s %016llx %-13s %016llx\n",
3423 "rsp:", save->rsp, "rax:", save->rax);
3424 pr_err("%-15s %016llx %-13s %016llx\n",
3425 "star:", save01->star, "lstar:", save01->lstar);
3426 pr_err("%-15s %016llx %-13s %016llx\n",
3427 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3428 pr_err("%-15s %016llx %-13s %016llx\n",
3429 "kernel_gs_base:", save01->kernel_gs_base,
3430 "sysenter_cs:", save01->sysenter_cs);
3431 pr_err("%-15s %016llx %-13s %016llx\n",
3432 "sysenter_esp:", save01->sysenter_esp,
3433 "sysenter_eip:", save01->sysenter_eip);
3434 pr_err("%-15s %016llx %-13s %016llx\n",
3435 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3436 pr_err("%-15s %016llx %-13s %016llx\n",
3437 "br_from:", save->br_from, "br_to:", save->br_to);
3438 pr_err("%-15s %016llx %-13s %016llx\n",
3439 "excp_from:", save->last_excp_from,
3440 "excp_to:", save->last_excp_to);
3443 static bool svm_check_exit_valid(u64 exit_code)
3445 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3446 svm_exit_handlers[exit_code]);
3449 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3451 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3453 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3454 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3455 vcpu->run->internal.ndata = 2;
3456 vcpu->run->internal.data[0] = exit_code;
3457 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3461 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3463 if (!svm_check_exit_valid(exit_code))
3464 return svm_handle_invalid_exit(vcpu, exit_code);
3466 #ifdef CONFIG_RETPOLINE
3467 if (exit_code == SVM_EXIT_MSR)
3468 return msr_interception(vcpu);
3469 else if (exit_code == SVM_EXIT_VINTR)
3470 return interrupt_window_interception(vcpu);
3471 else if (exit_code == SVM_EXIT_INTR)
3472 return intr_interception(vcpu);
3473 else if (exit_code == SVM_EXIT_HLT)
3474 return kvm_emulate_halt(vcpu);
3475 else if (exit_code == SVM_EXIT_NPF)
3476 return npf_interception(vcpu);
3478 return svm_exit_handlers[exit_code](vcpu);
3481 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
3482 u64 *info1, u64 *info2,
3483 u32 *intr_info, u32 *error_code)
3485 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3487 *reason = control->exit_code;
3488 *info1 = control->exit_info_1;
3489 *info2 = control->exit_info_2;
3490 *intr_info = control->exit_int_info;
3491 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3492 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3493 *error_code = control->exit_int_info_err;
3498 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3500 struct vcpu_svm *svm = to_svm(vcpu);
3501 struct kvm_run *kvm_run = vcpu->run;
3502 u32 exit_code = svm->vmcb->control.exit_code;
3504 /* SEV-ES guests must use the CR write traps to track CR registers. */
3505 if (!sev_es_guest(vcpu->kvm)) {
3506 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3507 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3509 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3512 if (is_guest_mode(vcpu)) {
3515 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM);
3517 vmexit = nested_svm_exit_special(svm);
3519 if (vmexit == NESTED_EXIT_CONTINUE)
3520 vmexit = nested_svm_exit_handled(svm);
3522 if (vmexit == NESTED_EXIT_DONE)
3526 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3527 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3528 kvm_run->fail_entry.hardware_entry_failure_reason
3529 = svm->vmcb->control.exit_code;
3530 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3535 if (exit_fastpath != EXIT_FASTPATH_NONE)
3538 return svm_invoke_exit_handler(vcpu, exit_code);
3541 static void pre_svm_run(struct kvm_vcpu *vcpu)
3543 struct svm_cpu_data *sd = per_cpu_ptr(&svm_data, vcpu->cpu);
3544 struct vcpu_svm *svm = to_svm(vcpu);
3547 * If the previous vmrun of the vmcb occurred on a different physical
3548 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3549 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3551 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3552 svm->current_vmcb->asid_generation = 0;
3553 vmcb_mark_all_dirty(svm->vmcb);
3554 svm->current_vmcb->cpu = vcpu->cpu;
3557 if (sev_guest(vcpu->kvm))
3558 return pre_sev_run(svm, vcpu->cpu);
3560 /* FIXME: handle wraparound of asid_generation */
3561 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3565 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3567 struct vcpu_svm *svm = to_svm(vcpu);
3569 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3571 if (svm->nmi_l1_to_l2)
3574 svm->nmi_masked = true;
3575 svm_set_iret_intercept(svm);
3576 ++vcpu->stat.nmi_injections;
3579 static bool svm_is_vnmi_pending(struct kvm_vcpu *vcpu)
3581 struct vcpu_svm *svm = to_svm(vcpu);
3583 if (!is_vnmi_enabled(svm))
3586 return !!(svm->vmcb->control.int_ctl & V_NMI_PENDING_MASK);
3589 static bool svm_set_vnmi_pending(struct kvm_vcpu *vcpu)
3591 struct vcpu_svm *svm = to_svm(vcpu);
3593 if (!is_vnmi_enabled(svm))
3596 if (svm->vmcb->control.int_ctl & V_NMI_PENDING_MASK)
3599 svm->vmcb->control.int_ctl |= V_NMI_PENDING_MASK;
3600 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
3603 * Because the pending NMI is serviced by hardware, KVM can't know when
3604 * the NMI is "injected", but for all intents and purposes, passing the
3605 * NMI off to hardware counts as injection.
3607 ++vcpu->stat.nmi_injections;
3612 static void svm_inject_irq(struct kvm_vcpu *vcpu, bool reinjected)
3614 struct vcpu_svm *svm = to_svm(vcpu);
3617 if (vcpu->arch.interrupt.soft) {
3618 if (svm_update_soft_interrupt_rip(vcpu))
3621 type = SVM_EVTINJ_TYPE_SOFT;
3623 type = SVM_EVTINJ_TYPE_INTR;
3626 trace_kvm_inj_virq(vcpu->arch.interrupt.nr,
3627 vcpu->arch.interrupt.soft, reinjected);
3628 ++vcpu->stat.irq_injections;
3630 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3631 SVM_EVTINJ_VALID | type;
3634 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
3635 int trig_mode, int vector)
3638 * apic->apicv_active must be read after vcpu->mode.
3639 * Pairs with smp_store_release in vcpu_enter_guest.
3641 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
3643 /* Note, this is called iff the local APIC is in-kernel. */
3644 if (!READ_ONCE(vcpu->arch.apic->apicv_active)) {
3645 /* Process the interrupt via kvm_check_and_inject_events(). */
3646 kvm_make_request(KVM_REQ_EVENT, vcpu);
3647 kvm_vcpu_kick(vcpu);
3651 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector);
3652 if (in_guest_mode) {
3654 * Signal the doorbell to tell hardware to inject the IRQ. If
3655 * the vCPU exits the guest before the doorbell chimes, hardware
3656 * will automatically process AVIC interrupts at the next VMRUN.
3658 avic_ring_doorbell(vcpu);
3661 * Wake the vCPU if it was blocking. KVM will then detect the
3662 * pending IRQ when checking if the vCPU has a wake event.
3664 kvm_vcpu_wake_up(vcpu);
3668 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3669 int trig_mode, int vector)
3671 kvm_lapic_set_irr(vector, apic);
3674 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in
3675 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before
3676 * the read of guest_mode. This guarantees that either VMRUN will see
3677 * and process the new vIRR entry, or that svm_complete_interrupt_delivery
3678 * will signal the doorbell if the CPU has already entered the guest.
3680 smp_mb__after_atomic();
3681 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);
3684 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3686 struct vcpu_svm *svm = to_svm(vcpu);
3689 * SEV-ES guests must always keep the CR intercepts cleared. CR
3690 * tracking is done using the CR write traps.
3692 if (sev_es_guest(vcpu->kvm))
3695 if (nested_svm_virtualize_tpr(vcpu))
3698 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3704 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3707 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3709 struct vcpu_svm *svm = to_svm(vcpu);
3711 if (is_vnmi_enabled(svm))
3712 return svm->vmcb->control.int_ctl & V_NMI_BLOCKING_MASK;
3714 return svm->nmi_masked;
3717 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3719 struct vcpu_svm *svm = to_svm(vcpu);
3721 if (is_vnmi_enabled(svm)) {
3723 svm->vmcb->control.int_ctl |= V_NMI_BLOCKING_MASK;
3725 svm->vmcb->control.int_ctl &= ~V_NMI_BLOCKING_MASK;
3728 svm->nmi_masked = masked;
3730 svm_set_iret_intercept(svm);
3732 svm_clr_iret_intercept(svm);
3736 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3738 struct vcpu_svm *svm = to_svm(vcpu);
3739 struct vmcb *vmcb = svm->vmcb;
3744 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3747 if (svm_get_nmi_mask(vcpu))
3750 return vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK;
3753 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3755 struct vcpu_svm *svm = to_svm(vcpu);
3756 if (svm->nested.nested_run_pending)
3759 if (svm_nmi_blocked(vcpu))
3762 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3763 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3768 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3770 struct vcpu_svm *svm = to_svm(vcpu);
3771 struct vmcb *vmcb = svm->vmcb;
3776 if (is_guest_mode(vcpu)) {
3777 /* As long as interrupts are being delivered... */
3778 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3779 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3780 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3783 /* ... vmexits aren't blocked by the interrupt shadow */
3784 if (nested_exit_on_intr(svm))
3787 if (!svm_get_if_flag(vcpu))
3791 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3794 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3796 struct vcpu_svm *svm = to_svm(vcpu);
3798 if (svm->nested.nested_run_pending)
3801 if (svm_interrupt_blocked(vcpu))
3805 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3806 * e.g. if the IRQ arrived asynchronously after checking nested events.
3808 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3814 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3816 struct vcpu_svm *svm = to_svm(vcpu);
3819 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3820 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3821 * get that intercept, this function will be called again though and
3822 * we'll get the vintr intercept. However, if the vGIF feature is
3823 * enabled, the STGI interception will not occur. Enable the irq
3824 * window under the assumption that the hardware will set the GIF.
3826 if (vgif || gif_set(svm)) {
3828 * IRQ window is not needed when AVIC is enabled,
3829 * unless we have pending ExtINT since it cannot be injected
3830 * via AVIC. In such case, KVM needs to temporarily disable AVIC,
3831 * and fallback to injecting IRQ via V_IRQ.
3833 * If running nested, AVIC is already locally inhibited
3834 * on this vCPU, therefore there is no need to request
3835 * the VM wide AVIC inhibition.
3837 if (!is_guest_mode(vcpu))
3838 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3844 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3846 struct vcpu_svm *svm = to_svm(vcpu);
3849 * KVM should never request an NMI window when vNMI is enabled, as KVM
3850 * allows at most one to-be-injected NMI and one pending NMI, i.e. if
3851 * two NMIs arrive simultaneously, KVM will inject one and set
3852 * V_NMI_PENDING for the other. WARN, but continue with the standard
3853 * single-step approach to try and salvage the pending NMI.
3855 WARN_ON_ONCE(is_vnmi_enabled(svm));
3857 if (svm_get_nmi_mask(vcpu) && !svm->awaiting_iret_completion)
3858 return; /* IRET will cause a vm exit */
3861 * SEV-ES guests are responsible for signaling when a vCPU is ready to
3862 * receive a new NMI, as SEV-ES guests can't be single-stepped, i.e.
3863 * KVM can't intercept and single-step IRET to detect when NMIs are
3864 * unblocked (architecturally speaking). See SVM_VMGEXIT_NMI_COMPLETE.
3866 * Note, GIF is guaranteed to be '1' for SEV-ES guests as hardware
3867 * ignores SEV-ES guest writes to EFER.SVME *and* CLGI/STGI are not
3868 * supported NAEs in the GHCB protocol.
3870 if (sev_es_guest(vcpu->kvm))
3873 if (!gif_set(svm)) {
3875 svm_set_intercept(svm, INTERCEPT_STGI);
3876 return; /* STGI will cause a vm exit */
3880 * Something prevents NMI from been injected. Single step over possible
3881 * problem (IRET or exception injection or interrupt shadow)
3883 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3884 svm->nmi_singlestep = true;
3885 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3888 static void svm_flush_tlb_asid(struct kvm_vcpu *vcpu)
3890 struct vcpu_svm *svm = to_svm(vcpu);
3893 * Unlike VMX, SVM doesn't provide a way to flush only NPT TLB entries.
3894 * A TLB flush for the current ASID flushes both "host" and "guest" TLB
3895 * entries, and thus is a superset of Hyper-V's fine grained flushing.
3897 kvm_hv_vcpu_purge_flush_tlb(vcpu);
3900 * Flush only the current ASID even if the TLB flush was invoked via
3901 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3902 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3903 * unconditionally does a TLB flush on both nested VM-Enter and nested
3904 * VM-Exit (via kvm_mmu_reset_context()).
3906 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3907 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3909 svm->current_vmcb->asid_generation--;
3912 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu)
3914 hpa_t root_tdp = vcpu->arch.mmu->root.hpa;
3917 * When running on Hyper-V with EnlightenedNptTlb enabled, explicitly
3918 * flush the NPT mappings via hypercall as flushing the ASID only
3919 * affects virtual to physical mappings, it does not invalidate guest
3920 * physical to host physical mappings.
3922 if (svm_hv_is_enlightened_tlb_enabled(vcpu) && VALID_PAGE(root_tdp))
3923 hyperv_flush_guest_mapping(root_tdp);
3925 svm_flush_tlb_asid(vcpu);
3928 static void svm_flush_tlb_all(struct kvm_vcpu *vcpu)
3931 * When running on Hyper-V with EnlightenedNptTlb enabled, remote TLB
3932 * flushes should be routed to hv_flush_remote_tlbs() without requesting
3933 * a "regular" remote flush. Reaching this point means either there's
3934 * a KVM bug or a prior hv_flush_remote_tlbs() call failed, both of
3935 * which might be fatal to the guest. Yell, but try to recover.
3937 if (WARN_ON_ONCE(svm_hv_is_enlightened_tlb_enabled(vcpu)))
3938 hv_flush_remote_tlbs(vcpu->kvm);
3940 svm_flush_tlb_asid(vcpu);
3943 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3945 struct vcpu_svm *svm = to_svm(vcpu);
3947 invlpga(gva, svm->vmcb->control.asid);
3950 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3952 struct vcpu_svm *svm = to_svm(vcpu);
3954 if (nested_svm_virtualize_tpr(vcpu))
3957 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3958 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3959 kvm_set_cr8(vcpu, cr8);
3963 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3965 struct vcpu_svm *svm = to_svm(vcpu);
3968 if (nested_svm_virtualize_tpr(vcpu) ||
3969 kvm_vcpu_apicv_active(vcpu))
3972 cr8 = kvm_get_cr8(vcpu);
3973 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3974 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3977 static void svm_complete_soft_interrupt(struct kvm_vcpu *vcpu, u8 vector,
3980 bool is_exception = (type == SVM_EXITINTINFO_TYPE_EXEPT);
3981 bool is_soft = (type == SVM_EXITINTINFO_TYPE_SOFT);
3982 struct vcpu_svm *svm = to_svm(vcpu);
3985 * If NRIPS is enabled, KVM must snapshot the pre-VMRUN next_rip that's
3986 * associated with the original soft exception/interrupt. next_rip is
3987 * cleared on all exits that can occur while vectoring an event, so KVM
3988 * needs to manually set next_rip for re-injection. Unlike the !nrips
3989 * case below, this needs to be done if and only if KVM is re-injecting
3990 * the same event, i.e. if the event is a soft exception/interrupt,
3991 * otherwise next_rip is unused on VMRUN.
3993 if (nrips && (is_soft || (is_exception && kvm_exception_is_soft(vector))) &&
3994 kvm_is_linear_rip(vcpu, svm->soft_int_old_rip + svm->soft_int_csbase))
3995 svm->vmcb->control.next_rip = svm->soft_int_next_rip;
3997 * If NRIPS isn't enabled, KVM must manually advance RIP prior to
3998 * injecting the soft exception/interrupt. That advancement needs to
3999 * be unwound if vectoring didn't complete. Note, the new event may
4000 * not be the injected event, e.g. if KVM injected an INTn, the INTn
4001 * hit a #NP in the guest, and the #NP encountered a #PF, the #NP will
4002 * be the reported vectored event, but RIP still needs to be unwound.
4004 else if (!nrips && (is_soft || is_exception) &&
4005 kvm_is_linear_rip(vcpu, svm->soft_int_next_rip + svm->soft_int_csbase))
4006 kvm_rip_write(vcpu, svm->soft_int_old_rip);
4009 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
4011 struct vcpu_svm *svm = to_svm(vcpu);
4014 u32 exitintinfo = svm->vmcb->control.exit_int_info;
4015 bool nmi_l1_to_l2 = svm->nmi_l1_to_l2;
4016 bool soft_int_injected = svm->soft_int_injected;
4018 svm->nmi_l1_to_l2 = false;
4019 svm->soft_int_injected = false;
4022 * If we've made progress since setting awaiting_iret_completion, we've
4023 * executed an IRET and can allow NMI injection.
4025 if (svm->awaiting_iret_completion &&
4026 kvm_rip_read(vcpu) != svm->nmi_iret_rip) {
4027 svm->awaiting_iret_completion = false;
4028 svm->nmi_masked = false;
4029 kvm_make_request(KVM_REQ_EVENT, vcpu);
4032 vcpu->arch.nmi_injected = false;
4033 kvm_clear_exception_queue(vcpu);
4034 kvm_clear_interrupt_queue(vcpu);
4036 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
4039 kvm_make_request(KVM_REQ_EVENT, vcpu);
4041 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
4042 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
4044 if (soft_int_injected)
4045 svm_complete_soft_interrupt(vcpu, vector, type);
4048 case SVM_EXITINTINFO_TYPE_NMI:
4049 vcpu->arch.nmi_injected = true;
4050 svm->nmi_l1_to_l2 = nmi_l1_to_l2;
4052 case SVM_EXITINTINFO_TYPE_EXEPT:
4054 * Never re-inject a #VC exception.
4056 if (vector == X86_TRAP_VC)
4059 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
4060 u32 err = svm->vmcb->control.exit_int_info_err;
4061 kvm_requeue_exception_e(vcpu, vector, err);
4064 kvm_requeue_exception(vcpu, vector);
4066 case SVM_EXITINTINFO_TYPE_INTR:
4067 kvm_queue_interrupt(vcpu, vector, false);
4069 case SVM_EXITINTINFO_TYPE_SOFT:
4070 kvm_queue_interrupt(vcpu, vector, true);
4078 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
4080 struct vcpu_svm *svm = to_svm(vcpu);
4081 struct vmcb_control_area *control = &svm->vmcb->control;
4083 control->exit_int_info = control->event_inj;
4084 control->exit_int_info_err = control->event_inj_err;
4085 control->event_inj = 0;
4086 svm_complete_interrupts(vcpu);
4089 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu)
4094 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
4096 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
4097 to_svm(vcpu)->vmcb->control.exit_info_1)
4098 return handle_fastpath_set_msr_irqoff(vcpu);
4100 return EXIT_FASTPATH_NONE;
4103 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu, bool spec_ctrl_intercepted)
4105 struct vcpu_svm *svm = to_svm(vcpu);
4107 guest_state_enter_irqoff();
4109 amd_clear_divider();
4111 if (sev_es_guest(vcpu->kvm))
4112 __svm_sev_es_vcpu_run(svm, spec_ctrl_intercepted);
4114 __svm_vcpu_run(svm, spec_ctrl_intercepted);
4116 guest_state_exit_irqoff();
4119 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
4121 struct vcpu_svm *svm = to_svm(vcpu);
4122 bool spec_ctrl_intercepted = msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL);
4124 trace_kvm_entry(vcpu);
4126 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4127 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4128 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4131 * Disable singlestep if we're injecting an interrupt/exception.
4132 * We don't want our modified rflags to be pushed on the stack where
4133 * we might not be able to easily reset them if we disabled NMI
4136 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
4138 * Event injection happens before external interrupts cause a
4139 * vmexit and interrupts are disabled here, so smp_send_reschedule
4140 * is enough to force an immediate vmexit.
4142 disable_nmi_singlestep(svm);
4143 smp_send_reschedule(vcpu->cpu);
4148 sync_lapic_to_cr8(vcpu);
4150 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
4151 svm->vmcb->control.asid = svm->asid;
4152 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
4154 svm->vmcb->save.cr2 = vcpu->arch.cr2;
4156 svm_hv_update_vp_id(svm->vmcb, vcpu);
4159 * Run with all-zero DR6 unless needed, so that we can get the exact cause
4162 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
4163 svm_set_dr6(svm, vcpu->arch.dr6);
4165 svm_set_dr6(svm, DR6_ACTIVE_LOW);
4168 kvm_load_guest_xsave_state(vcpu);
4170 kvm_wait_lapic_expire(vcpu);
4173 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
4174 * it's non-zero. Since vmentry is serialising on affected CPUs, there
4175 * is no need to worry about the conditional branch over the wrmsr
4176 * being speculatively taken.
4178 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4179 x86_spec_ctrl_set_guest(svm->virt_spec_ctrl);
4181 svm_vcpu_enter_exit(vcpu, spec_ctrl_intercepted);
4183 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4184 x86_spec_ctrl_restore_host(svm->virt_spec_ctrl);
4186 if (!sev_es_guest(vcpu->kvm)) {
4187 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4188 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4189 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4190 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4192 vcpu->arch.regs_dirty = 0;
4194 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4195 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI);
4197 kvm_load_host_xsave_state(vcpu);
4200 /* Any pending NMI will happen here */
4202 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4203 kvm_after_interrupt(vcpu);
4205 sync_cr8_to_lapic(vcpu);
4208 if (is_guest_mode(vcpu)) {
4209 nested_sync_control_from_vmcb02(svm);
4211 /* Track VMRUNs that have made past consistency checking */
4212 if (svm->nested.nested_run_pending &&
4213 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
4214 ++vcpu->stat.nested_run;
4216 svm->nested.nested_run_pending = 0;
4219 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4220 vmcb_mark_all_clean(svm->vmcb);
4222 /* if exit due to PF check for async PF */
4223 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4224 vcpu->arch.apf.host_apf_flags =
4225 kvm_read_and_reset_apf_flags();
4227 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET;
4230 * We need to handle MC intercepts here before the vcpu has a chance to
4231 * change the physical cpu
4233 if (unlikely(svm->vmcb->control.exit_code ==
4234 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4235 svm_handle_mce(vcpu);
4237 trace_kvm_exit(vcpu, KVM_ISA_SVM);
4239 svm_complete_interrupts(vcpu);
4241 if (is_guest_mode(vcpu))
4242 return EXIT_FASTPATH_NONE;
4244 return svm_exit_handlers_fastpath(vcpu);
4247 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
4250 struct vcpu_svm *svm = to_svm(vcpu);
4254 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
4255 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
4257 hv_track_root_tdp(vcpu, root_hpa);
4259 cr3 = vcpu->arch.cr3;
4260 } else if (root_level >= PT64_ROOT_4LEVEL) {
4261 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
4263 /* PCID in the guest should be impossible with a 32-bit MMU. */
4264 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
4268 svm->vmcb->save.cr3 = cr3;
4269 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
4273 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4276 * Patch in the VMMCALL instruction:
4278 hypercall[0] = 0x0f;
4279 hypercall[1] = 0x01;
4280 hypercall[2] = 0xd9;
4284 * The kvm parameter can be NULL (module initialization, or invocation before
4285 * VM creation). Be sure to check the kvm parameter before using it.
4287 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4290 case MSR_IA32_MCG_EXT_CTL:
4291 case KVM_FIRST_EMULATED_VMX_MSR ... KVM_LAST_EMULATED_VMX_MSR:
4293 case MSR_IA32_SMBASE:
4294 if (!IS_ENABLED(CONFIG_KVM_SMM))
4296 /* SEV-ES guests do not support SMM, so report false */
4297 if (kvm && sev_es_guest(kvm))
4307 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4309 struct vcpu_svm *svm = to_svm(vcpu);
4312 * SVM doesn't provide a way to disable just XSAVES in the guest, KVM
4313 * can only disable all variants of by disallowing CR4.OSXSAVE from
4314 * being set. As a result, if the host has XSAVE and XSAVES, and the
4315 * guest has XSAVE enabled, the guest can execute XSAVES without
4316 * faulting. Treat XSAVES as enabled in this case regardless of
4317 * whether it's advertised to the guest so that KVM context switches
4318 * XSS on VM-Enter/VM-Exit. Failure to do so would effectively give
4319 * the guest read/write access to the host's XSS.
4321 if (boot_cpu_has(X86_FEATURE_XSAVE) &&
4322 boot_cpu_has(X86_FEATURE_XSAVES) &&
4323 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE))
4324 kvm_governed_feature_set(vcpu, X86_FEATURE_XSAVES);
4326 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_NRIPS);
4327 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_TSCRATEMSR);
4328 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_LBRV);
4331 * Intercept VMLOAD if the vCPU mode is Intel in order to emulate that
4332 * VMLOAD drops bits 63:32 of SYSENTER (ignoring the fact that exposing
4333 * SVM on Intel is bonkers and extremely unlikely to work).
4335 if (!guest_cpuid_is_intel(vcpu))
4336 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_V_VMSAVE_VMLOAD);
4338 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_PAUSEFILTER);
4339 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_PFTHRESHOLD);
4340 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VGIF);
4341 kvm_governed_feature_check_and_set(vcpu, X86_FEATURE_VNMI);
4343 svm_recalc_instruction_intercepts(vcpu, svm);
4345 if (boot_cpu_has(X86_FEATURE_IBPB))
4346 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0,
4347 !!guest_has_pred_cmd_msr(vcpu));
4349 if (boot_cpu_has(X86_FEATURE_FLUSH_L1D))
4350 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_FLUSH_CMD, 0,
4351 !!guest_cpuid_has(vcpu, X86_FEATURE_FLUSH_L1D));
4353 if (sev_guest(vcpu->kvm))
4354 sev_vcpu_after_set_cpuid(svm);
4356 init_vmcb_after_set_cpuid(vcpu);
4359 static bool svm_has_wbinvd_exit(void)
4364 #define PRE_EX(exit) { .exit_code = (exit), \
4365 .stage = X86_ICPT_PRE_EXCEPT, }
4366 #define POST_EX(exit) { .exit_code = (exit), \
4367 .stage = X86_ICPT_POST_EXCEPT, }
4368 #define POST_MEM(exit) { .exit_code = (exit), \
4369 .stage = X86_ICPT_POST_MEMACCESS, }
4371 static const struct __x86_intercept {
4373 enum x86_intercept_stage stage;
4374 } x86_intercept_map[] = {
4375 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4376 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4377 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4378 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4379 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4380 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4381 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4382 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4383 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4384 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4385 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4386 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4387 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4388 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4389 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4390 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4391 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4392 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4393 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4394 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4395 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4396 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4397 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4398 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4399 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4400 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4401 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4402 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4403 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4404 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4405 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4406 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4407 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4408 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4409 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4410 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4411 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4412 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4413 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4414 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4415 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4416 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4417 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4418 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4419 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4420 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4421 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4428 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4429 struct x86_instruction_info *info,
4430 enum x86_intercept_stage stage,
4431 struct x86_exception *exception)
4433 struct vcpu_svm *svm = to_svm(vcpu);
4434 int vmexit, ret = X86EMUL_CONTINUE;
4435 struct __x86_intercept icpt_info;
4436 struct vmcb *vmcb = svm->vmcb;
4438 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4441 icpt_info = x86_intercept_map[info->intercept];
4443 if (stage != icpt_info.stage)
4446 switch (icpt_info.exit_code) {
4447 case SVM_EXIT_READ_CR0:
4448 if (info->intercept == x86_intercept_cr_read)
4449 icpt_info.exit_code += info->modrm_reg;
4451 case SVM_EXIT_WRITE_CR0: {
4452 unsigned long cr0, val;
4454 if (info->intercept == x86_intercept_cr_write)
4455 icpt_info.exit_code += info->modrm_reg;
4457 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4458 info->intercept == x86_intercept_clts)
4461 if (!(vmcb12_is_intercept(&svm->nested.ctl,
4462 INTERCEPT_SELECTIVE_CR0)))
4465 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4466 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4468 if (info->intercept == x86_intercept_lmsw) {
4471 /* lmsw can't clear PE - catch this here */
4472 if (cr0 & X86_CR0_PE)
4477 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4481 case SVM_EXIT_READ_DR0:
4482 case SVM_EXIT_WRITE_DR0:
4483 icpt_info.exit_code += info->modrm_reg;
4486 if (info->intercept == x86_intercept_wrmsr)
4487 vmcb->control.exit_info_1 = 1;
4489 vmcb->control.exit_info_1 = 0;
4491 case SVM_EXIT_PAUSE:
4493 * We get this for NOP only, but pause
4494 * is rep not, check this here
4496 if (info->rep_prefix != REPE_PREFIX)
4499 case SVM_EXIT_IOIO: {
4503 if (info->intercept == x86_intercept_in ||
4504 info->intercept == x86_intercept_ins) {
4505 exit_info = ((info->src_val & 0xffff) << 16) |
4507 bytes = info->dst_bytes;
4509 exit_info = (info->dst_val & 0xffff) << 16;
4510 bytes = info->src_bytes;
4513 if (info->intercept == x86_intercept_outs ||
4514 info->intercept == x86_intercept_ins)
4515 exit_info |= SVM_IOIO_STR_MASK;
4517 if (info->rep_prefix)
4518 exit_info |= SVM_IOIO_REP_MASK;
4520 bytes = min(bytes, 4u);
4522 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4524 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4526 vmcb->control.exit_info_1 = exit_info;
4527 vmcb->control.exit_info_2 = info->next_rip;
4535 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4536 if (static_cpu_has(X86_FEATURE_NRIPS))
4537 vmcb->control.next_rip = info->next_rip;
4538 vmcb->control.exit_code = icpt_info.exit_code;
4539 vmexit = nested_svm_exit_handled(svm);
4541 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4548 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4550 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR)
4551 vcpu->arch.at_instruction_boundary = true;
4554 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4556 if (!kvm_pause_in_guest(vcpu->kvm))
4557 shrink_ple_window(vcpu);
4560 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4562 /* [63:9] are reserved. */
4563 vcpu->arch.mcg_cap &= 0x1ff;
4566 #ifdef CONFIG_KVM_SMM
4567 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4569 struct vcpu_svm *svm = to_svm(vcpu);
4571 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4575 return is_smm(vcpu);
4578 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4580 struct vcpu_svm *svm = to_svm(vcpu);
4581 if (svm->nested.nested_run_pending)
4584 if (svm_smi_blocked(vcpu))
4587 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4588 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4594 static int svm_enter_smm(struct kvm_vcpu *vcpu, union kvm_smram *smram)
4596 struct vcpu_svm *svm = to_svm(vcpu);
4597 struct kvm_host_map map_save;
4600 if (!is_guest_mode(vcpu))
4604 * 32-bit SMRAM format doesn't preserve EFER and SVM state. Userspace is
4605 * responsible for ensuring nested SVM and SMIs are mutually exclusive.
4608 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4611 smram->smram64.svm_guest_flag = 1;
4612 smram->smram64.svm_guest_vmcb_gpa = svm->nested.vmcb12_gpa;
4614 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4615 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4616 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4618 ret = nested_svm_simple_vmexit(svm, SVM_EXIT_SW);
4623 * KVM uses VMCB01 to store L1 host state while L2 runs but
4624 * VMCB01 is going to be used during SMM and thus the state will
4625 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4626 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4627 * format of the area is identical to guest save area offsetted
4628 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4629 * within 'struct vmcb'). Note: HSAVE area may also be used by
4630 * L1 hypervisor to save additional host context (e.g. KVM does
4631 * that, see svm_prepare_switch_to_guest()) which must be
4634 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save))
4637 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4639 svm_copy_vmrun_state(map_save.hva + 0x400,
4640 &svm->vmcb01.ptr->save);
4642 kvm_vcpu_unmap(vcpu, &map_save, true);
4646 static int svm_leave_smm(struct kvm_vcpu *vcpu, const union kvm_smram *smram)
4648 struct vcpu_svm *svm = to_svm(vcpu);
4649 struct kvm_host_map map, map_save;
4650 struct vmcb *vmcb12;
4653 const struct kvm_smram_state_64 *smram64 = &smram->smram64;
4655 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4658 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4659 if (!smram64->svm_guest_flag)
4662 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4665 if (!(smram64->efer & EFER_SVME))
4668 if (kvm_vcpu_map(vcpu, gpa_to_gfn(smram64->svm_guest_vmcb_gpa), &map))
4672 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save))
4675 if (svm_allocate_nested(svm))
4679 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4680 * used during SMM (see svm_enter_smm())
4683 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4686 * Enter the nested guest now
4689 vmcb_mark_all_dirty(svm->vmcb01.ptr);
4692 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control);
4693 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save);
4694 ret = enter_svm_guest_mode(vcpu, smram64->svm_guest_vmcb_gpa, vmcb12, false);
4699 svm->nested.nested_run_pending = 1;
4702 kvm_vcpu_unmap(vcpu, &map_save, true);
4704 kvm_vcpu_unmap(vcpu, &map, true);
4708 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4710 struct vcpu_svm *svm = to_svm(vcpu);
4712 if (!gif_set(svm)) {
4714 svm_set_intercept(svm, INTERCEPT_STGI);
4715 /* STGI will cause a vm exit */
4717 /* We must be in SMM; RSM will cause a vmexit anyway. */
4722 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
4723 void *insn, int insn_len)
4725 bool smep, smap, is_user;
4728 /* Emulation is always possible when KVM has access to all guest state. */
4729 if (!sev_guest(vcpu->kvm))
4732 /* #UD and #GP should never be intercepted for SEV guests. */
4733 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD |
4734 EMULTYPE_TRAP_UD_FORCED |
4735 EMULTYPE_VMWARE_GP));
4738 * Emulation is impossible for SEV-ES guests as KVM doesn't have access
4739 * to guest register state.
4741 if (sev_es_guest(vcpu->kvm))
4745 * Emulation is possible if the instruction is already decoded, e.g.
4746 * when completing I/O after returning from userspace.
4748 if (emul_type & EMULTYPE_NO_DECODE)
4752 * Emulation is possible for SEV guests if and only if a prefilled
4753 * buffer containing the bytes of the intercepted instruction is
4754 * available. SEV guest memory is encrypted with a guest specific key
4755 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and
4758 * If KVM is NOT trying to simply skip an instruction, inject #UD if
4759 * KVM reached this point without an instruction buffer. In practice,
4760 * this path should never be hit by a well-behaved guest, e.g. KVM
4761 * doesn't intercept #UD or #GP for SEV guests, but this path is still
4762 * theoretically reachable, e.g. via unaccelerated fault-like AVIC
4763 * access, and needs to be handled by KVM to avoid putting the guest
4764 * into an infinite loop. Injecting #UD is somewhat arbitrary, but
4765 * its the least awful option given lack of insight into the guest.
4767 * If KVM is trying to skip an instruction, simply resume the guest.
4768 * If a #NPF occurs while the guest is vectoring an INT3/INTO, then KVM
4769 * will attempt to re-inject the INT3/INTO and skip the instruction.
4770 * In that scenario, retrying the INT3/INTO and hoping the guest will
4771 * make forward progress is the only option that has a chance of
4772 * success (and in practice it will work the vast majority of the time).
4774 if (unlikely(!insn)) {
4775 if (!(emul_type & EMULTYPE_SKIP))
4776 kvm_queue_exception(vcpu, UD_VECTOR);
4781 * Emulate for SEV guests if the insn buffer is not empty. The buffer
4782 * will be empty if the DecodeAssist microcode cannot fetch bytes for
4783 * the faulting instruction because the code fetch itself faulted, e.g.
4784 * the guest attempted to fetch from emulated MMIO or a guest page
4785 * table used to translate CS:RIP resides in emulated MMIO.
4787 if (likely(insn_len))
4791 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4794 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is
4795 * possible that CPU microcode implementing DecodeAssist will fail to
4796 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly
4797 * be '0'. This happens because microcode reads CS:RIP using a _data_
4798 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode
4799 * gives up and does not fill the instruction bytes buffer.
4801 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU
4802 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler
4803 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the
4804 * GuestIntrBytes field of the VMCB.
4806 * This does _not_ mean that the erratum has been encountered, as the
4807 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate
4808 * #PF, e.g. if the guest attempt to execute from emulated MMIO and
4809 * encountered a reserved/not-present #PF.
4811 * To hit the erratum, the following conditions must be true:
4812 * 1. CR4.SMAP=1 (obviously).
4813 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot
4814 * have been hit as the guest would have encountered a SMEP
4815 * violation #PF, not a #NPF.
4816 * 3. The #NPF is not due to a code fetch, in which case failure to
4817 * retrieve the instruction bytes is legitimate (see abvoe).
4819 * In addition, don't apply the erratum workaround if the #NPF occurred
4820 * while translating guest page tables (see below).
4822 error_code = to_svm(vcpu)->vmcb->control.exit_info_1;
4823 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK))
4826 smep = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMEP);
4827 smap = kvm_is_cr4_bit_set(vcpu, X86_CR4_SMAP);
4828 is_user = svm_get_cpl(vcpu) == 3;
4829 if (smap && (!smep || is_user)) {
4830 pr_err_ratelimited("SEV Guest triggered AMD Erratum 1096\n");
4833 * If the fault occurred in userspace, arbitrarily inject #GP
4834 * to avoid killing the guest and to hopefully avoid confusing
4835 * the guest kernel too much, e.g. injecting #PF would not be
4836 * coherent with respect to the guest's page tables. Request
4837 * triple fault if the fault occurred in the kernel as there's
4838 * no fault that KVM can inject without confusing the guest.
4839 * In practice, the triple fault is moot as no sane SEV kernel
4840 * will execute from user memory while also running with SMAP=1.
4843 kvm_inject_gp(vcpu, 0);
4845 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4850 * If the erratum was not hit, simply resume the guest and let it fault
4851 * again. While awful, e.g. the vCPU may get stuck in an infinite loop
4852 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to
4853 * userspace will kill the guest, and letting the emulator read garbage
4854 * will yield random behavior and potentially corrupt the guest.
4856 * Simply resuming the guest is technically not a violation of the SEV
4857 * architecture. AMD's APM states that all code fetches and page table
4858 * accesses for SEV guest are encrypted, regardless of the C-Bit. The
4859 * APM also states that encrypted accesses to MMIO are "ignored", but
4860 * doesn't explicitly define "ignored", i.e. doing nothing and letting
4861 * the guest spin is technically "ignoring" the access.
4866 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4868 struct vcpu_svm *svm = to_svm(vcpu);
4870 return !gif_set(svm);
4873 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4875 if (!sev_es_guest(vcpu->kvm))
4876 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4878 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4881 static void svm_vm_destroy(struct kvm *kvm)
4883 avic_vm_destroy(kvm);
4884 sev_vm_destroy(kvm);
4887 static int svm_vm_init(struct kvm *kvm)
4889 if (!pause_filter_count || !pause_filter_thresh)
4890 kvm->arch.pause_in_guest = true;
4893 int ret = avic_vm_init(kvm);
4901 static struct kvm_x86_ops svm_x86_ops __initdata = {
4902 .name = KBUILD_MODNAME,
4904 .check_processor_compatibility = svm_check_processor_compat,
4906 .hardware_unsetup = svm_hardware_unsetup,
4907 .hardware_enable = svm_hardware_enable,
4908 .hardware_disable = svm_hardware_disable,
4909 .has_emulated_msr = svm_has_emulated_msr,
4911 .vcpu_create = svm_vcpu_create,
4912 .vcpu_free = svm_vcpu_free,
4913 .vcpu_reset = svm_vcpu_reset,
4915 .vm_size = sizeof(struct kvm_svm),
4916 .vm_init = svm_vm_init,
4917 .vm_destroy = svm_vm_destroy,
4919 .prepare_switch_to_guest = svm_prepare_switch_to_guest,
4920 .vcpu_load = svm_vcpu_load,
4921 .vcpu_put = svm_vcpu_put,
4922 .vcpu_blocking = avic_vcpu_blocking,
4923 .vcpu_unblocking = avic_vcpu_unblocking,
4925 .update_exception_bitmap = svm_update_exception_bitmap,
4926 .get_msr_feature = svm_get_msr_feature,
4927 .get_msr = svm_get_msr,
4928 .set_msr = svm_set_msr,
4929 .get_segment_base = svm_get_segment_base,
4930 .get_segment = svm_get_segment,
4931 .set_segment = svm_set_segment,
4932 .get_cpl = svm_get_cpl,
4933 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
4934 .is_valid_cr0 = svm_is_valid_cr0,
4935 .set_cr0 = svm_set_cr0,
4936 .post_set_cr3 = sev_post_set_cr3,
4937 .is_valid_cr4 = svm_is_valid_cr4,
4938 .set_cr4 = svm_set_cr4,
4939 .set_efer = svm_set_efer,
4940 .get_idt = svm_get_idt,
4941 .set_idt = svm_set_idt,
4942 .get_gdt = svm_get_gdt,
4943 .set_gdt = svm_set_gdt,
4944 .set_dr7 = svm_set_dr7,
4945 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4946 .cache_reg = svm_cache_reg,
4947 .get_rflags = svm_get_rflags,
4948 .set_rflags = svm_set_rflags,
4949 .get_if_flag = svm_get_if_flag,
4951 .flush_tlb_all = svm_flush_tlb_all,
4952 .flush_tlb_current = svm_flush_tlb_current,
4953 .flush_tlb_gva = svm_flush_tlb_gva,
4954 .flush_tlb_guest = svm_flush_tlb_asid,
4956 .vcpu_pre_run = svm_vcpu_pre_run,
4957 .vcpu_run = svm_vcpu_run,
4958 .handle_exit = svm_handle_exit,
4959 .skip_emulated_instruction = svm_skip_emulated_instruction,
4960 .update_emulated_instruction = NULL,
4961 .set_interrupt_shadow = svm_set_interrupt_shadow,
4962 .get_interrupt_shadow = svm_get_interrupt_shadow,
4963 .patch_hypercall = svm_patch_hypercall,
4964 .inject_irq = svm_inject_irq,
4965 .inject_nmi = svm_inject_nmi,
4966 .is_vnmi_pending = svm_is_vnmi_pending,
4967 .set_vnmi_pending = svm_set_vnmi_pending,
4968 .inject_exception = svm_inject_exception,
4969 .cancel_injection = svm_cancel_injection,
4970 .interrupt_allowed = svm_interrupt_allowed,
4971 .nmi_allowed = svm_nmi_allowed,
4972 .get_nmi_mask = svm_get_nmi_mask,
4973 .set_nmi_mask = svm_set_nmi_mask,
4974 .enable_nmi_window = svm_enable_nmi_window,
4975 .enable_irq_window = svm_enable_irq_window,
4976 .update_cr8_intercept = svm_update_cr8_intercept,
4977 .set_virtual_apic_mode = avic_refresh_virtual_apic_mode,
4978 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl,
4979 .apicv_post_state_restore = avic_apicv_post_state_restore,
4980 .required_apicv_inhibits = AVIC_REQUIRED_APICV_INHIBITS,
4982 .get_exit_info = svm_get_exit_info,
4984 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4986 .has_wbinvd_exit = svm_has_wbinvd_exit,
4988 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4989 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4990 .write_tsc_offset = svm_write_tsc_offset,
4991 .write_tsc_multiplier = svm_write_tsc_multiplier,
4993 .load_mmu_pgd = svm_load_mmu_pgd,
4995 .check_intercept = svm_check_intercept,
4996 .handle_exit_irqoff = svm_handle_exit_irqoff,
4998 .request_immediate_exit = __kvm_request_immediate_exit,
5000 .sched_in = svm_sched_in,
5002 .nested_ops = &svm_nested_ops,
5004 .deliver_interrupt = svm_deliver_interrupt,
5005 .pi_update_irte = avic_pi_update_irte,
5006 .setup_mce = svm_setup_mce,
5008 #ifdef CONFIG_KVM_SMM
5009 .smi_allowed = svm_smi_allowed,
5010 .enter_smm = svm_enter_smm,
5011 .leave_smm = svm_leave_smm,
5012 .enable_smi_window = svm_enable_smi_window,
5015 .mem_enc_ioctl = sev_mem_enc_ioctl,
5016 .mem_enc_register_region = sev_mem_enc_register_region,
5017 .mem_enc_unregister_region = sev_mem_enc_unregister_region,
5018 .guest_memory_reclaimed = sev_guest_memory_reclaimed,
5020 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from,
5021 .vm_move_enc_context_from = sev_vm_move_enc_context_from,
5023 .can_emulate_instruction = svm_can_emulate_instruction,
5025 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
5027 .msr_filter_changed = svm_msr_filter_changed,
5028 .complete_emulated_msr = svm_complete_emulated_msr,
5030 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
5031 .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons,
5035 * The default MMIO mask is a single bit (excluding the present bit),
5036 * which could conflict with the memory encryption bit. Check for
5037 * memory encryption support and override the default MMIO mask if
5038 * memory encryption is enabled.
5040 static __init void svm_adjust_mmio_mask(void)
5042 unsigned int enc_bit, mask_bit;
5045 /* If there is no memory encryption support, use existing mask */
5046 if (cpuid_eax(0x80000000) < 0x8000001f)
5049 /* If memory encryption is not enabled, use existing mask */
5050 rdmsrl(MSR_AMD64_SYSCFG, msr);
5051 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
5054 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
5055 mask_bit = boot_cpu_data.x86_phys_bits;
5057 /* Increment the mask bit if it is the same as the encryption bit */
5058 if (enc_bit == mask_bit)
5062 * If the mask bit location is below 52, then some bits above the
5063 * physical addressing limit will always be reserved, so use the
5064 * rsvd_bits() function to generate the mask. This mask, along with
5065 * the present bit, will be used to generate a page fault with
5068 * If the mask bit location is 52 (or above), then clear the mask.
5070 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
5072 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
5075 static __init void svm_set_cpu_caps(void)
5079 kvm_caps.supported_perf_cap = 0;
5080 kvm_caps.supported_xss = 0;
5082 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
5084 kvm_cpu_cap_set(X86_FEATURE_SVM);
5085 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN);
5088 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
5091 kvm_cpu_cap_set(X86_FEATURE_NPT);
5094 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR);
5097 kvm_cpu_cap_set(X86_FEATURE_V_VMSAVE_VMLOAD);
5099 kvm_cpu_cap_set(X86_FEATURE_LBRV);
5101 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER))
5102 kvm_cpu_cap_set(X86_FEATURE_PAUSEFILTER);
5104 if (boot_cpu_has(X86_FEATURE_PFTHRESHOLD))
5105 kvm_cpu_cap_set(X86_FEATURE_PFTHRESHOLD);
5108 kvm_cpu_cap_set(X86_FEATURE_VGIF);
5111 kvm_cpu_cap_set(X86_FEATURE_VNMI);
5113 /* Nested VM can receive #VMEXIT instead of triggering #GP */
5114 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
5117 /* CPUID 0x80000008 */
5118 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
5119 boot_cpu_has(X86_FEATURE_AMD_SSBD))
5120 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
5124 * Enumerate support for PERFCTR_CORE if and only if KVM has
5125 * access to enough counters to virtualize "core" support,
5126 * otherwise limit vPMU support to the legacy number of counters.
5128 if (kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS_CORE)
5129 kvm_pmu_cap.num_counters_gp = min(AMD64_NUM_COUNTERS,
5130 kvm_pmu_cap.num_counters_gp);
5132 kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE);
5134 if (kvm_pmu_cap.version != 2 ||
5135 !kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE))
5136 kvm_cpu_cap_clear(X86_FEATURE_PERFMON_V2);
5139 /* CPUID 0x8000001F (SME/SEV features) */
5143 static __init int svm_hardware_setup(void)
5146 struct page *iopm_pages;
5149 unsigned int order = get_order(IOPM_SIZE);
5152 * NX is required for shadow paging and for NPT if the NX huge pages
5153 * mitigation is enabled.
5155 if (!boot_cpu_has(X86_FEATURE_NX)) {
5156 pr_err_ratelimited("NX (Execute Disable) not supported\n");
5159 kvm_enable_efer_bits(EFER_NX);
5161 iopm_pages = alloc_pages(GFP_KERNEL, order);
5166 iopm_va = page_address(iopm_pages);
5167 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
5168 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
5170 init_msrpm_offsets();
5172 kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
5173 XFEATURE_MASK_BNDCSR);
5175 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
5176 kvm_enable_efer_bits(EFER_FFXSR);
5179 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
5180 tsc_scaling = false;
5182 pr_info("TSC scaling supported\n");
5183 kvm_caps.has_tsc_control = true;
5186 kvm_caps.max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
5187 kvm_caps.tsc_scaling_ratio_frac_bits = 32;
5189 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
5191 if (boot_cpu_has(X86_FEATURE_AUTOIBRS))
5192 kvm_enable_efer_bits(EFER_AUTOIBRS);
5194 /* Check for pause filtering support */
5195 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
5196 pause_filter_count = 0;
5197 pause_filter_thresh = 0;
5198 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
5199 pause_filter_thresh = 0;
5203 pr_info("Nested Virtualization enabled\n");
5204 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
5208 * KVM's MMU doesn't support using 2-level paging for itself, and thus
5209 * NPT isn't supported if the host is using 2-level paging since host
5210 * CR4 is unchanged on VMRUN.
5212 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
5213 npt_enabled = false;
5215 if (!boot_cpu_has(X86_FEATURE_NPT))
5216 npt_enabled = false;
5218 /* Force VM NPT level equal to the host's paging level */
5219 kvm_configure_mmu(npt_enabled, get_npt_level(),
5220 get_npt_level(), PG_LEVEL_1G);
5221 pr_info("Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
5223 /* Setup shadow_me_value and shadow_me_mask */
5224 kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);
5226 svm_adjust_mmio_mask();
5228 nrips = nrips && boot_cpu_has(X86_FEATURE_NRIPS);
5231 * Note, SEV setup consumes npt_enabled and enable_mmio_caching (which
5232 * may be modified by svm_adjust_mmio_mask()), as well as nrips.
5234 sev_hardware_setup();
5236 svm_hv_hardware_setup();
5238 for_each_possible_cpu(cpu) {
5239 r = svm_cpu_init(cpu);
5244 enable_apicv = avic = avic && avic_hardware_setup();
5246 if (!enable_apicv) {
5247 svm_x86_ops.vcpu_blocking = NULL;
5248 svm_x86_ops.vcpu_unblocking = NULL;
5249 svm_x86_ops.vcpu_get_apicv_inhibit_reasons = NULL;
5250 } else if (!x2avic_enabled) {
5251 svm_x86_ops.allow_apicv_in_x2apic_without_x2apic_virtualization = true;
5256 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
5257 !IS_ENABLED(CONFIG_X86_64)) {
5260 pr_info("Virtual VMLOAD VMSAVE supported\n");
5264 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
5265 svm_gp_erratum_intercept = false;
5268 if (!boot_cpu_has(X86_FEATURE_VGIF))
5271 pr_info("Virtual GIF supported\n");
5274 vnmi = vgif && vnmi && boot_cpu_has(X86_FEATURE_VNMI);
5276 pr_info("Virtual NMI enabled\n");
5279 svm_x86_ops.is_vnmi_pending = NULL;
5280 svm_x86_ops.set_vnmi_pending = NULL;
5285 if (!boot_cpu_has(X86_FEATURE_LBRV))
5288 pr_info("LBR virtualization supported\n");
5292 pr_info("PMU virtualization is disabled\n");
5297 * It seems that on AMD processors PTE's accessed bit is
5298 * being set by the CPU hardware before the NPF vmexit.
5299 * This is not expected behaviour and our tests fail because
5301 * A workaround here is to disable support for
5302 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
5303 * In this case userspace can know if there is support using
5304 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
5306 * If future AMD CPU models change the behaviour described above,
5307 * this variable can be changed accordingly
5309 allow_smaller_maxphyaddr = !npt_enabled;
5314 svm_hardware_unsetup();
5319 static struct kvm_x86_init_ops svm_init_ops __initdata = {
5320 .hardware_setup = svm_hardware_setup,
5322 .runtime_ops = &svm_x86_ops,
5323 .pmu_ops = &amd_pmu_ops,
5326 static void __svm_exit(void)
5328 kvm_x86_vendor_exit();
5330 cpu_emergency_unregister_virt_callback(svm_emergency_disable);
5333 static int __init svm_init(void)
5337 __unused_size_checks();
5339 if (!kvm_is_svm_supported())
5342 r = kvm_x86_vendor_init(&svm_init_ops);
5346 cpu_emergency_register_virt_callback(svm_emergency_disable);
5349 * Common KVM initialization _must_ come last, after this, /dev/kvm is
5350 * exposed to userspace!
5352 r = kvm_init(sizeof(struct vcpu_svm), __alignof__(struct vcpu_svm),
5364 static void __exit svm_exit(void)
5370 module_init(svm_init)
5371 module_exit(svm_exit)