1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/spec-ctrl.h>
37 #include <asm/cpu_device_id.h>
38 #include <asm/traps.h>
40 #include <asm/virtext.h>
46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
48 MODULE_AUTHOR("Qumranet");
49 MODULE_LICENSE("GPL");
52 static const struct x86_cpu_id svm_cpu_id[] = {
53 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
56 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
59 #define IOPM_ALLOC_ORDER 2
60 #define MSRPM_ALLOC_ORDER 1
62 #define SEG_TYPE_LDT 2
63 #define SEG_TYPE_BUSY_TSS16 3
65 #define SVM_FEATURE_LBRV (1 << 1)
66 #define SVM_FEATURE_SVML (1 << 2)
67 #define SVM_FEATURE_TSC_RATE (1 << 4)
68 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
69 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
70 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
71 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
73 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
75 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
76 #define TSC_RATIO_MIN 0x0000000000000001ULL
77 #define TSC_RATIO_MAX 0x000000ffffffffffULL
79 static bool erratum_383_found __read_mostly;
81 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
84 * Set osvw_len to higher value when updated Revision Guides
85 * are published and we know what the new status bits are
87 static uint64_t osvw_len = 4, osvw_status;
89 static DEFINE_PER_CPU(u64, current_tsc_ratio);
90 #define TSC_RATIO_DEFAULT 0x0100000000ULL
92 static const struct svm_direct_access_msrs {
93 u32 index; /* Index of the MSR */
94 bool always; /* True if intercept is initially cleared */
95 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
96 { .index = MSR_STAR, .always = true },
97 { .index = MSR_IA32_SYSENTER_CS, .always = true },
99 { .index = MSR_GS_BASE, .always = true },
100 { .index = MSR_FS_BASE, .always = true },
101 { .index = MSR_KERNEL_GS_BASE, .always = true },
102 { .index = MSR_LSTAR, .always = true },
103 { .index = MSR_CSTAR, .always = true },
104 { .index = MSR_SYSCALL_MASK, .always = true },
106 { .index = MSR_IA32_SPEC_CTRL, .always = false },
107 { .index = MSR_IA32_PRED_CMD, .always = false },
108 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
109 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
110 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
111 { .index = MSR_IA32_LASTINTTOIP, .always = false },
112 { .index = MSR_EFER, .always = false },
113 { .index = MSR_IA32_CR_PAT, .always = false },
114 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
115 { .index = MSR_INVALID, .always = false },
119 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
120 * pause_filter_count: On processors that support Pause filtering(indicated
121 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
122 * count value. On VMRUN this value is loaded into an internal counter.
123 * Each time a pause instruction is executed, this counter is decremented
124 * until it reaches zero at which time a #VMEXIT is generated if pause
125 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
126 * Intercept Filtering for more details.
127 * This also indicate if ple logic enabled.
129 * pause_filter_thresh: In addition, some processor families support advanced
130 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
131 * the amount of time a guest is allowed to execute in a pause loop.
132 * In this mode, a 16-bit pause filter threshold field is added in the
133 * VMCB. The threshold value is a cycle count that is used to reset the
134 * pause counter. As with simple pause filtering, VMRUN loads the pause
135 * count value from VMCB into an internal counter. Then, on each pause
136 * instruction the hardware checks the elapsed number of cycles since
137 * the most recent pause instruction against the pause filter threshold.
138 * If the elapsed cycle count is greater than the pause filter threshold,
139 * then the internal pause count is reloaded from the VMCB and execution
140 * continues. If the elapsed cycle count is less than the pause filter
141 * threshold, then the internal pause count is decremented. If the count
142 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
143 * triggered. If advanced pause filtering is supported and pause filter
144 * threshold field is set to zero, the filter will operate in the simpler,
148 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
149 module_param(pause_filter_thresh, ushort, 0444);
151 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
152 module_param(pause_filter_count, ushort, 0444);
154 /* Default doubles per-vcpu window every exit. */
155 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
156 module_param(pause_filter_count_grow, ushort, 0444);
158 /* Default resets per-vcpu window every exit to pause_filter_count. */
159 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
160 module_param(pause_filter_count_shrink, ushort, 0444);
162 /* Default is to compute the maximum so we can never overflow. */
163 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
164 module_param(pause_filter_count_max, ushort, 0444);
167 * Use nested page tables by default. Note, NPT may get forced off by
168 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
170 bool npt_enabled = true;
171 module_param_named(npt, npt_enabled, bool, 0444);
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
189 /* enable/disable SEV support */
190 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191 module_param(sev, int, 0444);
193 /* enable/disable SEV-ES support */
194 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
195 module_param(sev_es, int, 0444);
197 bool __read_mostly dump_invalid_vmcb;
198 module_param(dump_invalid_vmcb, bool, 0644);
200 static bool svm_gp_erratum_intercept = true;
202 static u8 rsm_ins_bytes[] = "\x0f\xaa";
204 static unsigned long iopm_base;
206 struct kvm_ldttss_desc {
209 unsigned base1:8, type:5, dpl:2, p:1;
210 unsigned limit1:4, zero0:3, g:1, base2:8;
213 } __attribute__((packed));
215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
220 #define MSRS_RANGE_SIZE 2048
221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
223 u32 svm_msrpm_offset(u32 msr)
228 for (i = 0; i < NUM_MSR_MAPS; i++) {
229 if (msr < msrpm_ranges[i] ||
230 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
233 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
234 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
236 /* Now we have the u8 offset - but need the u32 offset */
240 /* MSR not in any range */
244 #define MAX_INST_SIZE 15
246 static int get_max_npt_level(void)
249 return PT64_ROOT_4LEVEL;
251 return PT32E_ROOT_LEVEL;
255 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
257 struct vcpu_svm *svm = to_svm(vcpu);
258 u64 old_efer = vcpu->arch.efer;
259 vcpu->arch.efer = efer;
262 /* Shadow paging assumes NX to be available. */
265 if (!(efer & EFER_LMA))
269 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
270 if (!(efer & EFER_SVME)) {
271 svm_leave_nested(svm);
272 svm_set_gif(svm, true);
273 /* #GP intercept is still needed for vmware backdoor */
274 if (!enable_vmware_backdoor)
275 clr_exception_intercept(svm, GP_VECTOR);
278 * Free the nested guest state, unless we are in SMM.
279 * In this case we will return to the nested guest
280 * as soon as we leave SMM.
282 if (!is_smm(&svm->vcpu))
283 svm_free_nested(svm);
286 int ret = svm_allocate_nested(svm);
289 vcpu->arch.efer = old_efer;
293 if (svm_gp_erratum_intercept)
294 set_exception_intercept(svm, GP_VECTOR);
298 svm->vmcb->save.efer = efer | EFER_SVME;
299 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
303 static int is_external_interrupt(u32 info)
305 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
306 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
309 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
311 struct vcpu_svm *svm = to_svm(vcpu);
314 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
315 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
319 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
321 struct vcpu_svm *svm = to_svm(vcpu);
324 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
326 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
330 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
332 struct vcpu_svm *svm = to_svm(vcpu);
335 * SEV-ES does not expose the next RIP. The RIP update is controlled by
336 * the type of exit and the #VC handler in the guest.
338 if (sev_es_guest(vcpu->kvm))
341 if (nrips && svm->vmcb->control.next_rip != 0) {
342 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
343 svm->next_rip = svm->vmcb->control.next_rip;
346 if (!svm->next_rip) {
347 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
350 kvm_rip_write(vcpu, svm->next_rip);
354 svm_set_interrupt_shadow(vcpu, 0);
359 static void svm_queue_exception(struct kvm_vcpu *vcpu)
361 struct vcpu_svm *svm = to_svm(vcpu);
362 unsigned nr = vcpu->arch.exception.nr;
363 bool has_error_code = vcpu->arch.exception.has_error_code;
364 u32 error_code = vcpu->arch.exception.error_code;
366 kvm_deliver_exception_payload(&svm->vcpu);
368 if (nr == BP_VECTOR && !nrips) {
369 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
372 * For guest debugging where we have to reinject #BP if some
373 * INT3 is guest-owned:
374 * Emulate nRIP by moving RIP forward. Will fail if injection
375 * raises a fault that is not intercepted. Still better than
376 * failing in all cases.
378 (void)skip_emulated_instruction(&svm->vcpu);
379 rip = kvm_rip_read(&svm->vcpu);
380 svm->int3_rip = rip + svm->vmcb->save.cs.base;
381 svm->int3_injected = rip - old_rip;
384 svm->vmcb->control.event_inj = nr
386 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
387 | SVM_EVTINJ_TYPE_EXEPT;
388 svm->vmcb->control.event_inj_err = error_code;
391 static void svm_init_erratum_383(void)
397 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
400 /* Use _safe variants to not break nested virtualization */
401 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
407 low = lower_32_bits(val);
408 high = upper_32_bits(val);
410 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
412 erratum_383_found = true;
415 static void svm_init_osvw(struct kvm_vcpu *vcpu)
418 * Guests should see errata 400 and 415 as fixed (assuming that
419 * HLT and IO instructions are intercepted).
421 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
422 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
425 * By increasing VCPU's osvw.length to 3 we are telling the guest that
426 * all osvw.status bits inside that length, including bit 0 (which is
427 * reserved for erratum 298), are valid. However, if host processor's
428 * osvw_len is 0 then osvw_status[0] carries no information. We need to
429 * be conservative here and therefore we tell the guest that erratum 298
430 * is present (because we really don't know).
432 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
433 vcpu->arch.osvw.status |= 1;
436 static int has_svm(void)
440 if (!cpu_has_svm(&msg)) {
441 printk(KERN_INFO "has_svm: %s\n", msg);
446 pr_info("KVM is unsupported when running as an SEV guest\n");
453 static void svm_hardware_disable(void)
455 /* Make sure we clean up behind us */
456 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
457 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
461 amd_pmu_disable_virt();
464 static int svm_hardware_enable(void)
467 struct svm_cpu_data *sd;
469 struct desc_struct *gdt;
470 int me = raw_smp_processor_id();
472 rdmsrl(MSR_EFER, efer);
473 if (efer & EFER_SVME)
477 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
480 sd = per_cpu(svm_data, me);
482 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
486 sd->asid_generation = 1;
487 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
488 sd->next_asid = sd->max_asid + 1;
489 sd->min_asid = max_sev_asid + 1;
491 gdt = get_current_gdt_rw();
492 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
494 wrmsrl(MSR_EFER, efer | EFER_SVME);
496 wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
498 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
499 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
500 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
507 * Note that it is possible to have a system with mixed processor
508 * revisions and therefore different OSVW bits. If bits are not the same
509 * on different processors then choose the worst case (i.e. if erratum
510 * is present on one processor and not on another then assume that the
511 * erratum is present everywhere).
513 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
514 uint64_t len, status = 0;
517 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
519 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
523 osvw_status = osvw_len = 0;
527 osvw_status |= status;
528 osvw_status &= (1ULL << osvw_len) - 1;
531 osvw_status = osvw_len = 0;
533 svm_init_erratum_383();
535 amd_pmu_enable_virt();
540 static void svm_cpu_uninit(int cpu)
542 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
547 per_cpu(svm_data, cpu) = NULL;
548 kfree(sd->sev_vmcbs);
549 __free_page(sd->save_area);
553 static int svm_cpu_init(int cpu)
555 struct svm_cpu_data *sd;
557 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
561 sd->save_area = alloc_page(GFP_KERNEL);
564 clear_page(page_address(sd->save_area));
566 if (svm_sev_enabled()) {
567 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
574 per_cpu(svm_data, cpu) = sd;
579 __free_page(sd->save_area);
586 static int direct_access_msr_slot(u32 msr)
590 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
591 if (direct_access_msrs[i].index == msr)
597 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
600 struct vcpu_svm *svm = to_svm(vcpu);
601 int slot = direct_access_msr_slot(msr);
606 /* Set the shadow bitmaps to the desired intercept states */
608 set_bit(slot, svm->shadow_msr_intercept.read);
610 clear_bit(slot, svm->shadow_msr_intercept.read);
613 set_bit(slot, svm->shadow_msr_intercept.write);
615 clear_bit(slot, svm->shadow_msr_intercept.write);
618 static bool valid_msr_intercept(u32 index)
620 return direct_access_msr_slot(index) != -ENOENT;
623 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
630 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
633 offset = svm_msrpm_offset(msr);
634 bit_write = 2 * (msr & 0x0f) + 1;
637 BUG_ON(offset == MSR_INVALID);
639 return !!test_bit(bit_write, &tmp);
642 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
643 u32 msr, int read, int write)
645 u8 bit_read, bit_write;
650 * If this warning triggers extend the direct_access_msrs list at the
651 * beginning of the file
653 WARN_ON(!valid_msr_intercept(msr));
655 /* Enforce non allowed MSRs to trap */
656 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
659 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
662 offset = svm_msrpm_offset(msr);
663 bit_read = 2 * (msr & 0x0f);
664 bit_write = 2 * (msr & 0x0f) + 1;
667 BUG_ON(offset == MSR_INVALID);
669 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
670 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
675 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
678 set_shadow_msr_intercept(vcpu, msr, read, write);
679 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
682 u32 *svm_vcpu_alloc_msrpm(void)
684 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
690 msrpm = page_address(pages);
691 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
696 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
700 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
701 if (!direct_access_msrs[i].always)
703 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
708 void svm_vcpu_free_msrpm(u32 *msrpm)
710 __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
713 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
715 struct vcpu_svm *svm = to_svm(vcpu);
719 * Set intercept permissions for all direct access MSRs again. They
720 * will automatically get filtered through the MSR filter, so we are
721 * back in sync after this.
723 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
724 u32 msr = direct_access_msrs[i].index;
725 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
726 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
728 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
732 static void add_msr_offset(u32 offset)
736 for (i = 0; i < MSRPM_OFFSETS; ++i) {
738 /* Offset already in list? */
739 if (msrpm_offsets[i] == offset)
742 /* Slot used by another offset? */
743 if (msrpm_offsets[i] != MSR_INVALID)
746 /* Add offset to list */
747 msrpm_offsets[i] = offset;
753 * If this BUG triggers the msrpm_offsets table has an overflow. Just
754 * increase MSRPM_OFFSETS in this case.
759 static void init_msrpm_offsets(void)
763 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
765 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
768 offset = svm_msrpm_offset(direct_access_msrs[i].index);
769 BUG_ON(offset == MSR_INVALID);
771 add_msr_offset(offset);
775 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
777 struct vcpu_svm *svm = to_svm(vcpu);
779 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
780 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
781 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
782 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
783 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
786 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
788 struct vcpu_svm *svm = to_svm(vcpu);
790 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
791 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
792 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
793 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
794 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
797 void disable_nmi_singlestep(struct vcpu_svm *svm)
799 svm->nmi_singlestep = false;
801 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
802 /* Clear our flags if they were not set by the guest */
803 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
804 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
805 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
806 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
810 static void grow_ple_window(struct kvm_vcpu *vcpu)
812 struct vcpu_svm *svm = to_svm(vcpu);
813 struct vmcb_control_area *control = &svm->vmcb->control;
814 int old = control->pause_filter_count;
816 control->pause_filter_count = __grow_ple_window(old,
818 pause_filter_count_grow,
819 pause_filter_count_max);
821 if (control->pause_filter_count != old) {
822 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
823 trace_kvm_ple_window_update(vcpu->vcpu_id,
824 control->pause_filter_count, old);
828 static void shrink_ple_window(struct kvm_vcpu *vcpu)
830 struct vcpu_svm *svm = to_svm(vcpu);
831 struct vmcb_control_area *control = &svm->vmcb->control;
832 int old = control->pause_filter_count;
834 control->pause_filter_count =
835 __shrink_ple_window(old,
837 pause_filter_count_shrink,
839 if (control->pause_filter_count != old) {
840 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
841 trace_kvm_ple_window_update(vcpu->vcpu_id,
842 control->pause_filter_count, old);
847 * The default MMIO mask is a single bit (excluding the present bit),
848 * which could conflict with the memory encryption bit. Check for
849 * memory encryption support and override the default MMIO mask if
850 * memory encryption is enabled.
852 static __init void svm_adjust_mmio_mask(void)
854 unsigned int enc_bit, mask_bit;
857 /* If there is no memory encryption support, use existing mask */
858 if (cpuid_eax(0x80000000) < 0x8000001f)
861 /* If memory encryption is not enabled, use existing mask */
862 rdmsrl(MSR_K8_SYSCFG, msr);
863 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
866 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
867 mask_bit = boot_cpu_data.x86_phys_bits;
869 /* Increment the mask bit if it is the same as the encryption bit */
870 if (enc_bit == mask_bit)
874 * If the mask bit location is below 52, then some bits above the
875 * physical addressing limit will always be reserved, so use the
876 * rsvd_bits() function to generate the mask. This mask, along with
877 * the present bit, will be used to generate a page fault with
880 * If the mask bit location is 52 (or above), then clear the mask.
882 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
884 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
887 static void svm_hardware_teardown(void)
891 if (svm_sev_enabled())
892 sev_hardware_teardown();
894 for_each_possible_cpu(cpu)
897 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
901 static __init void svm_set_cpu_caps(void)
907 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
909 kvm_cpu_cap_set(X86_FEATURE_SVM);
912 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
915 kvm_cpu_cap_set(X86_FEATURE_NPT);
917 /* Nested VM can receive #VMEXIT instead of triggering #GP */
918 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
921 /* CPUID 0x80000008 */
922 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
923 boot_cpu_has(X86_FEATURE_AMD_SSBD))
924 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
927 static __init int svm_hardware_setup(void)
930 struct page *iopm_pages;
934 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
939 iopm_va = page_address(iopm_pages);
940 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
941 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
943 init_msrpm_offsets();
945 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
947 if (boot_cpu_has(X86_FEATURE_NX))
948 kvm_enable_efer_bits(EFER_NX);
950 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
951 kvm_enable_efer_bits(EFER_FFXSR);
953 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
954 kvm_has_tsc_control = true;
955 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
956 kvm_tsc_scaling_ratio_frac_bits = 32;
959 /* Check for pause filtering support */
960 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
961 pause_filter_count = 0;
962 pause_filter_thresh = 0;
963 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
964 pause_filter_thresh = 0;
968 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
969 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
972 if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
973 sev_hardware_setup();
979 svm_adjust_mmio_mask();
981 for_each_possible_cpu(cpu) {
982 r = svm_cpu_init(cpu);
988 * KVM's MMU doesn't support using 2-level paging for itself, and thus
989 * NPT isn't supported if the host is using 2-level paging since host
990 * CR4 is unchanged on VMRUN.
992 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
995 if (!boot_cpu_has(X86_FEATURE_NPT))
998 kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
999 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
1002 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1008 !boot_cpu_has(X86_FEATURE_AVIC) ||
1009 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1012 pr_info("AVIC enabled\n");
1014 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1020 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1021 !IS_ENABLED(CONFIG_X86_64)) {
1024 pr_info("Virtual VMLOAD VMSAVE supported\n");
1028 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1029 svm_gp_erratum_intercept = false;
1032 if (!boot_cpu_has(X86_FEATURE_VGIF))
1035 pr_info("Virtual GIF supported\n");
1041 * It seems that on AMD processors PTE's accessed bit is
1042 * being set by the CPU hardware before the NPF vmexit.
1043 * This is not expected behaviour and our tests fail because
1045 * A workaround here is to disable support for
1046 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1047 * In this case userspace can know if there is support using
1048 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1050 * If future AMD CPU models change the behaviour described above,
1051 * this variable can be changed accordingly
1053 allow_smaller_maxphyaddr = !npt_enabled;
1058 svm_hardware_teardown();
1062 static void init_seg(struct vmcb_seg *seg)
1065 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1066 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1067 seg->limit = 0xffff;
1071 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1074 seg->attrib = SVM_SELECTOR_P_MASK | type;
1075 seg->limit = 0xffff;
1079 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1081 struct vcpu_svm *svm = to_svm(vcpu);
1082 u64 g_tsc_offset = 0;
1084 if (is_guest_mode(vcpu)) {
1085 /* Write L1's TSC offset. */
1086 g_tsc_offset = svm->vmcb->control.tsc_offset -
1087 svm->nested.hsave->control.tsc_offset;
1088 svm->nested.hsave->control.tsc_offset = offset;
1091 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1092 svm->vmcb->control.tsc_offset - g_tsc_offset,
1095 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1097 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1098 return svm->vmcb->control.tsc_offset;
1101 static void svm_check_invpcid(struct vcpu_svm *svm)
1104 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1105 * roots, or if INVPCID is disabled in the guest to inject #UD.
1107 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1109 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1110 svm_set_intercept(svm, INTERCEPT_INVPCID);
1112 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1116 static void init_vmcb(struct vcpu_svm *svm)
1118 struct vmcb_control_area *control = &svm->vmcb->control;
1119 struct vmcb_save_area *save = &svm->vmcb->save;
1121 svm->vcpu.arch.hflags = 0;
1123 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1124 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1125 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1126 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1127 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1128 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1129 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1130 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1132 set_dr_intercepts(svm);
1134 set_exception_intercept(svm, PF_VECTOR);
1135 set_exception_intercept(svm, UD_VECTOR);
1136 set_exception_intercept(svm, MC_VECTOR);
1137 set_exception_intercept(svm, AC_VECTOR);
1138 set_exception_intercept(svm, DB_VECTOR);
1140 * Guest access to VMware backdoor ports could legitimately
1141 * trigger #GP because of TSS I/O permission bitmap.
1142 * We intercept those #GP and allow access to them anyway
1145 if (enable_vmware_backdoor)
1146 set_exception_intercept(svm, GP_VECTOR);
1148 svm_set_intercept(svm, INTERCEPT_INTR);
1149 svm_set_intercept(svm, INTERCEPT_NMI);
1150 svm_set_intercept(svm, INTERCEPT_SMI);
1151 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1152 svm_set_intercept(svm, INTERCEPT_RDPMC);
1153 svm_set_intercept(svm, INTERCEPT_CPUID);
1154 svm_set_intercept(svm, INTERCEPT_INVD);
1155 svm_set_intercept(svm, INTERCEPT_INVLPG);
1156 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1157 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1158 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1159 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1160 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1161 svm_set_intercept(svm, INTERCEPT_VMRUN);
1162 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1163 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1164 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1165 svm_set_intercept(svm, INTERCEPT_STGI);
1166 svm_set_intercept(svm, INTERCEPT_CLGI);
1167 svm_set_intercept(svm, INTERCEPT_SKINIT);
1168 svm_set_intercept(svm, INTERCEPT_WBINVD);
1169 svm_set_intercept(svm, INTERCEPT_XSETBV);
1170 svm_set_intercept(svm, INTERCEPT_RDPRU);
1171 svm_set_intercept(svm, INTERCEPT_RSM);
1173 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1174 svm_set_intercept(svm, INTERCEPT_MONITOR);
1175 svm_set_intercept(svm, INTERCEPT_MWAIT);
1178 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1179 svm_set_intercept(svm, INTERCEPT_HLT);
1181 control->iopm_base_pa = __sme_set(iopm_base);
1182 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1183 control->int_ctl = V_INTR_MASKING_MASK;
1185 init_seg(&save->es);
1186 init_seg(&save->ss);
1187 init_seg(&save->ds);
1188 init_seg(&save->fs);
1189 init_seg(&save->gs);
1191 save->cs.selector = 0xf000;
1192 save->cs.base = 0xffff0000;
1193 /* Executable/Readable Code Segment */
1194 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1195 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1196 save->cs.limit = 0xffff;
1198 save->gdtr.limit = 0xffff;
1199 save->idtr.limit = 0xffff;
1201 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1202 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1204 svm_set_cr4(&svm->vcpu, 0);
1205 svm_set_efer(&svm->vcpu, 0);
1206 save->dr6 = 0xffff0ff0;
1207 kvm_set_rflags(&svm->vcpu, X86_EFLAGS_FIXED);
1208 save->rip = 0x0000fff0;
1209 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1212 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1213 * It also updates the guest-visible cr0 value.
1215 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1216 kvm_mmu_reset_context(&svm->vcpu);
1218 save->cr4 = X86_CR4_PAE;
1222 /* Setup VMCB for Nested Paging */
1223 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1224 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1225 clr_exception_intercept(svm, PF_VECTOR);
1226 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1227 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1228 save->g_pat = svm->vcpu.arch.pat;
1232 svm->asid_generation = 0;
1235 svm->nested.vmcb12_gpa = 0;
1236 svm->vcpu.arch.hflags = 0;
1238 if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1239 control->pause_filter_count = pause_filter_count;
1240 if (pause_filter_thresh)
1241 control->pause_filter_thresh = pause_filter_thresh;
1242 svm_set_intercept(svm, INTERCEPT_PAUSE);
1244 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1247 svm_check_invpcid(svm);
1249 if (kvm_vcpu_apicv_active(&svm->vcpu))
1250 avic_init_vmcb(svm);
1253 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1254 * in VMCB and clear intercepts to avoid #VMEXIT.
1257 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1258 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1259 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1263 svm_clr_intercept(svm, INTERCEPT_STGI);
1264 svm_clr_intercept(svm, INTERCEPT_CLGI);
1265 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1268 if (sev_guest(svm->vcpu.kvm)) {
1269 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1270 clr_exception_intercept(svm, UD_VECTOR);
1272 if (sev_es_guest(svm->vcpu.kvm)) {
1273 /* Perform SEV-ES specific VMCB updates */
1274 sev_es_init_vmcb(svm);
1278 vmcb_mark_all_dirty(svm->vmcb);
1284 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1286 struct vcpu_svm *svm = to_svm(vcpu);
1291 svm->virt_spec_ctrl = 0;
1294 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1295 MSR_IA32_APICBASE_ENABLE;
1296 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1297 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1301 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1302 kvm_rdx_write(vcpu, eax);
1304 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1305 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1308 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1310 struct vcpu_svm *svm;
1311 struct page *vmcb_page;
1312 struct page *vmsa_page = NULL;
1315 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1319 vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1323 if (sev_es_guest(svm->vcpu.kvm)) {
1325 * SEV-ES guests require a separate VMSA page used to contain
1326 * the encrypted register state of the guest.
1328 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1330 goto error_free_vmcb_page;
1333 * SEV-ES guests maintain an encrypted version of their FPU
1334 * state which is restored and saved on VMRUN and VMEXIT.
1335 * Free the fpu structure to prevent KVM from attempting to
1336 * access the FPU state.
1338 kvm_free_guest_fpu(vcpu);
1341 err = avic_init_vcpu(svm);
1343 goto error_free_vmsa_page;
1345 /* We initialize this flag to true to make sure that the is_running
1346 * bit would be set the first time the vcpu is loaded.
1348 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1349 svm->avic_is_running = true;
1351 svm->msrpm = svm_vcpu_alloc_msrpm();
1354 goto error_free_vmsa_page;
1357 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1359 svm->vmcb = page_address(vmcb_page);
1360 svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1363 svm->vmsa = page_address(vmsa_page);
1365 svm->asid_generation = 0;
1366 svm->guest_state_loaded = false;
1369 svm_init_osvw(vcpu);
1370 vcpu->arch.microcode_version = 0x01000065;
1372 if (sev_es_guest(svm->vcpu.kvm))
1373 /* Perform SEV-ES specific VMCB creation updates */
1374 sev_es_create_vcpu(svm);
1378 error_free_vmsa_page:
1380 __free_page(vmsa_page);
1381 error_free_vmcb_page:
1382 __free_page(vmcb_page);
1387 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1391 for_each_online_cpu(i)
1392 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1395 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1397 struct vcpu_svm *svm = to_svm(vcpu);
1400 * The vmcb page can be recycled, causing a false negative in
1401 * svm_vcpu_load(). So, ensure that no logical CPU has this
1402 * vmcb page recorded as its current vmcb.
1404 svm_clear_current_vmcb(svm->vmcb);
1406 svm_free_nested(svm);
1408 sev_free_vcpu(vcpu);
1410 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1411 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1414 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1416 struct vcpu_svm *svm = to_svm(vcpu);
1417 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1420 if (svm->guest_state_loaded)
1424 * Certain MSRs are restored on VMEXIT (sev-es), or vmload of host save
1425 * area (non-sev-es). Save ones that aren't so we can restore them
1426 * individually later.
1428 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1429 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1432 * Save additional host state that will be restored on VMEXIT (sev-es)
1433 * or subsequent vmload of host save area.
1435 if (sev_es_guest(svm->vcpu.kvm)) {
1436 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1438 vmsave(__sme_page_pa(sd->save_area));
1441 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1442 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1443 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1444 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1445 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1449 /* This assumes that the kernel never uses MSR_TSC_AUX */
1450 if (static_cpu_has(X86_FEATURE_RDTSCP))
1451 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1453 svm->guest_state_loaded = true;
1456 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1458 struct vcpu_svm *svm = to_svm(vcpu);
1461 if (!svm->guest_state_loaded)
1465 * Certain MSRs are restored on VMEXIT (sev-es), or vmload of host save
1466 * area (non-sev-es). Restore the ones that weren't.
1468 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1469 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1471 svm->guest_state_loaded = false;
1474 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1476 struct vcpu_svm *svm = to_svm(vcpu);
1477 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1479 if (unlikely(cpu != vcpu->cpu)) {
1480 svm->asid_generation = 0;
1481 vmcb_mark_all_dirty(svm->vmcb);
1484 if (sd->current_vmcb != svm->vmcb) {
1485 sd->current_vmcb = svm->vmcb;
1486 indirect_branch_prediction_barrier();
1488 avic_vcpu_load(vcpu, cpu);
1491 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1493 avic_vcpu_put(vcpu);
1494 svm_prepare_host_switch(vcpu);
1496 ++vcpu->stat.host_state_reload;
1499 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1501 struct vcpu_svm *svm = to_svm(vcpu);
1502 unsigned long rflags = svm->vmcb->save.rflags;
1504 if (svm->nmi_singlestep) {
1505 /* Hide our flags if they were not set by the guest */
1506 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1507 rflags &= ~X86_EFLAGS_TF;
1508 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1509 rflags &= ~X86_EFLAGS_RF;
1514 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1516 if (to_svm(vcpu)->nmi_singlestep)
1517 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1520 * Any change of EFLAGS.VM is accompanied by a reload of SS
1521 * (caused by either a task switch or an inter-privilege IRET),
1522 * so we do not need to update the CPL here.
1524 to_svm(vcpu)->vmcb->save.rflags = rflags;
1527 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1530 case VCPU_EXREG_PDPTR:
1531 BUG_ON(!npt_enabled);
1532 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1539 static void svm_set_vintr(struct vcpu_svm *svm)
1541 struct vmcb_control_area *control;
1543 /* The following fields are ignored when AVIC is enabled */
1544 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1545 svm_set_intercept(svm, INTERCEPT_VINTR);
1548 * This is just a dummy VINTR to actually cause a vmexit to happen.
1549 * Actual injection of virtual interrupts happens through EVENTINJ.
1551 control = &svm->vmcb->control;
1552 control->int_vector = 0x0;
1553 control->int_ctl &= ~V_INTR_PRIO_MASK;
1554 control->int_ctl |= V_IRQ_MASK |
1555 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1556 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1559 static void svm_clear_vintr(struct vcpu_svm *svm)
1561 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1562 svm_clr_intercept(svm, INTERCEPT_VINTR);
1564 /* Drop int_ctl fields related to VINTR injection. */
1565 svm->vmcb->control.int_ctl &= mask;
1566 if (is_guest_mode(&svm->vcpu)) {
1567 svm->nested.hsave->control.int_ctl &= mask;
1569 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1570 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1571 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1574 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1577 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1579 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1582 case VCPU_SREG_CS: return &save->cs;
1583 case VCPU_SREG_DS: return &save->ds;
1584 case VCPU_SREG_ES: return &save->es;
1585 case VCPU_SREG_FS: return &save->fs;
1586 case VCPU_SREG_GS: return &save->gs;
1587 case VCPU_SREG_SS: return &save->ss;
1588 case VCPU_SREG_TR: return &save->tr;
1589 case VCPU_SREG_LDTR: return &save->ldtr;
1595 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1597 struct vmcb_seg *s = svm_seg(vcpu, seg);
1602 static void svm_get_segment(struct kvm_vcpu *vcpu,
1603 struct kvm_segment *var, int seg)
1605 struct vmcb_seg *s = svm_seg(vcpu, seg);
1607 var->base = s->base;
1608 var->limit = s->limit;
1609 var->selector = s->selector;
1610 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1611 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1612 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1613 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1614 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1615 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1616 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1619 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1620 * However, the SVM spec states that the G bit is not observed by the
1621 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1622 * So let's synthesize a legal G bit for all segments, this helps
1623 * running KVM nested. It also helps cross-vendor migration, because
1624 * Intel's vmentry has a check on the 'G' bit.
1626 var->g = s->limit > 0xfffff;
1629 * AMD's VMCB does not have an explicit unusable field, so emulate it
1630 * for cross vendor migration purposes by "not present"
1632 var->unusable = !var->present;
1637 * Work around a bug where the busy flag in the tr selector
1647 * The accessed bit must always be set in the segment
1648 * descriptor cache, although it can be cleared in the
1649 * descriptor, the cached bit always remains at 1. Since
1650 * Intel has a check on this, set it here to support
1651 * cross-vendor migration.
1658 * On AMD CPUs sometimes the DB bit in the segment
1659 * descriptor is left as 1, although the whole segment has
1660 * been made unusable. Clear it here to pass an Intel VMX
1661 * entry check when cross vendor migrating.
1665 /* This is symmetric with svm_set_segment() */
1666 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1671 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1673 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1678 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1680 struct vcpu_svm *svm = to_svm(vcpu);
1682 dt->size = svm->vmcb->save.idtr.limit;
1683 dt->address = svm->vmcb->save.idtr.base;
1686 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1688 struct vcpu_svm *svm = to_svm(vcpu);
1690 svm->vmcb->save.idtr.limit = dt->size;
1691 svm->vmcb->save.idtr.base = dt->address ;
1692 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1695 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1697 struct vcpu_svm *svm = to_svm(vcpu);
1699 dt->size = svm->vmcb->save.gdtr.limit;
1700 dt->address = svm->vmcb->save.gdtr.base;
1703 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1705 struct vcpu_svm *svm = to_svm(vcpu);
1707 svm->vmcb->save.gdtr.limit = dt->size;
1708 svm->vmcb->save.gdtr.base = dt->address ;
1709 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1712 static void update_cr0_intercept(struct vcpu_svm *svm)
1718 * SEV-ES guests must always keep the CR intercepts cleared. CR
1719 * tracking is done using the CR write traps.
1721 if (sev_es_guest(svm->vcpu.kvm))
1724 gcr0 = svm->vcpu.arch.cr0;
1725 hcr0 = &svm->vmcb->save.cr0;
1726 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1727 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1729 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1731 if (gcr0 == *hcr0) {
1732 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1733 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1735 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1736 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1740 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1742 struct vcpu_svm *svm = to_svm(vcpu);
1744 #ifdef CONFIG_X86_64
1745 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1746 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1747 vcpu->arch.efer |= EFER_LMA;
1748 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1751 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1752 vcpu->arch.efer &= ~EFER_LMA;
1753 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1757 vcpu->arch.cr0 = cr0;
1760 cr0 |= X86_CR0_PG | X86_CR0_WP;
1763 * re-enable caching here because the QEMU bios
1764 * does not do it - this results in some delay at
1767 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1768 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1769 svm->vmcb->save.cr0 = cr0;
1770 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1771 update_cr0_intercept(svm);
1774 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1779 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1781 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1782 unsigned long old_cr4 = vcpu->arch.cr4;
1784 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1785 svm_flush_tlb(vcpu);
1787 vcpu->arch.cr4 = cr4;
1790 cr4 |= host_cr4_mce;
1791 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1792 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1794 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1795 kvm_update_cpuid_runtime(vcpu);
1798 static void svm_set_segment(struct kvm_vcpu *vcpu,
1799 struct kvm_segment *var, int seg)
1801 struct vcpu_svm *svm = to_svm(vcpu);
1802 struct vmcb_seg *s = svm_seg(vcpu, seg);
1804 s->base = var->base;
1805 s->limit = var->limit;
1806 s->selector = var->selector;
1807 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1808 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1809 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1810 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1811 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1812 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1813 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1814 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1817 * This is always accurate, except if SYSRET returned to a segment
1818 * with SS.DPL != 3. Intel does not have this quirk, and always
1819 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1820 * would entail passing the CPL to userspace and back.
1822 if (seg == VCPU_SREG_SS)
1823 /* This is symmetric with svm_get_segment() */
1824 svm->vmcb->save.cpl = (var->dpl & 3);
1826 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1829 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1831 struct vcpu_svm *svm = to_svm(vcpu);
1833 clr_exception_intercept(svm, BP_VECTOR);
1835 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1836 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1837 set_exception_intercept(svm, BP_VECTOR);
1841 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1843 if (sd->next_asid > sd->max_asid) {
1844 ++sd->asid_generation;
1845 sd->next_asid = sd->min_asid;
1846 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1847 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1850 svm->asid_generation = sd->asid_generation;
1851 svm->asid = sd->next_asid++;
1854 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1856 struct vmcb *vmcb = svm->vmcb;
1858 if (svm->vcpu.arch.guest_state_protected)
1861 if (unlikely(value != vmcb->save.dr6)) {
1862 vmcb->save.dr6 = value;
1863 vmcb_mark_dirty(vmcb, VMCB_DR);
1867 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1869 struct vcpu_svm *svm = to_svm(vcpu);
1871 if (vcpu->arch.guest_state_protected)
1874 get_debugreg(vcpu->arch.db[0], 0);
1875 get_debugreg(vcpu->arch.db[1], 1);
1876 get_debugreg(vcpu->arch.db[2], 2);
1877 get_debugreg(vcpu->arch.db[3], 3);
1879 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1880 * because db_interception might need it. We can do it before vmentry.
1882 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1883 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1884 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1885 set_dr_intercepts(svm);
1888 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1890 struct vcpu_svm *svm = to_svm(vcpu);
1892 if (vcpu->arch.guest_state_protected)
1895 svm->vmcb->save.dr7 = value;
1896 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1899 static int pf_interception(struct vcpu_svm *svm)
1901 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1902 u64 error_code = svm->vmcb->control.exit_info_1;
1904 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1905 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1906 svm->vmcb->control.insn_bytes : NULL,
1907 svm->vmcb->control.insn_len);
1910 static int npf_interception(struct vcpu_svm *svm)
1912 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1913 u64 error_code = svm->vmcb->control.exit_info_1;
1915 trace_kvm_page_fault(fault_address, error_code);
1916 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1917 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1918 svm->vmcb->control.insn_bytes : NULL,
1919 svm->vmcb->control.insn_len);
1922 static int db_interception(struct vcpu_svm *svm)
1924 struct kvm_run *kvm_run = svm->vcpu.run;
1925 struct kvm_vcpu *vcpu = &svm->vcpu;
1927 if (!(svm->vcpu.guest_debug &
1928 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1929 !svm->nmi_singlestep) {
1930 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1931 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1935 if (svm->nmi_singlestep) {
1936 disable_nmi_singlestep(svm);
1937 /* Make sure we check for pending NMIs upon entry */
1938 kvm_make_request(KVM_REQ_EVENT, vcpu);
1941 if (svm->vcpu.guest_debug &
1942 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1943 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1944 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1945 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1946 kvm_run->debug.arch.pc =
1947 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1948 kvm_run->debug.arch.exception = DB_VECTOR;
1955 static int bp_interception(struct vcpu_svm *svm)
1957 struct kvm_run *kvm_run = svm->vcpu.run;
1959 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1960 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1961 kvm_run->debug.arch.exception = BP_VECTOR;
1965 static int ud_interception(struct vcpu_svm *svm)
1967 return handle_ud(&svm->vcpu);
1970 static int ac_interception(struct vcpu_svm *svm)
1972 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1976 static bool is_erratum_383(void)
1981 if (!erratum_383_found)
1984 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1988 /* Bit 62 may or may not be set for this mce */
1989 value &= ~(1ULL << 62);
1991 if (value != 0xb600000000010015ULL)
1994 /* Clear MCi_STATUS registers */
1995 for (i = 0; i < 6; ++i)
1996 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1998 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2002 value &= ~(1ULL << 2);
2003 low = lower_32_bits(value);
2004 high = upper_32_bits(value);
2006 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2009 /* Flush tlb to evict multi-match entries */
2015 static void svm_handle_mce(struct vcpu_svm *svm)
2017 if (is_erratum_383()) {
2019 * Erratum 383 triggered. Guest state is corrupt so kill the
2022 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2024 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2030 * On an #MC intercept the MCE handler is not called automatically in
2031 * the host. So do it by hand here.
2033 kvm_machine_check();
2036 static int mc_interception(struct vcpu_svm *svm)
2041 static int shutdown_interception(struct vcpu_svm *svm)
2043 struct kvm_run *kvm_run = svm->vcpu.run;
2046 * The VM save area has already been encrypted so it
2047 * cannot be reinitialized - just terminate.
2049 if (sev_es_guest(svm->vcpu.kvm))
2053 * VMCB is undefined after a SHUTDOWN intercept
2054 * so reinitialize it.
2056 clear_page(svm->vmcb);
2059 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2063 static int io_interception(struct vcpu_svm *svm)
2065 struct kvm_vcpu *vcpu = &svm->vcpu;
2066 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2067 int size, in, string;
2070 ++svm->vcpu.stat.io_exits;
2071 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2072 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2073 port = io_info >> 16;
2074 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2077 if (sev_es_guest(vcpu->kvm))
2078 return sev_es_string_io(svm, size, port, in);
2080 return kvm_emulate_instruction(vcpu, 0);
2083 svm->next_rip = svm->vmcb->control.exit_info_2;
2085 return kvm_fast_pio(&svm->vcpu, size, port, in);
2088 static int nmi_interception(struct vcpu_svm *svm)
2093 static int intr_interception(struct vcpu_svm *svm)
2095 ++svm->vcpu.stat.irq_exits;
2099 static int nop_on_interception(struct vcpu_svm *svm)
2104 static int halt_interception(struct vcpu_svm *svm)
2106 return kvm_emulate_halt(&svm->vcpu);
2109 static int vmmcall_interception(struct vcpu_svm *svm)
2111 return kvm_emulate_hypercall(&svm->vcpu);
2114 static int vmload_interception(struct vcpu_svm *svm)
2116 struct vmcb *nested_vmcb;
2117 struct kvm_host_map map;
2120 if (nested_svm_check_permissions(svm))
2123 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2126 kvm_inject_gp(&svm->vcpu, 0);
2130 nested_vmcb = map.hva;
2132 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2134 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2135 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2140 static int vmsave_interception(struct vcpu_svm *svm)
2142 struct vmcb *nested_vmcb;
2143 struct kvm_host_map map;
2146 if (nested_svm_check_permissions(svm))
2149 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2152 kvm_inject_gp(&svm->vcpu, 0);
2156 nested_vmcb = map.hva;
2158 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2160 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2161 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2166 static int vmrun_interception(struct vcpu_svm *svm)
2168 if (nested_svm_check_permissions(svm))
2171 return nested_svm_vmrun(svm);
2181 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2182 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2184 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2186 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2187 return NONE_SVM_INSTR;
2189 switch (ctxt->modrm) {
2190 case 0xd8: /* VMRUN */
2191 return SVM_INSTR_VMRUN;
2192 case 0xda: /* VMLOAD */
2193 return SVM_INSTR_VMLOAD;
2194 case 0xdb: /* VMSAVE */
2195 return SVM_INSTR_VMSAVE;
2200 return NONE_SVM_INSTR;
2203 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2205 const int guest_mode_exit_codes[] = {
2206 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2207 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2208 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2210 int (*const svm_instr_handlers[])(struct vcpu_svm *svm) = {
2211 [SVM_INSTR_VMRUN] = vmrun_interception,
2212 [SVM_INSTR_VMLOAD] = vmload_interception,
2213 [SVM_INSTR_VMSAVE] = vmsave_interception,
2215 struct vcpu_svm *svm = to_svm(vcpu);
2218 if (is_guest_mode(vcpu)) {
2219 svm->vmcb->control.exit_code = guest_mode_exit_codes[opcode];
2220 svm->vmcb->control.exit_info_1 = 0;
2221 svm->vmcb->control.exit_info_2 = 0;
2223 /* Returns '1' or -errno on failure, '0' on success. */
2224 ret = nested_svm_vmexit(svm);
2229 return svm_instr_handlers[opcode](svm);
2233 * #GP handling code. Note that #GP can be triggered under the following two
2235 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2236 * some AMD CPUs when EAX of these instructions are in the reserved memory
2237 * regions (e.g. SMM memory on host).
2238 * 2) VMware backdoor
2240 static int gp_interception(struct vcpu_svm *svm)
2242 struct kvm_vcpu *vcpu = &svm->vcpu;
2243 u32 error_code = svm->vmcb->control.exit_info_1;
2246 /* Both #GP cases have zero error_code */
2250 /* Decode the instruction for usage later */
2251 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2254 opcode = svm_instr_opcode(vcpu);
2256 if (opcode == NONE_SVM_INSTR) {
2257 if (!enable_vmware_backdoor)
2261 * VMware backdoor emulation on #GP interception only handles
2262 * IN{S}, OUT{S}, and RDPMC.
2264 if (!is_guest_mode(vcpu))
2265 return kvm_emulate_instruction(vcpu,
2266 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2268 return emulate_svm_instr(vcpu, opcode);
2271 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2275 void svm_set_gif(struct vcpu_svm *svm, bool value)
2279 * If VGIF is enabled, the STGI intercept is only added to
2280 * detect the opening of the SMI/NMI window; remove it now.
2281 * Likewise, clear the VINTR intercept, we will set it
2282 * again while processing KVM_REQ_EVENT if needed.
2284 if (vgif_enabled(svm))
2285 svm_clr_intercept(svm, INTERCEPT_STGI);
2286 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2287 svm_clear_vintr(svm);
2290 if (svm->vcpu.arch.smi_pending ||
2291 svm->vcpu.arch.nmi_pending ||
2292 kvm_cpu_has_injectable_intr(&svm->vcpu))
2293 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2298 * After a CLGI no interrupts should come. But if vGIF is
2299 * in use, we still rely on the VINTR intercept (rather than
2300 * STGI) to detect an open interrupt window.
2302 if (!vgif_enabled(svm))
2303 svm_clear_vintr(svm);
2307 static int stgi_interception(struct vcpu_svm *svm)
2311 if (nested_svm_check_permissions(svm))
2314 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2315 svm_set_gif(svm, true);
2319 static int clgi_interception(struct vcpu_svm *svm)
2323 if (nested_svm_check_permissions(svm))
2326 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2327 svm_set_gif(svm, false);
2331 static int invlpga_interception(struct vcpu_svm *svm)
2333 struct kvm_vcpu *vcpu = &svm->vcpu;
2335 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2336 kvm_rax_read(&svm->vcpu));
2338 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2339 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2341 return kvm_skip_emulated_instruction(&svm->vcpu);
2344 static int skinit_interception(struct vcpu_svm *svm)
2346 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2348 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2352 static int wbinvd_interception(struct vcpu_svm *svm)
2354 return kvm_emulate_wbinvd(&svm->vcpu);
2357 static int xsetbv_interception(struct vcpu_svm *svm)
2359 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2360 u32 index = kvm_rcx_read(&svm->vcpu);
2362 int err = kvm_set_xcr(&svm->vcpu, index, new_bv);
2363 return kvm_complete_insn_gp(&svm->vcpu, err);
2366 static int rdpru_interception(struct vcpu_svm *svm)
2368 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2372 static int task_switch_interception(struct vcpu_svm *svm)
2376 int int_type = svm->vmcb->control.exit_int_info &
2377 SVM_EXITINTINFO_TYPE_MASK;
2378 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2380 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2382 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2383 bool has_error_code = false;
2386 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2388 if (svm->vmcb->control.exit_info_2 &
2389 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2390 reason = TASK_SWITCH_IRET;
2391 else if (svm->vmcb->control.exit_info_2 &
2392 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2393 reason = TASK_SWITCH_JMP;
2395 reason = TASK_SWITCH_GATE;
2397 reason = TASK_SWITCH_CALL;
2399 if (reason == TASK_SWITCH_GATE) {
2401 case SVM_EXITINTINFO_TYPE_NMI:
2402 svm->vcpu.arch.nmi_injected = false;
2404 case SVM_EXITINTINFO_TYPE_EXEPT:
2405 if (svm->vmcb->control.exit_info_2 &
2406 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2407 has_error_code = true;
2409 (u32)svm->vmcb->control.exit_info_2;
2411 kvm_clear_exception_queue(&svm->vcpu);
2413 case SVM_EXITINTINFO_TYPE_INTR:
2414 kvm_clear_interrupt_queue(&svm->vcpu);
2421 if (reason != TASK_SWITCH_GATE ||
2422 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2423 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2424 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2425 if (!skip_emulated_instruction(&svm->vcpu))
2429 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2432 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2433 has_error_code, error_code);
2436 static int cpuid_interception(struct vcpu_svm *svm)
2438 return kvm_emulate_cpuid(&svm->vcpu);
2441 static int iret_interception(struct vcpu_svm *svm)
2443 ++svm->vcpu.stat.nmi_window_exits;
2444 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2445 if (!sev_es_guest(svm->vcpu.kvm)) {
2446 svm_clr_intercept(svm, INTERCEPT_IRET);
2447 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2449 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2453 static int invd_interception(struct vcpu_svm *svm)
2455 /* Treat an INVD instruction as a NOP and just skip it. */
2456 return kvm_skip_emulated_instruction(&svm->vcpu);
2459 static int invlpg_interception(struct vcpu_svm *svm)
2461 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2462 return kvm_emulate_instruction(&svm->vcpu, 0);
2464 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2465 return kvm_skip_emulated_instruction(&svm->vcpu);
2468 static int emulate_on_interception(struct vcpu_svm *svm)
2470 return kvm_emulate_instruction(&svm->vcpu, 0);
2473 static int rsm_interception(struct vcpu_svm *svm)
2475 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2478 static int rdpmc_interception(struct vcpu_svm *svm)
2483 return emulate_on_interception(svm);
2485 err = kvm_rdpmc(&svm->vcpu);
2486 return kvm_complete_insn_gp(&svm->vcpu, err);
2489 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2492 unsigned long cr0 = svm->vcpu.arch.cr0;
2495 if (!is_guest_mode(&svm->vcpu) ||
2496 (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2499 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2500 val &= ~SVM_CR0_SELECTIVE_MASK;
2503 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2504 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2510 #define CR_VALID (1ULL << 63)
2512 static int cr_interception(struct vcpu_svm *svm)
2518 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2519 return emulate_on_interception(svm);
2521 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2522 return emulate_on_interception(svm);
2524 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2525 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2526 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2528 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2531 if (cr >= 16) { /* mov to cr */
2533 val = kvm_register_read(&svm->vcpu, reg);
2534 trace_kvm_cr_write(cr, val);
2537 if (!check_selective_cr0_intercepted(svm, val))
2538 err = kvm_set_cr0(&svm->vcpu, val);
2544 err = kvm_set_cr3(&svm->vcpu, val);
2547 err = kvm_set_cr4(&svm->vcpu, val);
2550 err = kvm_set_cr8(&svm->vcpu, val);
2553 WARN(1, "unhandled write to CR%d", cr);
2554 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2557 } else { /* mov from cr */
2560 val = kvm_read_cr0(&svm->vcpu);
2563 val = svm->vcpu.arch.cr2;
2566 val = kvm_read_cr3(&svm->vcpu);
2569 val = kvm_read_cr4(&svm->vcpu);
2572 val = kvm_get_cr8(&svm->vcpu);
2575 WARN(1, "unhandled read from CR%d", cr);
2576 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2579 kvm_register_write(&svm->vcpu, reg, val);
2580 trace_kvm_cr_read(cr, val);
2582 return kvm_complete_insn_gp(&svm->vcpu, err);
2585 static int cr_trap(struct vcpu_svm *svm)
2587 struct kvm_vcpu *vcpu = &svm->vcpu;
2588 unsigned long old_value, new_value;
2592 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2594 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2597 old_value = kvm_read_cr0(vcpu);
2598 svm_set_cr0(vcpu, new_value);
2600 kvm_post_set_cr0(vcpu, old_value, new_value);
2603 old_value = kvm_read_cr4(vcpu);
2604 svm_set_cr4(vcpu, new_value);
2606 kvm_post_set_cr4(vcpu, old_value, new_value);
2609 ret = kvm_set_cr8(&svm->vcpu, new_value);
2612 WARN(1, "unhandled CR%d write trap", cr);
2613 kvm_queue_exception(vcpu, UD_VECTOR);
2617 return kvm_complete_insn_gp(vcpu, ret);
2620 static int dr_interception(struct vcpu_svm *svm)
2626 if (svm->vcpu.guest_debug == 0) {
2628 * No more DR vmexits; force a reload of the debug registers
2629 * and reenter on this instruction. The next vmexit will
2630 * retrieve the full state of the debug registers.
2632 clr_dr_intercepts(svm);
2633 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2637 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2638 return emulate_on_interception(svm);
2640 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2641 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2642 if (dr >= 16) { /* mov to DRn */
2644 val = kvm_register_read(&svm->vcpu, reg);
2645 err = kvm_set_dr(&svm->vcpu, dr, val);
2647 kvm_get_dr(&svm->vcpu, dr, &val);
2648 kvm_register_write(&svm->vcpu, reg, val);
2651 return kvm_complete_insn_gp(&svm->vcpu, err);
2654 static int cr8_write_interception(struct vcpu_svm *svm)
2656 struct kvm_run *kvm_run = svm->vcpu.run;
2659 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2660 /* instruction emulation calls kvm_set_cr8() */
2661 r = cr_interception(svm);
2662 if (lapic_in_kernel(&svm->vcpu))
2664 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2666 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2670 static int efer_trap(struct vcpu_svm *svm)
2672 struct msr_data msr_info;
2676 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2677 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2678 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2679 * the guest doesn't have X86_FEATURE_SVM.
2681 msr_info.host_initiated = false;
2682 msr_info.index = MSR_EFER;
2683 msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2684 ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2686 return kvm_complete_insn_gp(&svm->vcpu, ret);
2689 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2693 switch (msr->index) {
2694 case MSR_F10H_DECFG:
2695 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2696 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2698 case MSR_IA32_PERF_CAPABILITIES:
2701 return KVM_MSR_RET_INVALID;
2707 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2709 struct vcpu_svm *svm = to_svm(vcpu);
2711 switch (msr_info->index) {
2713 msr_info->data = svm->vmcb->save.star;
2715 #ifdef CONFIG_X86_64
2717 msr_info->data = svm->vmcb->save.lstar;
2720 msr_info->data = svm->vmcb->save.cstar;
2722 case MSR_KERNEL_GS_BASE:
2723 msr_info->data = svm->vmcb->save.kernel_gs_base;
2725 case MSR_SYSCALL_MASK:
2726 msr_info->data = svm->vmcb->save.sfmask;
2729 case MSR_IA32_SYSENTER_CS:
2730 msr_info->data = svm->vmcb->save.sysenter_cs;
2732 case MSR_IA32_SYSENTER_EIP:
2733 msr_info->data = svm->sysenter_eip;
2735 case MSR_IA32_SYSENTER_ESP:
2736 msr_info->data = svm->sysenter_esp;
2739 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2741 msr_info->data = svm->tsc_aux;
2744 * Nobody will change the following 5 values in the VMCB so we can
2745 * safely return them on rdmsr. They will always be 0 until LBRV is
2748 case MSR_IA32_DEBUGCTLMSR:
2749 msr_info->data = svm->vmcb->save.dbgctl;
2751 case MSR_IA32_LASTBRANCHFROMIP:
2752 msr_info->data = svm->vmcb->save.br_from;
2754 case MSR_IA32_LASTBRANCHTOIP:
2755 msr_info->data = svm->vmcb->save.br_to;
2757 case MSR_IA32_LASTINTFROMIP:
2758 msr_info->data = svm->vmcb->save.last_excp_from;
2760 case MSR_IA32_LASTINTTOIP:
2761 msr_info->data = svm->vmcb->save.last_excp_to;
2763 case MSR_VM_HSAVE_PA:
2764 msr_info->data = svm->nested.hsave_msr;
2767 msr_info->data = svm->nested.vm_cr_msr;
2769 case MSR_IA32_SPEC_CTRL:
2770 if (!msr_info->host_initiated &&
2771 !guest_has_spec_ctrl_msr(vcpu))
2774 msr_info->data = svm->spec_ctrl;
2776 case MSR_AMD64_VIRT_SPEC_CTRL:
2777 if (!msr_info->host_initiated &&
2778 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2781 msr_info->data = svm->virt_spec_ctrl;
2783 case MSR_F15H_IC_CFG: {
2787 family = guest_cpuid_family(vcpu);
2788 model = guest_cpuid_model(vcpu);
2790 if (family < 0 || model < 0)
2791 return kvm_get_msr_common(vcpu, msr_info);
2795 if (family == 0x15 &&
2796 (model >= 0x2 && model < 0x20))
2797 msr_info->data = 0x1E;
2800 case MSR_F10H_DECFG:
2801 msr_info->data = svm->msr_decfg;
2804 return kvm_get_msr_common(vcpu, msr_info);
2809 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2811 struct vcpu_svm *svm = to_svm(vcpu);
2812 if (!sev_es_guest(svm->vcpu.kvm) || !err)
2813 return kvm_complete_insn_gp(&svm->vcpu, err);
2815 ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2816 ghcb_set_sw_exit_info_2(svm->ghcb,
2818 SVM_EVTINJ_TYPE_EXEPT |
2823 static int rdmsr_interception(struct vcpu_svm *svm)
2825 return kvm_emulate_rdmsr(&svm->vcpu);
2828 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2830 struct vcpu_svm *svm = to_svm(vcpu);
2831 int svm_dis, chg_mask;
2833 if (data & ~SVM_VM_CR_VALID_MASK)
2836 chg_mask = SVM_VM_CR_VALID_MASK;
2838 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2839 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2841 svm->nested.vm_cr_msr &= ~chg_mask;
2842 svm->nested.vm_cr_msr |= (data & chg_mask);
2844 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2846 /* check for svm_disable while efer.svme is set */
2847 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2853 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2855 struct vcpu_svm *svm = to_svm(vcpu);
2857 u32 ecx = msr->index;
2858 u64 data = msr->data;
2860 case MSR_IA32_CR_PAT:
2861 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2863 vcpu->arch.pat = data;
2864 svm->vmcb->save.g_pat = data;
2865 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2867 case MSR_IA32_SPEC_CTRL:
2868 if (!msr->host_initiated &&
2869 !guest_has_spec_ctrl_msr(vcpu))
2872 if (kvm_spec_ctrl_test_value(data))
2875 svm->spec_ctrl = data;
2881 * When it's written (to non-zero) for the first time, pass
2885 * The handling of the MSR bitmap for L2 guests is done in
2886 * nested_svm_vmrun_msrpm.
2887 * We update the L1 MSR bit as well since it will end up
2888 * touching the MSR anyway now.
2890 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2892 case MSR_IA32_PRED_CMD:
2893 if (!msr->host_initiated &&
2894 !guest_has_pred_cmd_msr(vcpu))
2897 if (data & ~PRED_CMD_IBPB)
2899 if (!boot_cpu_has(X86_FEATURE_IBPB))
2904 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2905 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2907 case MSR_AMD64_VIRT_SPEC_CTRL:
2908 if (!msr->host_initiated &&
2909 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2912 if (data & ~SPEC_CTRL_SSBD)
2915 svm->virt_spec_ctrl = data;
2918 svm->vmcb->save.star = data;
2920 #ifdef CONFIG_X86_64
2922 svm->vmcb->save.lstar = data;
2925 svm->vmcb->save.cstar = data;
2927 case MSR_KERNEL_GS_BASE:
2928 svm->vmcb->save.kernel_gs_base = data;
2930 case MSR_SYSCALL_MASK:
2931 svm->vmcb->save.sfmask = data;
2934 case MSR_IA32_SYSENTER_CS:
2935 svm->vmcb->save.sysenter_cs = data;
2937 case MSR_IA32_SYSENTER_EIP:
2938 svm->sysenter_eip = data;
2939 svm->vmcb->save.sysenter_eip = data;
2941 case MSR_IA32_SYSENTER_ESP:
2942 svm->sysenter_esp = data;
2943 svm->vmcb->save.sysenter_esp = data;
2946 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2950 * This is rare, so we update the MSR here instead of using
2951 * direct_access_msrs. Doing that would require a rdmsr in
2954 svm->tsc_aux = data;
2955 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2957 case MSR_IA32_DEBUGCTLMSR:
2958 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2959 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2963 if (data & DEBUGCTL_RESERVED_BITS)
2966 svm->vmcb->save.dbgctl = data;
2967 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2968 if (data & (1ULL<<0))
2969 svm_enable_lbrv(vcpu);
2971 svm_disable_lbrv(vcpu);
2973 case MSR_VM_HSAVE_PA:
2974 svm->nested.hsave_msr = data;
2977 return svm_set_vm_cr(vcpu, data);
2979 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2981 case MSR_F10H_DECFG: {
2982 struct kvm_msr_entry msr_entry;
2984 msr_entry.index = msr->index;
2985 if (svm_get_msr_feature(&msr_entry))
2988 /* Check the supported bits */
2989 if (data & ~msr_entry.data)
2992 /* Don't allow the guest to change a bit, #GP */
2993 if (!msr->host_initiated && (data ^ msr_entry.data))
2996 svm->msr_decfg = data;
2999 case MSR_IA32_APICBASE:
3000 if (kvm_vcpu_apicv_active(vcpu))
3001 avic_update_vapic_bar(to_svm(vcpu), data);
3004 return kvm_set_msr_common(vcpu, msr);
3009 static int wrmsr_interception(struct vcpu_svm *svm)
3011 return kvm_emulate_wrmsr(&svm->vcpu);
3014 static int msr_interception(struct vcpu_svm *svm)
3016 if (svm->vmcb->control.exit_info_1)
3017 return wrmsr_interception(svm);
3019 return rdmsr_interception(svm);
3022 static int interrupt_window_interception(struct vcpu_svm *svm)
3024 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3025 svm_clear_vintr(svm);
3028 * For AVIC, the only reason to end up here is ExtINTs.
3029 * In this case AVIC was temporarily disabled for
3030 * requesting the IRQ window and we have to re-enable it.
3032 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
3034 ++svm->vcpu.stat.irq_window_exits;
3038 static int pause_interception(struct vcpu_svm *svm)
3040 struct kvm_vcpu *vcpu = &svm->vcpu;
3044 * CPL is not made available for an SEV-ES guest, therefore
3045 * vcpu->arch.preempted_in_kernel can never be true. Just
3046 * set in_kernel to false as well.
3048 in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
3050 if (!kvm_pause_in_guest(vcpu->kvm))
3051 grow_ple_window(vcpu);
3053 kvm_vcpu_on_spin(vcpu, in_kernel);
3057 static int nop_interception(struct vcpu_svm *svm)
3059 return kvm_skip_emulated_instruction(&(svm->vcpu));
3062 static int monitor_interception(struct vcpu_svm *svm)
3064 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
3065 return nop_interception(svm);
3068 static int mwait_interception(struct vcpu_svm *svm)
3070 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
3071 return nop_interception(svm);
3074 static int invpcid_interception(struct vcpu_svm *svm)
3076 struct kvm_vcpu *vcpu = &svm->vcpu;
3080 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3081 kvm_queue_exception(vcpu, UD_VECTOR);
3086 * For an INVPCID intercept:
3087 * EXITINFO1 provides the linear address of the memory operand.
3088 * EXITINFO2 provides the contents of the register operand.
3090 type = svm->vmcb->control.exit_info_2;
3091 gva = svm->vmcb->control.exit_info_1;
3094 kvm_inject_gp(vcpu, 0);
3098 return kvm_handle_invpcid(vcpu, type, gva);
3101 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
3102 [SVM_EXIT_READ_CR0] = cr_interception,
3103 [SVM_EXIT_READ_CR3] = cr_interception,
3104 [SVM_EXIT_READ_CR4] = cr_interception,
3105 [SVM_EXIT_READ_CR8] = cr_interception,
3106 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3107 [SVM_EXIT_WRITE_CR0] = cr_interception,
3108 [SVM_EXIT_WRITE_CR3] = cr_interception,
3109 [SVM_EXIT_WRITE_CR4] = cr_interception,
3110 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3111 [SVM_EXIT_READ_DR0] = dr_interception,
3112 [SVM_EXIT_READ_DR1] = dr_interception,
3113 [SVM_EXIT_READ_DR2] = dr_interception,
3114 [SVM_EXIT_READ_DR3] = dr_interception,
3115 [SVM_EXIT_READ_DR4] = dr_interception,
3116 [SVM_EXIT_READ_DR5] = dr_interception,
3117 [SVM_EXIT_READ_DR6] = dr_interception,
3118 [SVM_EXIT_READ_DR7] = dr_interception,
3119 [SVM_EXIT_WRITE_DR0] = dr_interception,
3120 [SVM_EXIT_WRITE_DR1] = dr_interception,
3121 [SVM_EXIT_WRITE_DR2] = dr_interception,
3122 [SVM_EXIT_WRITE_DR3] = dr_interception,
3123 [SVM_EXIT_WRITE_DR4] = dr_interception,
3124 [SVM_EXIT_WRITE_DR5] = dr_interception,
3125 [SVM_EXIT_WRITE_DR6] = dr_interception,
3126 [SVM_EXIT_WRITE_DR7] = dr_interception,
3127 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3128 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3129 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3130 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3131 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3132 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3133 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3134 [SVM_EXIT_INTR] = intr_interception,
3135 [SVM_EXIT_NMI] = nmi_interception,
3136 [SVM_EXIT_SMI] = nop_on_interception,
3137 [SVM_EXIT_INIT] = nop_on_interception,
3138 [SVM_EXIT_VINTR] = interrupt_window_interception,
3139 [SVM_EXIT_RDPMC] = rdpmc_interception,
3140 [SVM_EXIT_CPUID] = cpuid_interception,
3141 [SVM_EXIT_IRET] = iret_interception,
3142 [SVM_EXIT_INVD] = invd_interception,
3143 [SVM_EXIT_PAUSE] = pause_interception,
3144 [SVM_EXIT_HLT] = halt_interception,
3145 [SVM_EXIT_INVLPG] = invlpg_interception,
3146 [SVM_EXIT_INVLPGA] = invlpga_interception,
3147 [SVM_EXIT_IOIO] = io_interception,
3148 [SVM_EXIT_MSR] = msr_interception,
3149 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3150 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3151 [SVM_EXIT_VMRUN] = vmrun_interception,
3152 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3153 [SVM_EXIT_VMLOAD] = vmload_interception,
3154 [SVM_EXIT_VMSAVE] = vmsave_interception,
3155 [SVM_EXIT_STGI] = stgi_interception,
3156 [SVM_EXIT_CLGI] = clgi_interception,
3157 [SVM_EXIT_SKINIT] = skinit_interception,
3158 [SVM_EXIT_WBINVD] = wbinvd_interception,
3159 [SVM_EXIT_MONITOR] = monitor_interception,
3160 [SVM_EXIT_MWAIT] = mwait_interception,
3161 [SVM_EXIT_XSETBV] = xsetbv_interception,
3162 [SVM_EXIT_RDPRU] = rdpru_interception,
3163 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3164 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3165 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3166 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3167 [SVM_EXIT_INVPCID] = invpcid_interception,
3168 [SVM_EXIT_NPF] = npf_interception,
3169 [SVM_EXIT_RSM] = rsm_interception,
3170 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3171 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3172 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3175 static void dump_vmcb(struct kvm_vcpu *vcpu)
3177 struct vcpu_svm *svm = to_svm(vcpu);
3178 struct vmcb_control_area *control = &svm->vmcb->control;
3179 struct vmcb_save_area *save = &svm->vmcb->save;
3181 if (!dump_invalid_vmcb) {
3182 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3186 pr_err("VMCB Control Area:\n");
3187 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3188 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3189 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3190 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3191 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3192 pr_err("%-20s%08x %08x\n", "intercepts:",
3193 control->intercepts[INTERCEPT_WORD3],
3194 control->intercepts[INTERCEPT_WORD4]);
3195 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3196 pr_err("%-20s%d\n", "pause filter threshold:",
3197 control->pause_filter_thresh);
3198 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3199 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3200 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3201 pr_err("%-20s%d\n", "asid:", control->asid);
3202 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3203 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3204 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3205 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3206 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3207 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3208 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3209 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3210 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3211 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3212 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3213 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3214 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3215 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3216 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3217 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3218 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3219 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3220 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3221 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3222 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3223 pr_err("VMCB State Save Area:\n");
3224 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3226 save->es.selector, save->es.attrib,
3227 save->es.limit, save->es.base);
3228 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3230 save->cs.selector, save->cs.attrib,
3231 save->cs.limit, save->cs.base);
3232 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3234 save->ss.selector, save->ss.attrib,
3235 save->ss.limit, save->ss.base);
3236 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3238 save->ds.selector, save->ds.attrib,
3239 save->ds.limit, save->ds.base);
3240 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3242 save->fs.selector, save->fs.attrib,
3243 save->fs.limit, save->fs.base);
3244 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3246 save->gs.selector, save->gs.attrib,
3247 save->gs.limit, save->gs.base);
3248 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3250 save->gdtr.selector, save->gdtr.attrib,
3251 save->gdtr.limit, save->gdtr.base);
3252 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3254 save->ldtr.selector, save->ldtr.attrib,
3255 save->ldtr.limit, save->ldtr.base);
3256 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3258 save->idtr.selector, save->idtr.attrib,
3259 save->idtr.limit, save->idtr.base);
3260 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3262 save->tr.selector, save->tr.attrib,
3263 save->tr.limit, save->tr.base);
3264 pr_err("cpl: %d efer: %016llx\n",
3265 save->cpl, save->efer);
3266 pr_err("%-15s %016llx %-13s %016llx\n",
3267 "cr0:", save->cr0, "cr2:", save->cr2);
3268 pr_err("%-15s %016llx %-13s %016llx\n",
3269 "cr3:", save->cr3, "cr4:", save->cr4);
3270 pr_err("%-15s %016llx %-13s %016llx\n",
3271 "dr6:", save->dr6, "dr7:", save->dr7);
3272 pr_err("%-15s %016llx %-13s %016llx\n",
3273 "rip:", save->rip, "rflags:", save->rflags);
3274 pr_err("%-15s %016llx %-13s %016llx\n",
3275 "rsp:", save->rsp, "rax:", save->rax);
3276 pr_err("%-15s %016llx %-13s %016llx\n",
3277 "star:", save->star, "lstar:", save->lstar);
3278 pr_err("%-15s %016llx %-13s %016llx\n",
3279 "cstar:", save->cstar, "sfmask:", save->sfmask);
3280 pr_err("%-15s %016llx %-13s %016llx\n",
3281 "kernel_gs_base:", save->kernel_gs_base,
3282 "sysenter_cs:", save->sysenter_cs);
3283 pr_err("%-15s %016llx %-13s %016llx\n",
3284 "sysenter_esp:", save->sysenter_esp,
3285 "sysenter_eip:", save->sysenter_eip);
3286 pr_err("%-15s %016llx %-13s %016llx\n",
3287 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3288 pr_err("%-15s %016llx %-13s %016llx\n",
3289 "br_from:", save->br_from, "br_to:", save->br_to);
3290 pr_err("%-15s %016llx %-13s %016llx\n",
3291 "excp_from:", save->last_excp_from,
3292 "excp_to:", save->last_excp_to);
3295 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3297 if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3298 svm_exit_handlers[exit_code])
3301 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3303 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3304 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3305 vcpu->run->internal.ndata = 2;
3306 vcpu->run->internal.data[0] = exit_code;
3307 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3312 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3314 if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3317 #ifdef CONFIG_RETPOLINE
3318 if (exit_code == SVM_EXIT_MSR)
3319 return msr_interception(svm);
3320 else if (exit_code == SVM_EXIT_VINTR)
3321 return interrupt_window_interception(svm);
3322 else if (exit_code == SVM_EXIT_INTR)
3323 return intr_interception(svm);
3324 else if (exit_code == SVM_EXIT_HLT)
3325 return halt_interception(svm);
3326 else if (exit_code == SVM_EXIT_NPF)
3327 return npf_interception(svm);
3329 return svm_exit_handlers[exit_code](svm);
3332 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3333 u32 *intr_info, u32 *error_code)
3335 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3337 *info1 = control->exit_info_1;
3338 *info2 = control->exit_info_2;
3339 *intr_info = control->exit_int_info;
3340 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3341 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3342 *error_code = control->exit_int_info_err;
3347 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3349 struct vcpu_svm *svm = to_svm(vcpu);
3350 struct kvm_run *kvm_run = vcpu->run;
3351 u32 exit_code = svm->vmcb->control.exit_code;
3353 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3355 /* SEV-ES guests must use the CR write traps to track CR registers. */
3356 if (!sev_es_guest(vcpu->kvm)) {
3357 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3358 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3360 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3363 if (is_guest_mode(vcpu)) {
3366 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3368 vmexit = nested_svm_exit_special(svm);
3370 if (vmexit == NESTED_EXIT_CONTINUE)
3371 vmexit = nested_svm_exit_handled(svm);
3373 if (vmexit == NESTED_EXIT_DONE)
3377 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3378 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3379 kvm_run->fail_entry.hardware_entry_failure_reason
3380 = svm->vmcb->control.exit_code;
3381 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3386 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3387 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3388 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3389 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3390 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3392 __func__, svm->vmcb->control.exit_int_info,
3395 if (exit_fastpath != EXIT_FASTPATH_NONE)
3398 return svm_invoke_exit_handler(svm, exit_code);
3401 static void reload_tss(struct kvm_vcpu *vcpu)
3403 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3405 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3409 static void pre_svm_run(struct vcpu_svm *svm)
3411 struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3413 if (sev_guest(svm->vcpu.kvm))
3414 return pre_sev_run(svm, svm->vcpu.cpu);
3416 /* FIXME: handle wraparound of asid_generation */
3417 if (svm->asid_generation != sd->asid_generation)
3421 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3423 struct vcpu_svm *svm = to_svm(vcpu);
3425 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3426 vcpu->arch.hflags |= HF_NMI_MASK;
3427 if (!sev_es_guest(svm->vcpu.kvm))
3428 svm_set_intercept(svm, INTERCEPT_IRET);
3429 ++vcpu->stat.nmi_injections;
3432 static void svm_set_irq(struct kvm_vcpu *vcpu)
3434 struct vcpu_svm *svm = to_svm(vcpu);
3436 BUG_ON(!(gif_set(svm)));
3438 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3439 ++vcpu->stat.irq_injections;
3441 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3442 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3445 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3447 struct vcpu_svm *svm = to_svm(vcpu);
3450 * SEV-ES guests must always keep the CR intercepts cleared. CR
3451 * tracking is done using the CR write traps.
3453 if (sev_es_guest(vcpu->kvm))
3456 if (nested_svm_virtualize_tpr(vcpu))
3459 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3465 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3468 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3470 struct vcpu_svm *svm = to_svm(vcpu);
3471 struct vmcb *vmcb = svm->vmcb;
3477 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3480 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3481 (svm->vcpu.arch.hflags & HF_NMI_MASK);
3486 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3488 struct vcpu_svm *svm = to_svm(vcpu);
3489 if (svm->nested.nested_run_pending)
3492 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3493 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3496 return !svm_nmi_blocked(vcpu);
3499 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3501 struct vcpu_svm *svm = to_svm(vcpu);
3503 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3506 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3508 struct vcpu_svm *svm = to_svm(vcpu);
3511 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3512 if (!sev_es_guest(svm->vcpu.kvm))
3513 svm_set_intercept(svm, INTERCEPT_IRET);
3515 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3516 if (!sev_es_guest(svm->vcpu.kvm))
3517 svm_clr_intercept(svm, INTERCEPT_IRET);
3521 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3523 struct vcpu_svm *svm = to_svm(vcpu);
3524 struct vmcb *vmcb = svm->vmcb;
3529 if (sev_es_guest(svm->vcpu.kvm)) {
3531 * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3532 * bit to determine the state of the IF flag.
3534 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3536 } else if (is_guest_mode(vcpu)) {
3537 /* As long as interrupts are being delivered... */
3538 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3539 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3540 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3543 /* ... vmexits aren't blocked by the interrupt shadow */
3544 if (nested_exit_on_intr(svm))
3547 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3551 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3554 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3556 struct vcpu_svm *svm = to_svm(vcpu);
3557 if (svm->nested.nested_run_pending)
3561 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3562 * e.g. if the IRQ arrived asynchronously after checking nested events.
3564 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3567 return !svm_interrupt_blocked(vcpu);
3570 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3572 struct vcpu_svm *svm = to_svm(vcpu);
3575 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3576 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3577 * get that intercept, this function will be called again though and
3578 * we'll get the vintr intercept. However, if the vGIF feature is
3579 * enabled, the STGI interception will not occur. Enable the irq
3580 * window under the assumption that the hardware will set the GIF.
3582 if (vgif_enabled(svm) || gif_set(svm)) {
3584 * IRQ window is not needed when AVIC is enabled,
3585 * unless we have pending ExtINT since it cannot be injected
3586 * via AVIC. In such case, we need to temporarily disable AVIC,
3587 * and fallback to injecting IRQ via V_IRQ.
3589 svm_toggle_avic_for_irq_window(vcpu, false);
3594 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3596 struct vcpu_svm *svm = to_svm(vcpu);
3598 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3600 return; /* IRET will cause a vm exit */
3602 if (!gif_set(svm)) {
3603 if (vgif_enabled(svm))
3604 svm_set_intercept(svm, INTERCEPT_STGI);
3605 return; /* STGI will cause a vm exit */
3609 * Something prevents NMI from been injected. Single step over possible
3610 * problem (IRET or exception injection or interrupt shadow)
3612 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3613 svm->nmi_singlestep = true;
3614 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3617 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3622 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3627 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3629 struct vcpu_svm *svm = to_svm(vcpu);
3632 * Flush only the current ASID even if the TLB flush was invoked via
3633 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3634 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3635 * unconditionally does a TLB flush on both nested VM-Enter and nested
3636 * VM-Exit (via kvm_mmu_reset_context()).
3638 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3639 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3641 svm->asid_generation--;
3644 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3646 struct vcpu_svm *svm = to_svm(vcpu);
3648 invlpga(gva, svm->vmcb->control.asid);
3651 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3653 struct vcpu_svm *svm = to_svm(vcpu);
3655 if (nested_svm_virtualize_tpr(vcpu))
3658 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3659 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3660 kvm_set_cr8(vcpu, cr8);
3664 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3666 struct vcpu_svm *svm = to_svm(vcpu);
3669 if (nested_svm_virtualize_tpr(vcpu) ||
3670 kvm_vcpu_apicv_active(vcpu))
3673 cr8 = kvm_get_cr8(vcpu);
3674 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3675 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3678 static void svm_complete_interrupts(struct vcpu_svm *svm)
3682 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3683 unsigned int3_injected = svm->int3_injected;
3685 svm->int3_injected = 0;
3688 * If we've made progress since setting HF_IRET_MASK, we've
3689 * executed an IRET and can allow NMI injection.
3691 if ((svm->vcpu.arch.hflags & HF_IRET_MASK) &&
3692 (sev_es_guest(svm->vcpu.kvm) ||
3693 kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip)) {
3694 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3695 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3698 svm->vcpu.arch.nmi_injected = false;
3699 kvm_clear_exception_queue(&svm->vcpu);
3700 kvm_clear_interrupt_queue(&svm->vcpu);
3702 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3705 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3707 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3708 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3711 case SVM_EXITINTINFO_TYPE_NMI:
3712 svm->vcpu.arch.nmi_injected = true;
3714 case SVM_EXITINTINFO_TYPE_EXEPT:
3716 * Never re-inject a #VC exception.
3718 if (vector == X86_TRAP_VC)
3722 * In case of software exceptions, do not reinject the vector,
3723 * but re-execute the instruction instead. Rewind RIP first
3724 * if we emulated INT3 before.
3726 if (kvm_exception_is_soft(vector)) {
3727 if (vector == BP_VECTOR && int3_injected &&
3728 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3729 kvm_rip_write(&svm->vcpu,
3730 kvm_rip_read(&svm->vcpu) -
3734 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3735 u32 err = svm->vmcb->control.exit_int_info_err;
3736 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3739 kvm_requeue_exception(&svm->vcpu, vector);
3741 case SVM_EXITINTINFO_TYPE_INTR:
3742 kvm_queue_interrupt(&svm->vcpu, vector, false);
3749 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3751 struct vcpu_svm *svm = to_svm(vcpu);
3752 struct vmcb_control_area *control = &svm->vmcb->control;
3754 control->exit_int_info = control->event_inj;
3755 control->exit_int_info_err = control->event_inj_err;
3756 control->event_inj = 0;
3757 svm_complete_interrupts(svm);
3760 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3762 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3763 to_svm(vcpu)->vmcb->control.exit_info_1)
3764 return handle_fastpath_set_msr_irqoff(vcpu);
3766 return EXIT_FASTPATH_NONE;
3769 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3770 struct vcpu_svm *svm)
3773 * VMENTER enables interrupts (host state), but the kernel state is
3774 * interrupts disabled when this is invoked. Also tell RCU about
3775 * it. This is the same logic as for exit_to_user_mode().
3777 * This ensures that e.g. latency analysis on the host observes
3778 * guest mode as interrupt enabled.
3780 * guest_enter_irqoff() informs context tracking about the
3781 * transition to guest mode and if enabled adjusts RCU state
3784 instrumentation_begin();
3785 trace_hardirqs_on_prepare();
3786 lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3787 instrumentation_end();
3789 guest_enter_irqoff();
3790 lockdep_hardirqs_on(CALLER_ADDR0);
3792 if (sev_es_guest(svm->vcpu.kvm)) {
3793 __svm_sev_es_vcpu_run(svm->vmcb_pa);
3795 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3797 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3799 vmload(__sme_page_pa(sd->save_area));
3803 * VMEXIT disables interrupts (host state), but tracing and lockdep
3804 * have them in state 'on' as recorded before entering guest mode.
3805 * Same as enter_from_user_mode().
3807 * guest_exit_irqoff() restores host context and reinstates RCU if
3808 * enabled and required.
3810 * This needs to be done before the below as native_read_msr()
3811 * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3812 * into world and some more.
3814 lockdep_hardirqs_off(CALLER_ADDR0);
3815 guest_exit_irqoff();
3817 instrumentation_begin();
3818 trace_hardirqs_off_finish();
3819 instrumentation_end();
3822 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3824 struct vcpu_svm *svm = to_svm(vcpu);
3826 trace_kvm_entry(vcpu);
3828 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3829 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3830 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3833 * Disable singlestep if we're injecting an interrupt/exception.
3834 * We don't want our modified rflags to be pushed on the stack where
3835 * we might not be able to easily reset them if we disabled NMI
3838 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3840 * Event injection happens before external interrupts cause a
3841 * vmexit and interrupts are disabled here, so smp_send_reschedule
3842 * is enough to force an immediate vmexit.
3844 disable_nmi_singlestep(svm);
3845 smp_send_reschedule(vcpu->cpu);
3850 sync_lapic_to_cr8(vcpu);
3852 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3853 svm->vmcb->control.asid = svm->asid;
3854 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3856 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3859 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3862 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3863 svm_set_dr6(svm, vcpu->arch.dr6);
3865 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3868 kvm_load_guest_xsave_state(vcpu);
3870 kvm_wait_lapic_expire(vcpu);
3873 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3874 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3875 * is no need to worry about the conditional branch over the wrmsr
3876 * being speculatively taken.
3878 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3880 svm_vcpu_enter_exit(vcpu, svm);
3883 * We do not use IBRS in the kernel. If this vCPU has used the
3884 * SPEC_CTRL MSR it may have left it on; save the value and
3885 * turn it off. This is much more efficient than blindly adding
3886 * it to the atomic save/restore list. Especially as the former
3887 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3889 * For non-nested case:
3890 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3894 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3897 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3898 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3900 if (!sev_es_guest(svm->vcpu.kvm))
3903 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3905 if (!sev_es_guest(svm->vcpu.kvm)) {
3906 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3907 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3908 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3909 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3912 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3913 kvm_before_interrupt(&svm->vcpu);
3915 kvm_load_host_xsave_state(vcpu);
3918 /* Any pending NMI will happen here */
3920 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3921 kvm_after_interrupt(&svm->vcpu);
3923 sync_cr8_to_lapic(vcpu);
3926 if (is_guest_mode(&svm->vcpu)) {
3927 sync_nested_vmcb_control(svm);
3928 svm->nested.nested_run_pending = 0;
3931 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3932 vmcb_mark_all_clean(svm->vmcb);
3934 /* if exit due to PF check for async PF */
3935 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3936 svm->vcpu.arch.apf.host_apf_flags =
3937 kvm_read_and_reset_apf_flags();
3940 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3941 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3945 * We need to handle MC intercepts here before the vcpu has a chance to
3946 * change the physical cpu
3948 if (unlikely(svm->vmcb->control.exit_code ==
3949 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3950 svm_handle_mce(svm);
3952 svm_complete_interrupts(svm);
3954 if (is_guest_mode(vcpu))
3955 return EXIT_FASTPATH_NONE;
3957 return svm_exit_handlers_fastpath(vcpu);
3960 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3963 struct vcpu_svm *svm = to_svm(vcpu);
3966 cr3 = __sme_set(root);
3968 svm->vmcb->control.nested_cr3 = cr3;
3969 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3971 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3972 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3974 cr3 = vcpu->arch.cr3;
3977 svm->vmcb->save.cr3 = cr3;
3978 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3981 static int is_disabled(void)
3985 rdmsrl(MSR_VM_CR, vm_cr);
3986 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3993 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3996 * Patch in the VMMCALL instruction:
3998 hypercall[0] = 0x0f;
3999 hypercall[1] = 0x01;
4000 hypercall[2] = 0xd9;
4003 static int __init svm_check_processor_compat(void)
4008 static bool svm_cpu_has_accelerated_tpr(void)
4014 * The kvm parameter can be NULL (module initialization, or invocation before
4015 * VM creation). Be sure to check the kvm parameter before using it.
4017 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4020 case MSR_IA32_MCG_EXT_CTL:
4021 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4023 case MSR_IA32_SMBASE:
4024 /* SEV-ES guests do not support SMM, so report false */
4025 if (kvm && sev_es_guest(kvm))
4035 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4040 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4042 struct vcpu_svm *svm = to_svm(vcpu);
4043 struct kvm_cpuid_entry2 *best;
4045 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4046 boot_cpu_has(X86_FEATURE_XSAVE) &&
4047 boot_cpu_has(X86_FEATURE_XSAVES);
4049 /* Update nrips enabled cache */
4050 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4051 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
4053 /* Check again if INVPCID interception if required */
4054 svm_check_invpcid(svm);
4056 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4057 if (sev_guest(vcpu->kvm)) {
4058 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
4060 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4063 if (!kvm_vcpu_apicv_active(vcpu))
4067 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
4068 * is exposed to the guest, disable AVIC.
4070 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
4071 kvm_request_apicv_update(vcpu->kvm, false,
4072 APICV_INHIBIT_REASON_X2APIC);
4075 * Currently, AVIC does not work with nested virtualization.
4076 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
4078 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4079 kvm_request_apicv_update(vcpu->kvm, false,
4080 APICV_INHIBIT_REASON_NESTED);
4083 static bool svm_has_wbinvd_exit(void)
4088 #define PRE_EX(exit) { .exit_code = (exit), \
4089 .stage = X86_ICPT_PRE_EXCEPT, }
4090 #define POST_EX(exit) { .exit_code = (exit), \
4091 .stage = X86_ICPT_POST_EXCEPT, }
4092 #define POST_MEM(exit) { .exit_code = (exit), \
4093 .stage = X86_ICPT_POST_MEMACCESS, }
4095 static const struct __x86_intercept {
4097 enum x86_intercept_stage stage;
4098 } x86_intercept_map[] = {
4099 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4100 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4101 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4102 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4103 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4104 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4105 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4106 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4107 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4108 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4109 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4110 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4111 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4112 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4113 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4114 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4115 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4116 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4117 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4118 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4119 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4120 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4121 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4122 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4123 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4124 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4125 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4126 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4127 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4128 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4129 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4130 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4131 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4132 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4133 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4134 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4135 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4136 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4137 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4138 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4139 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4140 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4141 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4142 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4143 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4144 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4145 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4152 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4153 struct x86_instruction_info *info,
4154 enum x86_intercept_stage stage,
4155 struct x86_exception *exception)
4157 struct vcpu_svm *svm = to_svm(vcpu);
4158 int vmexit, ret = X86EMUL_CONTINUE;
4159 struct __x86_intercept icpt_info;
4160 struct vmcb *vmcb = svm->vmcb;
4162 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4165 icpt_info = x86_intercept_map[info->intercept];
4167 if (stage != icpt_info.stage)
4170 switch (icpt_info.exit_code) {
4171 case SVM_EXIT_READ_CR0:
4172 if (info->intercept == x86_intercept_cr_read)
4173 icpt_info.exit_code += info->modrm_reg;
4175 case SVM_EXIT_WRITE_CR0: {
4176 unsigned long cr0, val;
4178 if (info->intercept == x86_intercept_cr_write)
4179 icpt_info.exit_code += info->modrm_reg;
4181 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4182 info->intercept == x86_intercept_clts)
4185 if (!(vmcb_is_intercept(&svm->nested.ctl,
4186 INTERCEPT_SELECTIVE_CR0)))
4189 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4190 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4192 if (info->intercept == x86_intercept_lmsw) {
4195 /* lmsw can't clear PE - catch this here */
4196 if (cr0 & X86_CR0_PE)
4201 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4205 case SVM_EXIT_READ_DR0:
4206 case SVM_EXIT_WRITE_DR0:
4207 icpt_info.exit_code += info->modrm_reg;
4210 if (info->intercept == x86_intercept_wrmsr)
4211 vmcb->control.exit_info_1 = 1;
4213 vmcb->control.exit_info_1 = 0;
4215 case SVM_EXIT_PAUSE:
4217 * We get this for NOP only, but pause
4218 * is rep not, check this here
4220 if (info->rep_prefix != REPE_PREFIX)
4223 case SVM_EXIT_IOIO: {
4227 if (info->intercept == x86_intercept_in ||
4228 info->intercept == x86_intercept_ins) {
4229 exit_info = ((info->src_val & 0xffff) << 16) |
4231 bytes = info->dst_bytes;
4233 exit_info = (info->dst_val & 0xffff) << 16;
4234 bytes = info->src_bytes;
4237 if (info->intercept == x86_intercept_outs ||
4238 info->intercept == x86_intercept_ins)
4239 exit_info |= SVM_IOIO_STR_MASK;
4241 if (info->rep_prefix)
4242 exit_info |= SVM_IOIO_REP_MASK;
4244 bytes = min(bytes, 4u);
4246 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4248 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4250 vmcb->control.exit_info_1 = exit_info;
4251 vmcb->control.exit_info_2 = info->next_rip;
4259 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4260 if (static_cpu_has(X86_FEATURE_NRIPS))
4261 vmcb->control.next_rip = info->next_rip;
4262 vmcb->control.exit_code = icpt_info.exit_code;
4263 vmexit = nested_svm_exit_handled(svm);
4265 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4272 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4276 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4278 if (!kvm_pause_in_guest(vcpu->kvm))
4279 shrink_ple_window(vcpu);
4282 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4284 /* [63:9] are reserved. */
4285 vcpu->arch.mcg_cap &= 0x1ff;
4288 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4290 struct vcpu_svm *svm = to_svm(vcpu);
4292 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4296 return is_smm(vcpu);
4299 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4301 struct vcpu_svm *svm = to_svm(vcpu);
4302 if (svm->nested.nested_run_pending)
4305 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4306 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4309 return !svm_smi_blocked(vcpu);
4312 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4314 struct vcpu_svm *svm = to_svm(vcpu);
4317 if (is_guest_mode(vcpu)) {
4318 /* FED8h - SVM Guest */
4319 put_smstate(u64, smstate, 0x7ed8, 1);
4320 /* FEE0h - SVM Guest VMCB Physical Address */
4321 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4323 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4324 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4325 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4327 ret = nested_svm_vmexit(svm);
4334 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4336 struct vcpu_svm *svm = to_svm(vcpu);
4337 struct kvm_host_map map;
4340 if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4341 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4342 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4343 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4346 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4349 if (!(saved_efer & EFER_SVME))
4352 if (kvm_vcpu_map(&svm->vcpu,
4353 gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4356 if (svm_allocate_nested(svm))
4359 ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4360 kvm_vcpu_unmap(&svm->vcpu, &map, true);
4367 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4369 struct vcpu_svm *svm = to_svm(vcpu);
4371 if (!gif_set(svm)) {
4372 if (vgif_enabled(svm))
4373 svm_set_intercept(svm, INTERCEPT_STGI);
4374 /* STGI will cause a vm exit */
4376 /* We must be in SMM; RSM will cause a vmexit anyway. */
4380 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4382 bool smep, smap, is_user;
4386 * When the guest is an SEV-ES guest, emulation is not possible.
4388 if (sev_es_guest(vcpu->kvm))
4392 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4395 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4396 * possible that CPU microcode implementing DecodeAssist will fail
4397 * to read bytes of instruction which caused #NPF. In this case,
4398 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4399 * return 0 instead of the correct guest instruction bytes.
4401 * This happens because CPU microcode reading instruction bytes
4402 * uses a special opcode which attempts to read data using CPL=0
4403 * privileges. The microcode reads CS:RIP and if it hits a SMAP
4404 * fault, it gives up and returns no instruction bytes.
4407 * We reach here in case CPU supports DecodeAssist, raised #NPF and
4408 * returned 0 in GuestIntrBytes field of the VMCB.
4409 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4410 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4411 * in case vCPU CPL==3 (Because otherwise guest would have triggered
4412 * a SMEP fault instead of #NPF).
4413 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4414 * As most guests enable SMAP if they have also enabled SMEP, use above
4415 * logic in order to attempt minimize false-positive of detecting errata
4416 * while still preserving all cases semantic correctness.
4419 * To determine what instruction the guest was executing, the hypervisor
4420 * will have to decode the instruction at the instruction pointer.
4422 * In non SEV guest, hypervisor will be able to read the guest
4423 * memory to decode the instruction pointer when insn_len is zero
4424 * so we return true to indicate that decoding is possible.
4426 * But in the SEV guest, the guest memory is encrypted with the
4427 * guest specific key and hypervisor will not be able to decode the
4428 * instruction pointer so we will not able to workaround it. Lets
4429 * print the error and request to kill the guest.
4431 if (likely(!insn || insn_len))
4435 * If RIP is invalid, go ahead with emulation which will cause an
4436 * internal error exit.
4438 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4441 cr4 = kvm_read_cr4(vcpu);
4442 smep = cr4 & X86_CR4_SMEP;
4443 smap = cr4 & X86_CR4_SMAP;
4444 is_user = svm_get_cpl(vcpu) == 3;
4445 if (smap && (!smep || is_user)) {
4446 if (!sev_guest(vcpu->kvm))
4449 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4450 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4456 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4458 struct vcpu_svm *svm = to_svm(vcpu);
4461 * TODO: Last condition latch INIT signals on vCPU when
4462 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4463 * To properly emulate the INIT intercept,
4464 * svm_check_nested_events() should call nested_svm_vmexit()
4465 * if an INIT signal is pending.
4467 return !gif_set(svm) ||
4468 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4471 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4473 if (!sev_es_guest(vcpu->kvm))
4474 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4476 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4479 static void svm_vm_destroy(struct kvm *kvm)
4481 avic_vm_destroy(kvm);
4482 sev_vm_destroy(kvm);
4485 static int svm_vm_init(struct kvm *kvm)
4487 if (!pause_filter_count || !pause_filter_thresh)
4488 kvm->arch.pause_in_guest = true;
4491 int ret = avic_vm_init(kvm);
4496 kvm_apicv_init(kvm, avic);
4500 static struct kvm_x86_ops svm_x86_ops __initdata = {
4501 .hardware_unsetup = svm_hardware_teardown,
4502 .hardware_enable = svm_hardware_enable,
4503 .hardware_disable = svm_hardware_disable,
4504 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4505 .has_emulated_msr = svm_has_emulated_msr,
4507 .vcpu_create = svm_create_vcpu,
4508 .vcpu_free = svm_free_vcpu,
4509 .vcpu_reset = svm_vcpu_reset,
4511 .vm_size = sizeof(struct kvm_svm),
4512 .vm_init = svm_vm_init,
4513 .vm_destroy = svm_vm_destroy,
4515 .prepare_guest_switch = svm_prepare_guest_switch,
4516 .vcpu_load = svm_vcpu_load,
4517 .vcpu_put = svm_vcpu_put,
4518 .vcpu_blocking = svm_vcpu_blocking,
4519 .vcpu_unblocking = svm_vcpu_unblocking,
4521 .update_exception_bitmap = svm_update_exception_bitmap,
4522 .get_msr_feature = svm_get_msr_feature,
4523 .get_msr = svm_get_msr,
4524 .set_msr = svm_set_msr,
4525 .get_segment_base = svm_get_segment_base,
4526 .get_segment = svm_get_segment,
4527 .set_segment = svm_set_segment,
4528 .get_cpl = svm_get_cpl,
4529 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4530 .set_cr0 = svm_set_cr0,
4531 .is_valid_cr4 = svm_is_valid_cr4,
4532 .set_cr4 = svm_set_cr4,
4533 .set_efer = svm_set_efer,
4534 .get_idt = svm_get_idt,
4535 .set_idt = svm_set_idt,
4536 .get_gdt = svm_get_gdt,
4537 .set_gdt = svm_set_gdt,
4538 .set_dr7 = svm_set_dr7,
4539 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4540 .cache_reg = svm_cache_reg,
4541 .get_rflags = svm_get_rflags,
4542 .set_rflags = svm_set_rflags,
4544 .tlb_flush_all = svm_flush_tlb,
4545 .tlb_flush_current = svm_flush_tlb,
4546 .tlb_flush_gva = svm_flush_tlb_gva,
4547 .tlb_flush_guest = svm_flush_tlb,
4549 .run = svm_vcpu_run,
4550 .handle_exit = handle_exit,
4551 .skip_emulated_instruction = skip_emulated_instruction,
4552 .update_emulated_instruction = NULL,
4553 .set_interrupt_shadow = svm_set_interrupt_shadow,
4554 .get_interrupt_shadow = svm_get_interrupt_shadow,
4555 .patch_hypercall = svm_patch_hypercall,
4556 .set_irq = svm_set_irq,
4557 .set_nmi = svm_inject_nmi,
4558 .queue_exception = svm_queue_exception,
4559 .cancel_injection = svm_cancel_injection,
4560 .interrupt_allowed = svm_interrupt_allowed,
4561 .nmi_allowed = svm_nmi_allowed,
4562 .get_nmi_mask = svm_get_nmi_mask,
4563 .set_nmi_mask = svm_set_nmi_mask,
4564 .enable_nmi_window = svm_enable_nmi_window,
4565 .enable_irq_window = svm_enable_irq_window,
4566 .update_cr8_intercept = svm_update_cr8_intercept,
4567 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4568 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4569 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4570 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4571 .load_eoi_exitmap = svm_load_eoi_exitmap,
4572 .hwapic_irr_update = svm_hwapic_irr_update,
4573 .hwapic_isr_update = svm_hwapic_isr_update,
4574 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4575 .apicv_post_state_restore = avic_post_state_restore,
4577 .set_tss_addr = svm_set_tss_addr,
4578 .set_identity_map_addr = svm_set_identity_map_addr,
4579 .get_mt_mask = svm_get_mt_mask,
4581 .get_exit_info = svm_get_exit_info,
4583 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4585 .has_wbinvd_exit = svm_has_wbinvd_exit,
4587 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4589 .load_mmu_pgd = svm_load_mmu_pgd,
4591 .check_intercept = svm_check_intercept,
4592 .handle_exit_irqoff = svm_handle_exit_irqoff,
4594 .request_immediate_exit = __kvm_request_immediate_exit,
4596 .sched_in = svm_sched_in,
4598 .pmu_ops = &amd_pmu_ops,
4599 .nested_ops = &svm_nested_ops,
4601 .deliver_posted_interrupt = svm_deliver_avic_intr,
4602 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4603 .update_pi_irte = svm_update_pi_irte,
4604 .setup_mce = svm_setup_mce,
4606 .smi_allowed = svm_smi_allowed,
4607 .pre_enter_smm = svm_pre_enter_smm,
4608 .pre_leave_smm = svm_pre_leave_smm,
4609 .enable_smi_window = svm_enable_smi_window,
4611 .mem_enc_op = svm_mem_enc_op,
4612 .mem_enc_reg_region = svm_register_enc_region,
4613 .mem_enc_unreg_region = svm_unregister_enc_region,
4615 .can_emulate_instruction = svm_can_emulate_instruction,
4617 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4619 .msr_filter_changed = svm_msr_filter_changed,
4620 .complete_emulated_msr = svm_complete_emulated_msr,
4622 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4625 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4626 .cpu_has_kvm_support = has_svm,
4627 .disabled_by_bios = is_disabled,
4628 .hardware_setup = svm_hardware_setup,
4629 .check_processor_compatibility = svm_check_processor_compat,
4631 .runtime_ops = &svm_x86_ops,
4634 static int __init svm_init(void)
4636 __unused_size_checks();
4638 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4639 __alignof__(struct vcpu_svm), THIS_MODULE);
4642 static void __exit svm_exit(void)
4647 module_init(svm_init)
4648 module_exit(svm_exit)