1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/frame.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
37 #include <asm/spec-ctrl.h>
38 #include <asm/cpu_device_id.h>
40 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
51 static const struct x86_cpu_id svm_cpu_id[] = {
52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
64 #define SVM_FEATURE_LBRV (1 << 1)
65 #define SVM_FEATURE_SVML (1 << 2)
66 #define SVM_FEATURE_TSC_RATE (1 << 4)
67 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
69 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
70 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78 static bool erratum_383_found __read_mostly;
80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
86 static uint64_t osvw_len = 4, osvw_status;
88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
91 static const struct svm_direct_access_msrs {
92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94 } direct_access_msrs[] = {
95 { .index = MSR_STAR, .always = true },
96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
106 { .index = MSR_IA32_PRED_CMD, .always = false },
107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 bool npt_enabled = true;
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152 module_param(pause_filter_thresh, ushort, 0444);
154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155 module_param(pause_filter_count, ushort, 0444);
157 /* Default doubles per-vcpu window every exit. */
158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159 module_param(pause_filter_count_grow, ushort, 0444);
161 /* Default resets per-vcpu window every exit to pause_filter_count. */
162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163 module_param(pause_filter_count_shrink, ushort, 0444);
165 /* Default is to compute the maximum so we can never overflow. */
166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167 module_param(pause_filter_count_max, ushort, 0444);
169 /* allow nested paging (virtualized MMU) for all guests */
170 static int npt = true;
171 module_param(npt, int, S_IRUGO);
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
189 /* enable/disable SEV support */
190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191 module_param(sev, int, 0444);
193 static bool __read_mostly dump_invalid_vmcb = 0;
194 module_param(dump_invalid_vmcb, bool, 0644);
196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
198 static void svm_complete_interrupts(struct vcpu_svm *svm);
200 static unsigned long iopm_base;
202 struct kvm_ldttss_desc {
205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
209 } __attribute__((packed));
211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
216 #define MSRS_RANGE_SIZE 2048
217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
219 u32 svm_msrpm_offset(u32 msr)
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
232 /* Now we have the u8 offset - but need the u32 offset */
236 /* MSR not in any range */
240 #define MAX_INST_SIZE 15
242 static inline void clgi(void)
244 asm volatile (__ex("clgi"));
247 static inline void stgi(void)
249 asm volatile (__ex("stgi"));
252 static inline void invlpga(unsigned long addr, u32 asid)
254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
257 static int get_npt_level(struct kvm_vcpu *vcpu)
260 return PT64_ROOT_4LEVEL;
262 return PT32E_ROOT_LEVEL;
266 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
268 vcpu->arch.efer = efer;
271 /* Shadow paging assumes NX to be available. */
274 if (!(efer & EFER_LMA))
278 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
279 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
282 static int is_external_interrupt(u32 info)
284 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
285 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
288 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
290 struct vcpu_svm *svm = to_svm(vcpu);
293 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
294 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
298 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
300 struct vcpu_svm *svm = to_svm(vcpu);
303 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
305 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
309 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
311 struct vcpu_svm *svm = to_svm(vcpu);
313 if (nrips && svm->vmcb->control.next_rip != 0) {
314 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
315 svm->next_rip = svm->vmcb->control.next_rip;
318 if (!svm->next_rip) {
319 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
322 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
323 pr_err("%s: ip 0x%lx next 0x%llx\n",
324 __func__, kvm_rip_read(vcpu), svm->next_rip);
325 kvm_rip_write(vcpu, svm->next_rip);
327 svm_set_interrupt_shadow(vcpu, 0);
332 static void svm_queue_exception(struct kvm_vcpu *vcpu)
334 struct vcpu_svm *svm = to_svm(vcpu);
335 unsigned nr = vcpu->arch.exception.nr;
336 bool has_error_code = vcpu->arch.exception.has_error_code;
337 bool reinject = vcpu->arch.exception.injected;
338 u32 error_code = vcpu->arch.exception.error_code;
341 * If we are within a nested VM we'd better #VMEXIT and let the guest
342 * handle the exception
345 nested_svm_check_exception(svm, nr, has_error_code, error_code))
348 kvm_deliver_exception_payload(&svm->vcpu);
350 if (nr == BP_VECTOR && !nrips) {
351 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
354 * For guest debugging where we have to reinject #BP if some
355 * INT3 is guest-owned:
356 * Emulate nRIP by moving RIP forward. Will fail if injection
357 * raises a fault that is not intercepted. Still better than
358 * failing in all cases.
360 (void)skip_emulated_instruction(&svm->vcpu);
361 rip = kvm_rip_read(&svm->vcpu);
362 svm->int3_rip = rip + svm->vmcb->save.cs.base;
363 svm->int3_injected = rip - old_rip;
366 svm->vmcb->control.event_inj = nr
368 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
369 | SVM_EVTINJ_TYPE_EXEPT;
370 svm->vmcb->control.event_inj_err = error_code;
373 static void svm_init_erratum_383(void)
379 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
382 /* Use _safe variants to not break nested virtualization */
383 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
389 low = lower_32_bits(val);
390 high = upper_32_bits(val);
392 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
394 erratum_383_found = true;
397 static void svm_init_osvw(struct kvm_vcpu *vcpu)
400 * Guests should see errata 400 and 415 as fixed (assuming that
401 * HLT and IO instructions are intercepted).
403 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
404 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
407 * By increasing VCPU's osvw.length to 3 we are telling the guest that
408 * all osvw.status bits inside that length, including bit 0 (which is
409 * reserved for erratum 298), are valid. However, if host processor's
410 * osvw_len is 0 then osvw_status[0] carries no information. We need to
411 * be conservative here and therefore we tell the guest that erratum 298
412 * is present (because we really don't know).
414 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
415 vcpu->arch.osvw.status |= 1;
418 static int has_svm(void)
422 if (!cpu_has_svm(&msg)) {
423 printk(KERN_INFO "has_svm: %s\n", msg);
430 static void svm_hardware_disable(void)
432 /* Make sure we clean up behind us */
433 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
434 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
438 amd_pmu_disable_virt();
441 static int svm_hardware_enable(void)
444 struct svm_cpu_data *sd;
446 struct desc_struct *gdt;
447 int me = raw_smp_processor_id();
449 rdmsrl(MSR_EFER, efer);
450 if (efer & EFER_SVME)
454 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
457 sd = per_cpu(svm_data, me);
459 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
463 sd->asid_generation = 1;
464 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
465 sd->next_asid = sd->max_asid + 1;
466 sd->min_asid = max_sev_asid + 1;
468 gdt = get_current_gdt_rw();
469 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
471 wrmsrl(MSR_EFER, efer | EFER_SVME);
473 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
475 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
476 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
477 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
484 * Note that it is possible to have a system with mixed processor
485 * revisions and therefore different OSVW bits. If bits are not the same
486 * on different processors then choose the worst case (i.e. if erratum
487 * is present on one processor and not on another then assume that the
488 * erratum is present everywhere).
490 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
491 uint64_t len, status = 0;
494 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
496 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
500 osvw_status = osvw_len = 0;
504 osvw_status |= status;
505 osvw_status &= (1ULL << osvw_len) - 1;
508 osvw_status = osvw_len = 0;
510 svm_init_erratum_383();
512 amd_pmu_enable_virt();
517 static void svm_cpu_uninit(int cpu)
519 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
524 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
525 kfree(sd->sev_vmcbs);
526 __free_page(sd->save_area);
530 static int svm_cpu_init(int cpu)
532 struct svm_cpu_data *sd;
534 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
538 sd->save_area = alloc_page(GFP_KERNEL);
542 if (svm_sev_enabled()) {
543 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
550 per_cpu(svm_data, cpu) = sd;
555 __free_page(sd->save_area);
562 static bool valid_msr_intercept(u32 index)
566 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
567 if (direct_access_msrs[i].index == index)
573 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
580 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
583 offset = svm_msrpm_offset(msr);
584 bit_write = 2 * (msr & 0x0f) + 1;
587 BUG_ON(offset == MSR_INVALID);
589 return !!test_bit(bit_write, &tmp);
592 static void set_msr_interception(u32 *msrpm, unsigned msr,
595 u8 bit_read, bit_write;
600 * If this warning triggers extend the direct_access_msrs list at the
601 * beginning of the file
603 WARN_ON(!valid_msr_intercept(msr));
605 offset = svm_msrpm_offset(msr);
606 bit_read = 2 * (msr & 0x0f);
607 bit_write = 2 * (msr & 0x0f) + 1;
610 BUG_ON(offset == MSR_INVALID);
612 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
613 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
618 static void svm_vcpu_init_msrpm(u32 *msrpm)
622 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
624 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
625 if (!direct_access_msrs[i].always)
628 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
632 static void add_msr_offset(u32 offset)
636 for (i = 0; i < MSRPM_OFFSETS; ++i) {
638 /* Offset already in list? */
639 if (msrpm_offsets[i] == offset)
642 /* Slot used by another offset? */
643 if (msrpm_offsets[i] != MSR_INVALID)
646 /* Add offset to list */
647 msrpm_offsets[i] = offset;
653 * If this BUG triggers the msrpm_offsets table has an overflow. Just
654 * increase MSRPM_OFFSETS in this case.
659 static void init_msrpm_offsets(void)
663 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
665 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
668 offset = svm_msrpm_offset(direct_access_msrs[i].index);
669 BUG_ON(offset == MSR_INVALID);
671 add_msr_offset(offset);
675 static void svm_enable_lbrv(struct vcpu_svm *svm)
677 u32 *msrpm = svm->msrpm;
679 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
680 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
681 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
682 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
683 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
686 static void svm_disable_lbrv(struct vcpu_svm *svm)
688 u32 *msrpm = svm->msrpm;
690 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
691 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
692 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
693 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
694 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
697 void disable_nmi_singlestep(struct vcpu_svm *svm)
699 svm->nmi_singlestep = false;
701 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
702 /* Clear our flags if they were not set by the guest */
703 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
704 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
705 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
706 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
710 static void grow_ple_window(struct kvm_vcpu *vcpu)
712 struct vcpu_svm *svm = to_svm(vcpu);
713 struct vmcb_control_area *control = &svm->vmcb->control;
714 int old = control->pause_filter_count;
716 control->pause_filter_count = __grow_ple_window(old,
718 pause_filter_count_grow,
719 pause_filter_count_max);
721 if (control->pause_filter_count != old) {
722 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
723 trace_kvm_ple_window_update(vcpu->vcpu_id,
724 control->pause_filter_count, old);
728 static void shrink_ple_window(struct kvm_vcpu *vcpu)
730 struct vcpu_svm *svm = to_svm(vcpu);
731 struct vmcb_control_area *control = &svm->vmcb->control;
732 int old = control->pause_filter_count;
734 control->pause_filter_count =
735 __shrink_ple_window(old,
737 pause_filter_count_shrink,
739 if (control->pause_filter_count != old) {
740 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
741 trace_kvm_ple_window_update(vcpu->vcpu_id,
742 control->pause_filter_count, old);
747 * The default MMIO mask is a single bit (excluding the present bit),
748 * which could conflict with the memory encryption bit. Check for
749 * memory encryption support and override the default MMIO mask if
750 * memory encryption is enabled.
752 static __init void svm_adjust_mmio_mask(void)
754 unsigned int enc_bit, mask_bit;
757 /* If there is no memory encryption support, use existing mask */
758 if (cpuid_eax(0x80000000) < 0x8000001f)
761 /* If memory encryption is not enabled, use existing mask */
762 rdmsrl(MSR_K8_SYSCFG, msr);
763 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
766 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
767 mask_bit = boot_cpu_data.x86_phys_bits;
769 /* Increment the mask bit if it is the same as the encryption bit */
770 if (enc_bit == mask_bit)
774 * If the mask bit location is below 52, then some bits above the
775 * physical addressing limit will always be reserved, so use the
776 * rsvd_bits() function to generate the mask. This mask, along with
777 * the present bit, will be used to generate a page fault with
780 * If the mask bit location is 52 (or above), then clear the mask.
782 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
784 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
787 static void svm_hardware_teardown(void)
791 if (svm_sev_enabled())
792 sev_hardware_teardown();
794 for_each_possible_cpu(cpu)
797 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
801 static __init void svm_set_cpu_caps(void)
807 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
809 kvm_cpu_cap_set(X86_FEATURE_SVM);
812 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
815 kvm_cpu_cap_set(X86_FEATURE_NPT);
818 /* CPUID 0x80000008 */
819 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
820 boot_cpu_has(X86_FEATURE_AMD_SSBD))
821 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
824 static __init int svm_hardware_setup(void)
827 struct page *iopm_pages;
831 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
836 iopm_va = page_address(iopm_pages);
837 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
838 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
840 init_msrpm_offsets();
842 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
844 if (boot_cpu_has(X86_FEATURE_NX))
845 kvm_enable_efer_bits(EFER_NX);
847 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
848 kvm_enable_efer_bits(EFER_FFXSR);
850 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
851 kvm_has_tsc_control = true;
852 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
853 kvm_tsc_scaling_ratio_frac_bits = 32;
856 /* Check for pause filtering support */
857 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
858 pause_filter_count = 0;
859 pause_filter_thresh = 0;
860 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
861 pause_filter_thresh = 0;
865 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
866 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
870 if (boot_cpu_has(X86_FEATURE_SEV) &&
871 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
872 r = sev_hardware_setup();
880 svm_adjust_mmio_mask();
882 for_each_possible_cpu(cpu) {
883 r = svm_cpu_init(cpu);
888 if (!boot_cpu_has(X86_FEATURE_NPT))
891 if (npt_enabled && !npt)
894 kvm_configure_mmu(npt_enabled, PT_PDPE_LEVEL);
895 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
898 if (!boot_cpu_has(X86_FEATURE_NRIPS))
904 !boot_cpu_has(X86_FEATURE_AVIC) ||
905 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
908 pr_info("AVIC enabled\n");
910 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
916 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
917 !IS_ENABLED(CONFIG_X86_64)) {
920 pr_info("Virtual VMLOAD VMSAVE supported\n");
925 if (!boot_cpu_has(X86_FEATURE_VGIF))
928 pr_info("Virtual GIF supported\n");
936 svm_hardware_teardown();
940 static void init_seg(struct vmcb_seg *seg)
943 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
944 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
949 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
952 seg->attrib = SVM_SELECTOR_P_MASK | type;
957 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
959 struct vcpu_svm *svm = to_svm(vcpu);
961 if (is_guest_mode(vcpu))
962 return svm->nested.hsave->control.tsc_offset;
964 return vcpu->arch.tsc_offset;
967 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
969 struct vcpu_svm *svm = to_svm(vcpu);
970 u64 g_tsc_offset = 0;
972 if (is_guest_mode(vcpu)) {
973 /* Write L1's TSC offset. */
974 g_tsc_offset = svm->vmcb->control.tsc_offset -
975 svm->nested.hsave->control.tsc_offset;
976 svm->nested.hsave->control.tsc_offset = offset;
979 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
980 svm->vmcb->control.tsc_offset - g_tsc_offset,
983 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
985 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
986 return svm->vmcb->control.tsc_offset;
989 static void init_vmcb(struct vcpu_svm *svm)
991 struct vmcb_control_area *control = &svm->vmcb->control;
992 struct vmcb_save_area *save = &svm->vmcb->save;
994 svm->vcpu.arch.hflags = 0;
996 set_cr_intercept(svm, INTERCEPT_CR0_READ);
997 set_cr_intercept(svm, INTERCEPT_CR3_READ);
998 set_cr_intercept(svm, INTERCEPT_CR4_READ);
999 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1000 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1001 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1002 if (!kvm_vcpu_apicv_active(&svm->vcpu))
1003 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1005 set_dr_intercepts(svm);
1007 set_exception_intercept(svm, PF_VECTOR);
1008 set_exception_intercept(svm, UD_VECTOR);
1009 set_exception_intercept(svm, MC_VECTOR);
1010 set_exception_intercept(svm, AC_VECTOR);
1011 set_exception_intercept(svm, DB_VECTOR);
1013 * Guest access to VMware backdoor ports could legitimately
1014 * trigger #GP because of TSS I/O permission bitmap.
1015 * We intercept those #GP and allow access to them anyway
1018 if (enable_vmware_backdoor)
1019 set_exception_intercept(svm, GP_VECTOR);
1021 set_intercept(svm, INTERCEPT_INTR);
1022 set_intercept(svm, INTERCEPT_NMI);
1023 set_intercept(svm, INTERCEPT_SMI);
1024 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1025 set_intercept(svm, INTERCEPT_RDPMC);
1026 set_intercept(svm, INTERCEPT_CPUID);
1027 set_intercept(svm, INTERCEPT_INVD);
1028 set_intercept(svm, INTERCEPT_INVLPG);
1029 set_intercept(svm, INTERCEPT_INVLPGA);
1030 set_intercept(svm, INTERCEPT_IOIO_PROT);
1031 set_intercept(svm, INTERCEPT_MSR_PROT);
1032 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1033 set_intercept(svm, INTERCEPT_SHUTDOWN);
1034 set_intercept(svm, INTERCEPT_VMRUN);
1035 set_intercept(svm, INTERCEPT_VMMCALL);
1036 set_intercept(svm, INTERCEPT_VMLOAD);
1037 set_intercept(svm, INTERCEPT_VMSAVE);
1038 set_intercept(svm, INTERCEPT_STGI);
1039 set_intercept(svm, INTERCEPT_CLGI);
1040 set_intercept(svm, INTERCEPT_SKINIT);
1041 set_intercept(svm, INTERCEPT_WBINVD);
1042 set_intercept(svm, INTERCEPT_XSETBV);
1043 set_intercept(svm, INTERCEPT_RDPRU);
1044 set_intercept(svm, INTERCEPT_RSM);
1046 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1047 set_intercept(svm, INTERCEPT_MONITOR);
1048 set_intercept(svm, INTERCEPT_MWAIT);
1051 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1052 set_intercept(svm, INTERCEPT_HLT);
1054 control->iopm_base_pa = __sme_set(iopm_base);
1055 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1056 control->int_ctl = V_INTR_MASKING_MASK;
1058 init_seg(&save->es);
1059 init_seg(&save->ss);
1060 init_seg(&save->ds);
1061 init_seg(&save->fs);
1062 init_seg(&save->gs);
1064 save->cs.selector = 0xf000;
1065 save->cs.base = 0xffff0000;
1066 /* Executable/Readable Code Segment */
1067 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1068 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1069 save->cs.limit = 0xffff;
1071 save->gdtr.limit = 0xffff;
1072 save->idtr.limit = 0xffff;
1074 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1075 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1077 svm_set_efer(&svm->vcpu, 0);
1078 save->dr6 = 0xffff0ff0;
1079 kvm_set_rflags(&svm->vcpu, 2);
1080 save->rip = 0x0000fff0;
1081 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1084 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1085 * It also updates the guest-visible cr0 value.
1087 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1088 kvm_mmu_reset_context(&svm->vcpu);
1090 save->cr4 = X86_CR4_PAE;
1094 /* Setup VMCB for Nested Paging */
1095 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1096 clr_intercept(svm, INTERCEPT_INVLPG);
1097 clr_exception_intercept(svm, PF_VECTOR);
1098 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1099 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1100 save->g_pat = svm->vcpu.arch.pat;
1104 svm->asid_generation = 0;
1106 svm->nested.vmcb = 0;
1107 svm->vcpu.arch.hflags = 0;
1109 if (pause_filter_count) {
1110 control->pause_filter_count = pause_filter_count;
1111 if (pause_filter_thresh)
1112 control->pause_filter_thresh = pause_filter_thresh;
1113 set_intercept(svm, INTERCEPT_PAUSE);
1115 clr_intercept(svm, INTERCEPT_PAUSE);
1118 if (kvm_vcpu_apicv_active(&svm->vcpu))
1119 avic_init_vmcb(svm);
1122 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1123 * in VMCB and clear intercepts to avoid #VMEXIT.
1126 clr_intercept(svm, INTERCEPT_VMLOAD);
1127 clr_intercept(svm, INTERCEPT_VMSAVE);
1128 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1132 clr_intercept(svm, INTERCEPT_STGI);
1133 clr_intercept(svm, INTERCEPT_CLGI);
1134 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1137 if (sev_guest(svm->vcpu.kvm)) {
1138 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1139 clr_exception_intercept(svm, UD_VECTOR);
1142 mark_all_dirty(svm->vmcb);
1148 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1150 struct vcpu_svm *svm = to_svm(vcpu);
1155 svm->virt_spec_ctrl = 0;
1158 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1159 MSR_IA32_APICBASE_ENABLE;
1160 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1161 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1165 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1166 kvm_rdx_write(vcpu, eax);
1168 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1169 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1172 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1174 struct vcpu_svm *svm;
1176 struct page *msrpm_pages;
1177 struct page *hsave_page;
1178 struct page *nested_msrpm_pages;
1181 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1185 page = alloc_page(GFP_KERNEL_ACCOUNT);
1189 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1193 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1194 if (!nested_msrpm_pages)
1197 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
1201 err = avic_init_vcpu(svm);
1205 /* We initialize this flag to true to make sure that the is_running
1206 * bit would be set the first time the vcpu is loaded.
1208 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1209 svm->avic_is_running = true;
1211 svm->nested.hsave = page_address(hsave_page);
1213 svm->msrpm = page_address(msrpm_pages);
1214 svm_vcpu_init_msrpm(svm->msrpm);
1216 svm->nested.msrpm = page_address(nested_msrpm_pages);
1217 svm_vcpu_init_msrpm(svm->nested.msrpm);
1219 svm->vmcb = page_address(page);
1220 clear_page(svm->vmcb);
1221 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1222 svm->asid_generation = 0;
1225 svm_init_osvw(vcpu);
1226 vcpu->arch.microcode_version = 0x01000065;
1231 __free_page(hsave_page);
1233 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1235 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1242 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1246 for_each_online_cpu(i)
1247 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1250 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1252 struct vcpu_svm *svm = to_svm(vcpu);
1255 * The vmcb page can be recycled, causing a false negative in
1256 * svm_vcpu_load(). So, ensure that no logical CPU has this
1257 * vmcb page recorded as its current vmcb.
1259 svm_clear_current_vmcb(svm->vmcb);
1261 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1262 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1263 __free_page(virt_to_page(svm->nested.hsave));
1264 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1267 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1269 struct vcpu_svm *svm = to_svm(vcpu);
1270 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1273 if (unlikely(cpu != vcpu->cpu)) {
1274 svm->asid_generation = 0;
1275 mark_all_dirty(svm->vmcb);
1278 #ifdef CONFIG_X86_64
1279 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1281 savesegment(fs, svm->host.fs);
1282 savesegment(gs, svm->host.gs);
1283 svm->host.ldt = kvm_read_ldt();
1285 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1286 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1288 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1289 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1290 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1291 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1292 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1295 /* This assumes that the kernel never uses MSR_TSC_AUX */
1296 if (static_cpu_has(X86_FEATURE_RDTSCP))
1297 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1299 if (sd->current_vmcb != svm->vmcb) {
1300 sd->current_vmcb = svm->vmcb;
1301 indirect_branch_prediction_barrier();
1303 avic_vcpu_load(vcpu, cpu);
1306 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1308 struct vcpu_svm *svm = to_svm(vcpu);
1311 avic_vcpu_put(vcpu);
1313 ++vcpu->stat.host_state_reload;
1314 kvm_load_ldt(svm->host.ldt);
1315 #ifdef CONFIG_X86_64
1316 loadsegment(fs, svm->host.fs);
1317 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1318 load_gs_index(svm->host.gs);
1320 #ifdef CONFIG_X86_32_LAZY_GS
1321 loadsegment(gs, svm->host.gs);
1324 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1325 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1328 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1330 struct vcpu_svm *svm = to_svm(vcpu);
1331 unsigned long rflags = svm->vmcb->save.rflags;
1333 if (svm->nmi_singlestep) {
1334 /* Hide our flags if they were not set by the guest */
1335 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1336 rflags &= ~X86_EFLAGS_TF;
1337 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1338 rflags &= ~X86_EFLAGS_RF;
1343 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1345 if (to_svm(vcpu)->nmi_singlestep)
1346 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1349 * Any change of EFLAGS.VM is accompanied by a reload of SS
1350 * (caused by either a task switch or an inter-privilege IRET),
1351 * so we do not need to update the CPL here.
1353 to_svm(vcpu)->vmcb->save.rflags = rflags;
1356 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1359 case VCPU_EXREG_PDPTR:
1360 BUG_ON(!npt_enabled);
1361 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1368 static inline void svm_enable_vintr(struct vcpu_svm *svm)
1370 struct vmcb_control_area *control;
1372 /* The following fields are ignored when AVIC is enabled */
1373 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1376 * This is just a dummy VINTR to actually cause a vmexit to happen.
1377 * Actual injection of virtual interrupts happens through EVENTINJ.
1379 control = &svm->vmcb->control;
1380 control->int_vector = 0x0;
1381 control->int_ctl &= ~V_INTR_PRIO_MASK;
1382 control->int_ctl |= V_IRQ_MASK |
1383 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1384 mark_dirty(svm->vmcb, VMCB_INTR);
1387 static void svm_set_vintr(struct vcpu_svm *svm)
1389 set_intercept(svm, INTERCEPT_VINTR);
1390 if (is_intercept(svm, INTERCEPT_VINTR))
1391 svm_enable_vintr(svm);
1394 static void svm_clear_vintr(struct vcpu_svm *svm)
1396 clr_intercept(svm, INTERCEPT_VINTR);
1398 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1399 mark_dirty(svm->vmcb, VMCB_INTR);
1402 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1404 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1407 case VCPU_SREG_CS: return &save->cs;
1408 case VCPU_SREG_DS: return &save->ds;
1409 case VCPU_SREG_ES: return &save->es;
1410 case VCPU_SREG_FS: return &save->fs;
1411 case VCPU_SREG_GS: return &save->gs;
1412 case VCPU_SREG_SS: return &save->ss;
1413 case VCPU_SREG_TR: return &save->tr;
1414 case VCPU_SREG_LDTR: return &save->ldtr;
1420 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1422 struct vmcb_seg *s = svm_seg(vcpu, seg);
1427 static void svm_get_segment(struct kvm_vcpu *vcpu,
1428 struct kvm_segment *var, int seg)
1430 struct vmcb_seg *s = svm_seg(vcpu, seg);
1432 var->base = s->base;
1433 var->limit = s->limit;
1434 var->selector = s->selector;
1435 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1436 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1437 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1438 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1439 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1440 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1441 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1444 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1445 * However, the SVM spec states that the G bit is not observed by the
1446 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1447 * So let's synthesize a legal G bit for all segments, this helps
1448 * running KVM nested. It also helps cross-vendor migration, because
1449 * Intel's vmentry has a check on the 'G' bit.
1451 var->g = s->limit > 0xfffff;
1454 * AMD's VMCB does not have an explicit unusable field, so emulate it
1455 * for cross vendor migration purposes by "not present"
1457 var->unusable = !var->present;
1462 * Work around a bug where the busy flag in the tr selector
1472 * The accessed bit must always be set in the segment
1473 * descriptor cache, although it can be cleared in the
1474 * descriptor, the cached bit always remains at 1. Since
1475 * Intel has a check on this, set it here to support
1476 * cross-vendor migration.
1483 * On AMD CPUs sometimes the DB bit in the segment
1484 * descriptor is left as 1, although the whole segment has
1485 * been made unusable. Clear it here to pass an Intel VMX
1486 * entry check when cross vendor migrating.
1490 /* This is symmetric with svm_set_segment() */
1491 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1496 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1498 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1503 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1505 struct vcpu_svm *svm = to_svm(vcpu);
1507 dt->size = svm->vmcb->save.idtr.limit;
1508 dt->address = svm->vmcb->save.idtr.base;
1511 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1513 struct vcpu_svm *svm = to_svm(vcpu);
1515 svm->vmcb->save.idtr.limit = dt->size;
1516 svm->vmcb->save.idtr.base = dt->address ;
1517 mark_dirty(svm->vmcb, VMCB_DT);
1520 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1522 struct vcpu_svm *svm = to_svm(vcpu);
1524 dt->size = svm->vmcb->save.gdtr.limit;
1525 dt->address = svm->vmcb->save.gdtr.base;
1528 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1530 struct vcpu_svm *svm = to_svm(vcpu);
1532 svm->vmcb->save.gdtr.limit = dt->size;
1533 svm->vmcb->save.gdtr.base = dt->address ;
1534 mark_dirty(svm->vmcb, VMCB_DT);
1537 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1541 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1545 static void update_cr0_intercept(struct vcpu_svm *svm)
1547 ulong gcr0 = svm->vcpu.arch.cr0;
1548 u64 *hcr0 = &svm->vmcb->save.cr0;
1550 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1551 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1553 mark_dirty(svm->vmcb, VMCB_CR);
1555 if (gcr0 == *hcr0) {
1556 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1557 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1559 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1560 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1564 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1566 struct vcpu_svm *svm = to_svm(vcpu);
1568 #ifdef CONFIG_X86_64
1569 if (vcpu->arch.efer & EFER_LME) {
1570 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1571 vcpu->arch.efer |= EFER_LMA;
1572 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1575 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1576 vcpu->arch.efer &= ~EFER_LMA;
1577 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1581 vcpu->arch.cr0 = cr0;
1584 cr0 |= X86_CR0_PG | X86_CR0_WP;
1587 * re-enable caching here because the QEMU bios
1588 * does not do it - this results in some delay at
1591 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1592 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1593 svm->vmcb->save.cr0 = cr0;
1594 mark_dirty(svm->vmcb, VMCB_CR);
1595 update_cr0_intercept(svm);
1598 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1600 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1601 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1603 if (cr4 & X86_CR4_VMXE)
1606 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1607 svm_flush_tlb(vcpu);
1609 vcpu->arch.cr4 = cr4;
1612 cr4 |= host_cr4_mce;
1613 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1614 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1618 static void svm_set_segment(struct kvm_vcpu *vcpu,
1619 struct kvm_segment *var, int seg)
1621 struct vcpu_svm *svm = to_svm(vcpu);
1622 struct vmcb_seg *s = svm_seg(vcpu, seg);
1624 s->base = var->base;
1625 s->limit = var->limit;
1626 s->selector = var->selector;
1627 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1628 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1629 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1630 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1631 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1632 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1633 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1634 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1637 * This is always accurate, except if SYSRET returned to a segment
1638 * with SS.DPL != 3. Intel does not have this quirk, and always
1639 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1640 * would entail passing the CPL to userspace and back.
1642 if (seg == VCPU_SREG_SS)
1643 /* This is symmetric with svm_get_segment() */
1644 svm->vmcb->save.cpl = (var->dpl & 3);
1646 mark_dirty(svm->vmcb, VMCB_SEG);
1649 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1651 struct vcpu_svm *svm = to_svm(vcpu);
1653 clr_exception_intercept(svm, BP_VECTOR);
1655 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1656 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1657 set_exception_intercept(svm, BP_VECTOR);
1659 vcpu->guest_debug = 0;
1662 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1664 if (sd->next_asid > sd->max_asid) {
1665 ++sd->asid_generation;
1666 sd->next_asid = sd->min_asid;
1667 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1670 svm->asid_generation = sd->asid_generation;
1671 svm->vmcb->control.asid = sd->next_asid++;
1673 mark_dirty(svm->vmcb, VMCB_ASID);
1676 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1678 struct vmcb *vmcb = svm->vmcb;
1680 if (unlikely(value != vmcb->save.dr6)) {
1681 vmcb->save.dr6 = value;
1682 mark_dirty(vmcb, VMCB_DR);
1686 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1688 struct vcpu_svm *svm = to_svm(vcpu);
1690 get_debugreg(vcpu->arch.db[0], 0);
1691 get_debugreg(vcpu->arch.db[1], 1);
1692 get_debugreg(vcpu->arch.db[2], 2);
1693 get_debugreg(vcpu->arch.db[3], 3);
1695 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1696 * because db_interception might need it. We can do it before vmentry.
1698 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1699 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1700 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1701 set_dr_intercepts(svm);
1704 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1706 struct vcpu_svm *svm = to_svm(vcpu);
1708 svm->vmcb->save.dr7 = value;
1709 mark_dirty(svm->vmcb, VMCB_DR);
1712 static int pf_interception(struct vcpu_svm *svm)
1714 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1715 u64 error_code = svm->vmcb->control.exit_info_1;
1717 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1718 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1719 svm->vmcb->control.insn_bytes : NULL,
1720 svm->vmcb->control.insn_len);
1723 static int npf_interception(struct vcpu_svm *svm)
1725 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1726 u64 error_code = svm->vmcb->control.exit_info_1;
1728 trace_kvm_page_fault(fault_address, error_code);
1729 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1730 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1731 svm->vmcb->control.insn_bytes : NULL,
1732 svm->vmcb->control.insn_len);
1735 static int db_interception(struct vcpu_svm *svm)
1737 struct kvm_run *kvm_run = svm->vcpu.run;
1738 struct kvm_vcpu *vcpu = &svm->vcpu;
1740 if (!(svm->vcpu.guest_debug &
1741 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1742 !svm->nmi_singlestep) {
1743 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1744 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1748 if (svm->nmi_singlestep) {
1749 disable_nmi_singlestep(svm);
1750 /* Make sure we check for pending NMIs upon entry */
1751 kvm_make_request(KVM_REQ_EVENT, vcpu);
1754 if (svm->vcpu.guest_debug &
1755 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1756 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1757 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1758 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1759 kvm_run->debug.arch.pc =
1760 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1761 kvm_run->debug.arch.exception = DB_VECTOR;
1768 static int bp_interception(struct vcpu_svm *svm)
1770 struct kvm_run *kvm_run = svm->vcpu.run;
1772 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1773 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1774 kvm_run->debug.arch.exception = BP_VECTOR;
1778 static int ud_interception(struct vcpu_svm *svm)
1780 return handle_ud(&svm->vcpu);
1783 static int ac_interception(struct vcpu_svm *svm)
1785 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1789 static int gp_interception(struct vcpu_svm *svm)
1791 struct kvm_vcpu *vcpu = &svm->vcpu;
1792 u32 error_code = svm->vmcb->control.exit_info_1;
1794 WARN_ON_ONCE(!enable_vmware_backdoor);
1797 * VMware backdoor emulation on #GP interception only handles IN{S},
1798 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1801 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1804 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1807 static bool is_erratum_383(void)
1812 if (!erratum_383_found)
1815 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1819 /* Bit 62 may or may not be set for this mce */
1820 value &= ~(1ULL << 62);
1822 if (value != 0xb600000000010015ULL)
1825 /* Clear MCi_STATUS registers */
1826 for (i = 0; i < 6; ++i)
1827 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1829 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1833 value &= ~(1ULL << 2);
1834 low = lower_32_bits(value);
1835 high = upper_32_bits(value);
1837 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1840 /* Flush tlb to evict multi-match entries */
1847 * Trigger machine check on the host. We assume all the MSRs are already set up
1848 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1849 * We pass a fake environment to the machine check handler because we want
1850 * the guest to be always treated like user space, no matter what context
1851 * it used internally.
1853 static void kvm_machine_check(void)
1855 #if defined(CONFIG_X86_MCE)
1856 struct pt_regs regs = {
1857 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1858 .flags = X86_EFLAGS_IF,
1861 do_machine_check(®s, 0);
1865 static void svm_handle_mce(struct vcpu_svm *svm)
1867 if (is_erratum_383()) {
1869 * Erratum 383 triggered. Guest state is corrupt so kill the
1872 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1874 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1880 * On an #MC intercept the MCE handler is not called automatically in
1881 * the host. So do it by hand here.
1883 kvm_machine_check();
1886 static int mc_interception(struct vcpu_svm *svm)
1891 static int shutdown_interception(struct vcpu_svm *svm)
1893 struct kvm_run *kvm_run = svm->vcpu.run;
1896 * VMCB is undefined after a SHUTDOWN intercept
1897 * so reinitialize it.
1899 clear_page(svm->vmcb);
1902 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1906 static int io_interception(struct vcpu_svm *svm)
1908 struct kvm_vcpu *vcpu = &svm->vcpu;
1909 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1910 int size, in, string;
1913 ++svm->vcpu.stat.io_exits;
1914 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1915 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1917 return kvm_emulate_instruction(vcpu, 0);
1919 port = io_info >> 16;
1920 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1921 svm->next_rip = svm->vmcb->control.exit_info_2;
1923 return kvm_fast_pio(&svm->vcpu, size, port, in);
1926 static int nmi_interception(struct vcpu_svm *svm)
1931 static int intr_interception(struct vcpu_svm *svm)
1933 ++svm->vcpu.stat.irq_exits;
1937 static int nop_on_interception(struct vcpu_svm *svm)
1942 static int halt_interception(struct vcpu_svm *svm)
1944 return kvm_emulate_halt(&svm->vcpu);
1947 static int vmmcall_interception(struct vcpu_svm *svm)
1949 return kvm_emulate_hypercall(&svm->vcpu);
1952 static int vmload_interception(struct vcpu_svm *svm)
1954 struct vmcb *nested_vmcb;
1955 struct kvm_host_map map;
1958 if (nested_svm_check_permissions(svm))
1961 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1964 kvm_inject_gp(&svm->vcpu, 0);
1968 nested_vmcb = map.hva;
1970 ret = kvm_skip_emulated_instruction(&svm->vcpu);
1972 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1973 kvm_vcpu_unmap(&svm->vcpu, &map, true);
1978 static int vmsave_interception(struct vcpu_svm *svm)
1980 struct vmcb *nested_vmcb;
1981 struct kvm_host_map map;
1984 if (nested_svm_check_permissions(svm))
1987 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1990 kvm_inject_gp(&svm->vcpu, 0);
1994 nested_vmcb = map.hva;
1996 ret = kvm_skip_emulated_instruction(&svm->vcpu);
1998 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1999 kvm_vcpu_unmap(&svm->vcpu, &map, true);
2004 static int vmrun_interception(struct vcpu_svm *svm)
2006 if (nested_svm_check_permissions(svm))
2009 return nested_svm_vmrun(svm);
2012 static int stgi_interception(struct vcpu_svm *svm)
2016 if (nested_svm_check_permissions(svm))
2020 * If VGIF is enabled, the STGI intercept is only added to
2021 * detect the opening of the SMI/NMI window; remove it now.
2023 if (vgif_enabled(svm))
2024 clr_intercept(svm, INTERCEPT_STGI);
2026 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2027 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2034 static int clgi_interception(struct vcpu_svm *svm)
2038 if (nested_svm_check_permissions(svm))
2041 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2045 /* After a CLGI no interrupts should come */
2046 if (!kvm_vcpu_apicv_active(&svm->vcpu))
2047 svm_clear_vintr(svm);
2052 static int invlpga_interception(struct vcpu_svm *svm)
2054 struct kvm_vcpu *vcpu = &svm->vcpu;
2056 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2057 kvm_rax_read(&svm->vcpu));
2059 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2060 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2062 return kvm_skip_emulated_instruction(&svm->vcpu);
2065 static int skinit_interception(struct vcpu_svm *svm)
2067 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2069 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2073 static int wbinvd_interception(struct vcpu_svm *svm)
2075 return kvm_emulate_wbinvd(&svm->vcpu);
2078 static int xsetbv_interception(struct vcpu_svm *svm)
2080 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2081 u32 index = kvm_rcx_read(&svm->vcpu);
2083 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2084 return kvm_skip_emulated_instruction(&svm->vcpu);
2090 static int rdpru_interception(struct vcpu_svm *svm)
2092 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2096 static int task_switch_interception(struct vcpu_svm *svm)
2100 int int_type = svm->vmcb->control.exit_int_info &
2101 SVM_EXITINTINFO_TYPE_MASK;
2102 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2104 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2106 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2107 bool has_error_code = false;
2110 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2112 if (svm->vmcb->control.exit_info_2 &
2113 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2114 reason = TASK_SWITCH_IRET;
2115 else if (svm->vmcb->control.exit_info_2 &
2116 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2117 reason = TASK_SWITCH_JMP;
2119 reason = TASK_SWITCH_GATE;
2121 reason = TASK_SWITCH_CALL;
2123 if (reason == TASK_SWITCH_GATE) {
2125 case SVM_EXITINTINFO_TYPE_NMI:
2126 svm->vcpu.arch.nmi_injected = false;
2128 case SVM_EXITINTINFO_TYPE_EXEPT:
2129 if (svm->vmcb->control.exit_info_2 &
2130 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2131 has_error_code = true;
2133 (u32)svm->vmcb->control.exit_info_2;
2135 kvm_clear_exception_queue(&svm->vcpu);
2137 case SVM_EXITINTINFO_TYPE_INTR:
2138 kvm_clear_interrupt_queue(&svm->vcpu);
2145 if (reason != TASK_SWITCH_GATE ||
2146 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2147 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2148 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2149 if (!skip_emulated_instruction(&svm->vcpu))
2153 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2156 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2157 has_error_code, error_code);
2160 static int cpuid_interception(struct vcpu_svm *svm)
2162 return kvm_emulate_cpuid(&svm->vcpu);
2165 static int iret_interception(struct vcpu_svm *svm)
2167 ++svm->vcpu.stat.nmi_window_exits;
2168 clr_intercept(svm, INTERCEPT_IRET);
2169 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2170 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2171 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2175 static int invlpg_interception(struct vcpu_svm *svm)
2177 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2178 return kvm_emulate_instruction(&svm->vcpu, 0);
2180 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2181 return kvm_skip_emulated_instruction(&svm->vcpu);
2184 static int emulate_on_interception(struct vcpu_svm *svm)
2186 return kvm_emulate_instruction(&svm->vcpu, 0);
2189 static int rsm_interception(struct vcpu_svm *svm)
2191 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2194 static int rdpmc_interception(struct vcpu_svm *svm)
2199 return emulate_on_interception(svm);
2201 err = kvm_rdpmc(&svm->vcpu);
2202 return kvm_complete_insn_gp(&svm->vcpu, err);
2205 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2208 unsigned long cr0 = svm->vcpu.arch.cr0;
2212 intercept = svm->nested.intercept;
2214 if (!is_guest_mode(&svm->vcpu) ||
2215 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2218 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2219 val &= ~SVM_CR0_SELECTIVE_MASK;
2222 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2223 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2229 #define CR_VALID (1ULL << 63)
2231 static int cr_interception(struct vcpu_svm *svm)
2237 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2238 return emulate_on_interception(svm);
2240 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2241 return emulate_on_interception(svm);
2243 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2244 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2245 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2247 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2250 if (cr >= 16) { /* mov to cr */
2252 val = kvm_register_read(&svm->vcpu, reg);
2255 if (!check_selective_cr0_intercepted(svm, val))
2256 err = kvm_set_cr0(&svm->vcpu, val);
2262 err = kvm_set_cr3(&svm->vcpu, val);
2265 err = kvm_set_cr4(&svm->vcpu, val);
2268 err = kvm_set_cr8(&svm->vcpu, val);
2271 WARN(1, "unhandled write to CR%d", cr);
2272 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2275 } else { /* mov from cr */
2278 val = kvm_read_cr0(&svm->vcpu);
2281 val = svm->vcpu.arch.cr2;
2284 val = kvm_read_cr3(&svm->vcpu);
2287 val = kvm_read_cr4(&svm->vcpu);
2290 val = kvm_get_cr8(&svm->vcpu);
2293 WARN(1, "unhandled read from CR%d", cr);
2294 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2297 kvm_register_write(&svm->vcpu, reg, val);
2299 return kvm_complete_insn_gp(&svm->vcpu, err);
2302 static int dr_interception(struct vcpu_svm *svm)
2307 if (svm->vcpu.guest_debug == 0) {
2309 * No more DR vmexits; force a reload of the debug registers
2310 * and reenter on this instruction. The next vmexit will
2311 * retrieve the full state of the debug registers.
2313 clr_dr_intercepts(svm);
2314 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2318 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2319 return emulate_on_interception(svm);
2321 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2322 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2324 if (dr >= 16) { /* mov to DRn */
2325 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2327 val = kvm_register_read(&svm->vcpu, reg);
2328 kvm_set_dr(&svm->vcpu, dr - 16, val);
2330 if (!kvm_require_dr(&svm->vcpu, dr))
2332 kvm_get_dr(&svm->vcpu, dr, &val);
2333 kvm_register_write(&svm->vcpu, reg, val);
2336 return kvm_skip_emulated_instruction(&svm->vcpu);
2339 static int cr8_write_interception(struct vcpu_svm *svm)
2341 struct kvm_run *kvm_run = svm->vcpu.run;
2344 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2345 /* instruction emulation calls kvm_set_cr8() */
2346 r = cr_interception(svm);
2347 if (lapic_in_kernel(&svm->vcpu))
2349 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2351 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2355 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2359 switch (msr->index) {
2360 case MSR_F10H_DECFG:
2361 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2362 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2371 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2373 struct vcpu_svm *svm = to_svm(vcpu);
2375 switch (msr_info->index) {
2377 msr_info->data = svm->vmcb->save.star;
2379 #ifdef CONFIG_X86_64
2381 msr_info->data = svm->vmcb->save.lstar;
2384 msr_info->data = svm->vmcb->save.cstar;
2386 case MSR_KERNEL_GS_BASE:
2387 msr_info->data = svm->vmcb->save.kernel_gs_base;
2389 case MSR_SYSCALL_MASK:
2390 msr_info->data = svm->vmcb->save.sfmask;
2393 case MSR_IA32_SYSENTER_CS:
2394 msr_info->data = svm->vmcb->save.sysenter_cs;
2396 case MSR_IA32_SYSENTER_EIP:
2397 msr_info->data = svm->sysenter_eip;
2399 case MSR_IA32_SYSENTER_ESP:
2400 msr_info->data = svm->sysenter_esp;
2403 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2405 msr_info->data = svm->tsc_aux;
2408 * Nobody will change the following 5 values in the VMCB so we can
2409 * safely return them on rdmsr. They will always be 0 until LBRV is
2412 case MSR_IA32_DEBUGCTLMSR:
2413 msr_info->data = svm->vmcb->save.dbgctl;
2415 case MSR_IA32_LASTBRANCHFROMIP:
2416 msr_info->data = svm->vmcb->save.br_from;
2418 case MSR_IA32_LASTBRANCHTOIP:
2419 msr_info->data = svm->vmcb->save.br_to;
2421 case MSR_IA32_LASTINTFROMIP:
2422 msr_info->data = svm->vmcb->save.last_excp_from;
2424 case MSR_IA32_LASTINTTOIP:
2425 msr_info->data = svm->vmcb->save.last_excp_to;
2427 case MSR_VM_HSAVE_PA:
2428 msr_info->data = svm->nested.hsave_msr;
2431 msr_info->data = svm->nested.vm_cr_msr;
2433 case MSR_IA32_SPEC_CTRL:
2434 if (!msr_info->host_initiated &&
2435 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2436 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2437 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2438 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2441 msr_info->data = svm->spec_ctrl;
2443 case MSR_AMD64_VIRT_SPEC_CTRL:
2444 if (!msr_info->host_initiated &&
2445 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2448 msr_info->data = svm->virt_spec_ctrl;
2450 case MSR_F15H_IC_CFG: {
2454 family = guest_cpuid_family(vcpu);
2455 model = guest_cpuid_model(vcpu);
2457 if (family < 0 || model < 0)
2458 return kvm_get_msr_common(vcpu, msr_info);
2462 if (family == 0x15 &&
2463 (model >= 0x2 && model < 0x20))
2464 msr_info->data = 0x1E;
2467 case MSR_F10H_DECFG:
2468 msr_info->data = svm->msr_decfg;
2471 return kvm_get_msr_common(vcpu, msr_info);
2476 static int rdmsr_interception(struct vcpu_svm *svm)
2478 return kvm_emulate_rdmsr(&svm->vcpu);
2481 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2483 struct vcpu_svm *svm = to_svm(vcpu);
2484 int svm_dis, chg_mask;
2486 if (data & ~SVM_VM_CR_VALID_MASK)
2489 chg_mask = SVM_VM_CR_VALID_MASK;
2491 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2492 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2494 svm->nested.vm_cr_msr &= ~chg_mask;
2495 svm->nested.vm_cr_msr |= (data & chg_mask);
2497 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2499 /* check for svm_disable while efer.svme is set */
2500 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2506 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2508 struct vcpu_svm *svm = to_svm(vcpu);
2510 u32 ecx = msr->index;
2511 u64 data = msr->data;
2513 case MSR_IA32_CR_PAT:
2514 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2516 vcpu->arch.pat = data;
2517 svm->vmcb->save.g_pat = data;
2518 mark_dirty(svm->vmcb, VMCB_NPT);
2520 case MSR_IA32_SPEC_CTRL:
2521 if (!msr->host_initiated &&
2522 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2523 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2524 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2525 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2528 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2531 svm->spec_ctrl = data;
2537 * When it's written (to non-zero) for the first time, pass
2541 * The handling of the MSR bitmap for L2 guests is done in
2542 * nested_svm_vmrun_msrpm.
2543 * We update the L1 MSR bit as well since it will end up
2544 * touching the MSR anyway now.
2546 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2548 case MSR_IA32_PRED_CMD:
2549 if (!msr->host_initiated &&
2550 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2553 if (data & ~PRED_CMD_IBPB)
2555 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2560 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2561 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2563 case MSR_AMD64_VIRT_SPEC_CTRL:
2564 if (!msr->host_initiated &&
2565 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2568 if (data & ~SPEC_CTRL_SSBD)
2571 svm->virt_spec_ctrl = data;
2574 svm->vmcb->save.star = data;
2576 #ifdef CONFIG_X86_64
2578 svm->vmcb->save.lstar = data;
2581 svm->vmcb->save.cstar = data;
2583 case MSR_KERNEL_GS_BASE:
2584 svm->vmcb->save.kernel_gs_base = data;
2586 case MSR_SYSCALL_MASK:
2587 svm->vmcb->save.sfmask = data;
2590 case MSR_IA32_SYSENTER_CS:
2591 svm->vmcb->save.sysenter_cs = data;
2593 case MSR_IA32_SYSENTER_EIP:
2594 svm->sysenter_eip = data;
2595 svm->vmcb->save.sysenter_eip = data;
2597 case MSR_IA32_SYSENTER_ESP:
2598 svm->sysenter_esp = data;
2599 svm->vmcb->save.sysenter_esp = data;
2602 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2606 * This is rare, so we update the MSR here instead of using
2607 * direct_access_msrs. Doing that would require a rdmsr in
2610 svm->tsc_aux = data;
2611 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2613 case MSR_IA32_DEBUGCTLMSR:
2614 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2615 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2619 if (data & DEBUGCTL_RESERVED_BITS)
2622 svm->vmcb->save.dbgctl = data;
2623 mark_dirty(svm->vmcb, VMCB_LBR);
2624 if (data & (1ULL<<0))
2625 svm_enable_lbrv(svm);
2627 svm_disable_lbrv(svm);
2629 case MSR_VM_HSAVE_PA:
2630 svm->nested.hsave_msr = data;
2633 return svm_set_vm_cr(vcpu, data);
2635 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2637 case MSR_F10H_DECFG: {
2638 struct kvm_msr_entry msr_entry;
2640 msr_entry.index = msr->index;
2641 if (svm_get_msr_feature(&msr_entry))
2644 /* Check the supported bits */
2645 if (data & ~msr_entry.data)
2648 /* Don't allow the guest to change a bit, #GP */
2649 if (!msr->host_initiated && (data ^ msr_entry.data))
2652 svm->msr_decfg = data;
2655 case MSR_IA32_APICBASE:
2656 if (kvm_vcpu_apicv_active(vcpu))
2657 avic_update_vapic_bar(to_svm(vcpu), data);
2660 return kvm_set_msr_common(vcpu, msr);
2665 static int wrmsr_interception(struct vcpu_svm *svm)
2667 return kvm_emulate_wrmsr(&svm->vcpu);
2670 static int msr_interception(struct vcpu_svm *svm)
2672 if (svm->vmcb->control.exit_info_1)
2673 return wrmsr_interception(svm);
2675 return rdmsr_interception(svm);
2678 static int interrupt_window_interception(struct vcpu_svm *svm)
2680 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2681 svm_clear_vintr(svm);
2684 * For AVIC, the only reason to end up here is ExtINTs.
2685 * In this case AVIC was temporarily disabled for
2686 * requesting the IRQ window and we have to re-enable it.
2688 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2690 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2691 mark_dirty(svm->vmcb, VMCB_INTR);
2692 ++svm->vcpu.stat.irq_window_exits;
2696 static int pause_interception(struct vcpu_svm *svm)
2698 struct kvm_vcpu *vcpu = &svm->vcpu;
2699 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2701 if (pause_filter_thresh)
2702 grow_ple_window(vcpu);
2704 kvm_vcpu_on_spin(vcpu, in_kernel);
2708 static int nop_interception(struct vcpu_svm *svm)
2710 return kvm_skip_emulated_instruction(&(svm->vcpu));
2713 static int monitor_interception(struct vcpu_svm *svm)
2715 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2716 return nop_interception(svm);
2719 static int mwait_interception(struct vcpu_svm *svm)
2721 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2722 return nop_interception(svm);
2725 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2726 [SVM_EXIT_READ_CR0] = cr_interception,
2727 [SVM_EXIT_READ_CR3] = cr_interception,
2728 [SVM_EXIT_READ_CR4] = cr_interception,
2729 [SVM_EXIT_READ_CR8] = cr_interception,
2730 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
2731 [SVM_EXIT_WRITE_CR0] = cr_interception,
2732 [SVM_EXIT_WRITE_CR3] = cr_interception,
2733 [SVM_EXIT_WRITE_CR4] = cr_interception,
2734 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2735 [SVM_EXIT_READ_DR0] = dr_interception,
2736 [SVM_EXIT_READ_DR1] = dr_interception,
2737 [SVM_EXIT_READ_DR2] = dr_interception,
2738 [SVM_EXIT_READ_DR3] = dr_interception,
2739 [SVM_EXIT_READ_DR4] = dr_interception,
2740 [SVM_EXIT_READ_DR5] = dr_interception,
2741 [SVM_EXIT_READ_DR6] = dr_interception,
2742 [SVM_EXIT_READ_DR7] = dr_interception,
2743 [SVM_EXIT_WRITE_DR0] = dr_interception,
2744 [SVM_EXIT_WRITE_DR1] = dr_interception,
2745 [SVM_EXIT_WRITE_DR2] = dr_interception,
2746 [SVM_EXIT_WRITE_DR3] = dr_interception,
2747 [SVM_EXIT_WRITE_DR4] = dr_interception,
2748 [SVM_EXIT_WRITE_DR5] = dr_interception,
2749 [SVM_EXIT_WRITE_DR6] = dr_interception,
2750 [SVM_EXIT_WRITE_DR7] = dr_interception,
2751 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2752 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2753 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2754 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2755 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2756 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
2757 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
2758 [SVM_EXIT_INTR] = intr_interception,
2759 [SVM_EXIT_NMI] = nmi_interception,
2760 [SVM_EXIT_SMI] = nop_on_interception,
2761 [SVM_EXIT_INIT] = nop_on_interception,
2762 [SVM_EXIT_VINTR] = interrupt_window_interception,
2763 [SVM_EXIT_RDPMC] = rdpmc_interception,
2764 [SVM_EXIT_CPUID] = cpuid_interception,
2765 [SVM_EXIT_IRET] = iret_interception,
2766 [SVM_EXIT_INVD] = emulate_on_interception,
2767 [SVM_EXIT_PAUSE] = pause_interception,
2768 [SVM_EXIT_HLT] = halt_interception,
2769 [SVM_EXIT_INVLPG] = invlpg_interception,
2770 [SVM_EXIT_INVLPGA] = invlpga_interception,
2771 [SVM_EXIT_IOIO] = io_interception,
2772 [SVM_EXIT_MSR] = msr_interception,
2773 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2774 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2775 [SVM_EXIT_VMRUN] = vmrun_interception,
2776 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2777 [SVM_EXIT_VMLOAD] = vmload_interception,
2778 [SVM_EXIT_VMSAVE] = vmsave_interception,
2779 [SVM_EXIT_STGI] = stgi_interception,
2780 [SVM_EXIT_CLGI] = clgi_interception,
2781 [SVM_EXIT_SKINIT] = skinit_interception,
2782 [SVM_EXIT_WBINVD] = wbinvd_interception,
2783 [SVM_EXIT_MONITOR] = monitor_interception,
2784 [SVM_EXIT_MWAIT] = mwait_interception,
2785 [SVM_EXIT_XSETBV] = xsetbv_interception,
2786 [SVM_EXIT_RDPRU] = rdpru_interception,
2787 [SVM_EXIT_NPF] = npf_interception,
2788 [SVM_EXIT_RSM] = rsm_interception,
2789 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2790 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
2793 static void dump_vmcb(struct kvm_vcpu *vcpu)
2795 struct vcpu_svm *svm = to_svm(vcpu);
2796 struct vmcb_control_area *control = &svm->vmcb->control;
2797 struct vmcb_save_area *save = &svm->vmcb->save;
2799 if (!dump_invalid_vmcb) {
2800 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2804 pr_err("VMCB Control Area:\n");
2805 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2806 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2807 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2808 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2809 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2810 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2811 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2812 pr_err("%-20s%d\n", "pause filter threshold:",
2813 control->pause_filter_thresh);
2814 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2815 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2816 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2817 pr_err("%-20s%d\n", "asid:", control->asid);
2818 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2819 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2820 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2821 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2822 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2823 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2824 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2825 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2826 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2827 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2828 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2829 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2830 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2831 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2832 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2833 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2834 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2835 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2836 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2837 pr_err("VMCB State Save Area:\n");
2838 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2840 save->es.selector, save->es.attrib,
2841 save->es.limit, save->es.base);
2842 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2844 save->cs.selector, save->cs.attrib,
2845 save->cs.limit, save->cs.base);
2846 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2848 save->ss.selector, save->ss.attrib,
2849 save->ss.limit, save->ss.base);
2850 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2852 save->ds.selector, save->ds.attrib,
2853 save->ds.limit, save->ds.base);
2854 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2856 save->fs.selector, save->fs.attrib,
2857 save->fs.limit, save->fs.base);
2858 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2860 save->gs.selector, save->gs.attrib,
2861 save->gs.limit, save->gs.base);
2862 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2864 save->gdtr.selector, save->gdtr.attrib,
2865 save->gdtr.limit, save->gdtr.base);
2866 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2868 save->ldtr.selector, save->ldtr.attrib,
2869 save->ldtr.limit, save->ldtr.base);
2870 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2872 save->idtr.selector, save->idtr.attrib,
2873 save->idtr.limit, save->idtr.base);
2874 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2876 save->tr.selector, save->tr.attrib,
2877 save->tr.limit, save->tr.base);
2878 pr_err("cpl: %d efer: %016llx\n",
2879 save->cpl, save->efer);
2880 pr_err("%-15s %016llx %-13s %016llx\n",
2881 "cr0:", save->cr0, "cr2:", save->cr2);
2882 pr_err("%-15s %016llx %-13s %016llx\n",
2883 "cr3:", save->cr3, "cr4:", save->cr4);
2884 pr_err("%-15s %016llx %-13s %016llx\n",
2885 "dr6:", save->dr6, "dr7:", save->dr7);
2886 pr_err("%-15s %016llx %-13s %016llx\n",
2887 "rip:", save->rip, "rflags:", save->rflags);
2888 pr_err("%-15s %016llx %-13s %016llx\n",
2889 "rsp:", save->rsp, "rax:", save->rax);
2890 pr_err("%-15s %016llx %-13s %016llx\n",
2891 "star:", save->star, "lstar:", save->lstar);
2892 pr_err("%-15s %016llx %-13s %016llx\n",
2893 "cstar:", save->cstar, "sfmask:", save->sfmask);
2894 pr_err("%-15s %016llx %-13s %016llx\n",
2895 "kernel_gs_base:", save->kernel_gs_base,
2896 "sysenter_cs:", save->sysenter_cs);
2897 pr_err("%-15s %016llx %-13s %016llx\n",
2898 "sysenter_esp:", save->sysenter_esp,
2899 "sysenter_eip:", save->sysenter_eip);
2900 pr_err("%-15s %016llx %-13s %016llx\n",
2901 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2902 pr_err("%-15s %016llx %-13s %016llx\n",
2903 "br_from:", save->br_from, "br_to:", save->br_to);
2904 pr_err("%-15s %016llx %-13s %016llx\n",
2905 "excp_from:", save->last_excp_from,
2906 "excp_to:", save->last_excp_to);
2909 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2911 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2913 *info1 = control->exit_info_1;
2914 *info2 = control->exit_info_2;
2917 static int handle_exit(struct kvm_vcpu *vcpu,
2918 enum exit_fastpath_completion exit_fastpath)
2920 struct vcpu_svm *svm = to_svm(vcpu);
2921 struct kvm_run *kvm_run = vcpu->run;
2922 u32 exit_code = svm->vmcb->control.exit_code;
2924 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2926 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2927 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2929 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2931 if (unlikely(svm->nested.exit_required)) {
2932 nested_svm_vmexit(svm);
2933 svm->nested.exit_required = false;
2938 if (is_guest_mode(vcpu)) {
2941 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2942 svm->vmcb->control.exit_info_1,
2943 svm->vmcb->control.exit_info_2,
2944 svm->vmcb->control.exit_int_info,
2945 svm->vmcb->control.exit_int_info_err,
2948 vmexit = nested_svm_exit_special(svm);
2950 if (vmexit == NESTED_EXIT_CONTINUE)
2951 vmexit = nested_svm_exit_handled(svm);
2953 if (vmexit == NESTED_EXIT_DONE)
2957 svm_complete_interrupts(svm);
2959 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2960 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2961 kvm_run->fail_entry.hardware_entry_failure_reason
2962 = svm->vmcb->control.exit_code;
2967 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2968 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2969 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2970 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2971 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
2973 __func__, svm->vmcb->control.exit_int_info,
2976 if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
2977 kvm_skip_emulated_instruction(vcpu);
2979 } else if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2980 || !svm_exit_handlers[exit_code]) {
2981 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2983 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2984 vcpu->run->internal.suberror =
2985 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2986 vcpu->run->internal.ndata = 1;
2987 vcpu->run->internal.data[0] = exit_code;
2991 #ifdef CONFIG_RETPOLINE
2992 if (exit_code == SVM_EXIT_MSR)
2993 return msr_interception(svm);
2994 else if (exit_code == SVM_EXIT_VINTR)
2995 return interrupt_window_interception(svm);
2996 else if (exit_code == SVM_EXIT_INTR)
2997 return intr_interception(svm);
2998 else if (exit_code == SVM_EXIT_HLT)
2999 return halt_interception(svm);
3000 else if (exit_code == SVM_EXIT_NPF)
3001 return npf_interception(svm);
3003 return svm_exit_handlers[exit_code](svm);
3006 static void reload_tss(struct kvm_vcpu *vcpu)
3008 int cpu = raw_smp_processor_id();
3010 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3011 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3015 static void pre_svm_run(struct vcpu_svm *svm)
3017 int cpu = raw_smp_processor_id();
3019 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3021 if (sev_guest(svm->vcpu.kvm))
3022 return pre_sev_run(svm, cpu);
3024 /* FIXME: handle wraparound of asid_generation */
3025 if (svm->asid_generation != sd->asid_generation)
3029 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3031 struct vcpu_svm *svm = to_svm(vcpu);
3033 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3034 vcpu->arch.hflags |= HF_NMI_MASK;
3035 set_intercept(svm, INTERCEPT_IRET);
3036 ++vcpu->stat.nmi_injections;
3039 static void svm_set_irq(struct kvm_vcpu *vcpu)
3041 struct vcpu_svm *svm = to_svm(vcpu);
3043 BUG_ON(!(gif_set(svm)));
3045 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3046 ++vcpu->stat.irq_injections;
3048 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3049 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3052 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3054 struct vcpu_svm *svm = to_svm(vcpu);
3056 if (svm_nested_virtualize_tpr(vcpu))
3059 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3065 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3068 static bool svm_nmi_allowed(struct kvm_vcpu *vcpu)
3070 struct vcpu_svm *svm = to_svm(vcpu);
3071 struct vmcb *vmcb = svm->vmcb;
3074 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3077 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3078 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3079 ret = ret && gif_set(svm);
3084 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3086 struct vcpu_svm *svm = to_svm(vcpu);
3088 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3091 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3093 struct vcpu_svm *svm = to_svm(vcpu);
3096 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3097 set_intercept(svm, INTERCEPT_IRET);
3099 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3100 clr_intercept(svm, INTERCEPT_IRET);
3104 static bool svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3106 struct vcpu_svm *svm = to_svm(vcpu);
3107 struct vmcb *vmcb = svm->vmcb;
3109 if (!gif_set(svm) ||
3110 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3113 if (is_guest_mode(vcpu) && (svm->vcpu.arch.hflags & HF_VINTR_MASK))
3114 return !!(svm->vcpu.arch.hflags & HF_HIF_MASK);
3116 return !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3119 static void enable_irq_window(struct kvm_vcpu *vcpu)
3121 struct vcpu_svm *svm = to_svm(vcpu);
3124 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3125 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3126 * get that intercept, this function will be called again though and
3127 * we'll get the vintr intercept. However, if the vGIF feature is
3128 * enabled, the STGI interception will not occur. Enable the irq
3129 * window under the assumption that the hardware will set the GIF.
3131 if (vgif_enabled(svm) || gif_set(svm)) {
3133 * IRQ window is not needed when AVIC is enabled,
3134 * unless we have pending ExtINT since it cannot be injected
3135 * via AVIC. In such case, we need to temporarily disable AVIC,
3136 * and fallback to injecting IRQ via V_IRQ.
3138 svm_toggle_avic_for_irq_window(vcpu, false);
3143 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3145 struct vcpu_svm *svm = to_svm(vcpu);
3147 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3149 return; /* IRET will cause a vm exit */
3151 if (!gif_set(svm)) {
3152 if (vgif_enabled(svm))
3153 set_intercept(svm, INTERCEPT_STGI);
3154 return; /* STGI will cause a vm exit */
3158 * Something prevents NMI from been injected. Single step over possible
3159 * problem (IRET or exception injection or interrupt shadow)
3161 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3162 svm->nmi_singlestep = true;
3163 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3166 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3171 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3176 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3178 struct vcpu_svm *svm = to_svm(vcpu);
3181 * Flush only the current ASID even if the TLB flush was invoked via
3182 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3183 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3184 * unconditionally does a TLB flush on both nested VM-Enter and nested
3185 * VM-Exit (via kvm_mmu_reset_context()).
3187 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3188 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3190 svm->asid_generation--;
3193 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3195 struct vcpu_svm *svm = to_svm(vcpu);
3197 invlpga(gva, svm->vmcb->control.asid);
3200 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3204 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3206 struct vcpu_svm *svm = to_svm(vcpu);
3208 if (svm_nested_virtualize_tpr(vcpu))
3211 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3212 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3213 kvm_set_cr8(vcpu, cr8);
3217 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3219 struct vcpu_svm *svm = to_svm(vcpu);
3222 if (svm_nested_virtualize_tpr(vcpu) ||
3223 kvm_vcpu_apicv_active(vcpu))
3226 cr8 = kvm_get_cr8(vcpu);
3227 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3228 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3231 static void svm_complete_interrupts(struct vcpu_svm *svm)
3235 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3236 unsigned int3_injected = svm->int3_injected;
3238 svm->int3_injected = 0;
3241 * If we've made progress since setting HF_IRET_MASK, we've
3242 * executed an IRET and can allow NMI injection.
3244 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3245 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3246 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3247 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3250 svm->vcpu.arch.nmi_injected = false;
3251 kvm_clear_exception_queue(&svm->vcpu);
3252 kvm_clear_interrupt_queue(&svm->vcpu);
3254 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3257 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3259 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3260 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3263 case SVM_EXITINTINFO_TYPE_NMI:
3264 svm->vcpu.arch.nmi_injected = true;
3266 case SVM_EXITINTINFO_TYPE_EXEPT:
3268 * In case of software exceptions, do not reinject the vector,
3269 * but re-execute the instruction instead. Rewind RIP first
3270 * if we emulated INT3 before.
3272 if (kvm_exception_is_soft(vector)) {
3273 if (vector == BP_VECTOR && int3_injected &&
3274 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3275 kvm_rip_write(&svm->vcpu,
3276 kvm_rip_read(&svm->vcpu) -
3280 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3281 u32 err = svm->vmcb->control.exit_int_info_err;
3282 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3285 kvm_requeue_exception(&svm->vcpu, vector);
3287 case SVM_EXITINTINFO_TYPE_INTR:
3288 kvm_queue_interrupt(&svm->vcpu, vector, false);
3295 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3297 struct vcpu_svm *svm = to_svm(vcpu);
3298 struct vmcb_control_area *control = &svm->vmcb->control;
3300 control->exit_int_info = control->event_inj;
3301 control->exit_int_info_err = control->event_inj_err;
3302 control->event_inj = 0;
3303 svm_complete_interrupts(svm);
3306 static enum exit_fastpath_completion svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3308 if (!is_guest_mode(vcpu) &&
3309 to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3310 to_svm(vcpu)->vmcb->control.exit_info_1)
3311 return handle_fastpath_set_msr_irqoff(vcpu);
3313 return EXIT_FASTPATH_NONE;
3316 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3318 static enum exit_fastpath_completion svm_vcpu_run(struct kvm_vcpu *vcpu)
3320 enum exit_fastpath_completion exit_fastpath;
3321 struct vcpu_svm *svm = to_svm(vcpu);
3323 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3324 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3325 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3328 * A vmexit emulation is required before the vcpu can be executed
3331 if (unlikely(svm->nested.exit_required))
3332 return EXIT_FASTPATH_NONE;
3335 * Disable singlestep if we're injecting an interrupt/exception.
3336 * We don't want our modified rflags to be pushed on the stack where
3337 * we might not be able to easily reset them if we disabled NMI
3340 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3342 * Event injection happens before external interrupts cause a
3343 * vmexit and interrupts are disabled here, so smp_send_reschedule
3344 * is enough to force an immediate vmexit.
3346 disable_nmi_singlestep(svm);
3347 smp_send_reschedule(vcpu->cpu);
3352 sync_lapic_to_cr8(vcpu);
3354 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3357 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3360 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3361 svm_set_dr6(svm, vcpu->arch.dr6);
3363 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3366 kvm_load_guest_xsave_state(vcpu);
3368 if (lapic_in_kernel(vcpu) &&
3369 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3370 kvm_wait_lapic_expire(vcpu);
3373 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3374 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3375 * is no need to worry about the conditional branch over the wrmsr
3376 * being speculatively taken.
3378 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3380 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3382 #ifdef CONFIG_X86_64
3383 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3385 loadsegment(fs, svm->host.fs);
3386 #ifndef CONFIG_X86_32_LAZY_GS
3387 loadsegment(gs, svm->host.gs);
3392 * We do not use IBRS in the kernel. If this vCPU has used the
3393 * SPEC_CTRL MSR it may have left it on; save the value and
3394 * turn it off. This is much more efficient than blindly adding
3395 * it to the atomic save/restore list. Especially as the former
3396 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3398 * For non-nested case:
3399 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3403 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3406 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3407 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3411 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3413 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3414 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3415 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3416 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3418 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3419 kvm_before_interrupt(&svm->vcpu);
3421 kvm_load_host_xsave_state(vcpu);
3424 /* Any pending NMI will happen here */
3425 exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3427 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3428 kvm_after_interrupt(&svm->vcpu);
3430 sync_cr8_to_lapic(vcpu);
3433 svm->nested.nested_run_pending = 0;
3435 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3437 /* if exit due to PF check for async PF */
3438 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3439 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
3442 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3443 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3447 * We need to handle MC intercepts here before the vcpu has a chance to
3448 * change the physical cpu
3450 if (unlikely(svm->vmcb->control.exit_code ==
3451 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3452 svm_handle_mce(svm);
3454 mark_all_clean(svm->vmcb);
3455 return exit_fastpath;
3458 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
3460 struct vcpu_svm *svm = to_svm(vcpu);
3461 bool update_guest_cr3 = true;
3464 cr3 = __sme_set(root);
3466 svm->vmcb->control.nested_cr3 = cr3;
3467 mark_dirty(svm->vmcb, VMCB_NPT);
3469 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3470 if (is_guest_mode(vcpu))
3471 update_guest_cr3 = false;
3472 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3473 cr3 = vcpu->arch.cr3;
3474 else /* CR3 is already up-to-date. */
3475 update_guest_cr3 = false;
3478 if (update_guest_cr3) {
3479 svm->vmcb->save.cr3 = cr3;
3480 mark_dirty(svm->vmcb, VMCB_CR);
3484 static int is_disabled(void)
3488 rdmsrl(MSR_VM_CR, vm_cr);
3489 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3496 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3499 * Patch in the VMMCALL instruction:
3501 hypercall[0] = 0x0f;
3502 hypercall[1] = 0x01;
3503 hypercall[2] = 0xd9;
3506 static int __init svm_check_processor_compat(void)
3511 static bool svm_cpu_has_accelerated_tpr(void)
3516 static bool svm_has_emulated_msr(int index)
3519 case MSR_IA32_MCG_EXT_CTL:
3520 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3529 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3534 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3536 struct vcpu_svm *svm = to_svm(vcpu);
3538 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3539 boot_cpu_has(X86_FEATURE_XSAVE) &&
3540 boot_cpu_has(X86_FEATURE_XSAVES);
3542 /* Update nrips enabled cache */
3543 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3544 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3546 if (!kvm_vcpu_apicv_active(vcpu))
3550 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3551 * is exposed to the guest, disable AVIC.
3553 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3554 kvm_request_apicv_update(vcpu->kvm, false,
3555 APICV_INHIBIT_REASON_X2APIC);
3558 * Currently, AVIC does not work with nested virtualization.
3559 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3561 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3562 kvm_request_apicv_update(vcpu->kvm, false,
3563 APICV_INHIBIT_REASON_NESTED);
3566 static bool svm_has_wbinvd_exit(void)
3571 #define PRE_EX(exit) { .exit_code = (exit), \
3572 .stage = X86_ICPT_PRE_EXCEPT, }
3573 #define POST_EX(exit) { .exit_code = (exit), \
3574 .stage = X86_ICPT_POST_EXCEPT, }
3575 #define POST_MEM(exit) { .exit_code = (exit), \
3576 .stage = X86_ICPT_POST_MEMACCESS, }
3578 static const struct __x86_intercept {
3580 enum x86_intercept_stage stage;
3581 } x86_intercept_map[] = {
3582 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3583 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3584 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3585 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3586 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3587 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3588 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
3589 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3590 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3591 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3592 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3593 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3594 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3595 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3596 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
3597 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3598 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3599 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3600 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3601 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3602 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3603 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3604 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
3605 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3606 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3607 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
3608 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3609 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3610 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3611 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3612 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3613 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3614 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3615 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3616 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
3617 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3618 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3619 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3620 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3621 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3622 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3623 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
3624 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3625 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3626 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3627 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
3628 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
3635 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3636 struct x86_instruction_info *info,
3637 enum x86_intercept_stage stage,
3638 struct x86_exception *exception)
3640 struct vcpu_svm *svm = to_svm(vcpu);
3641 int vmexit, ret = X86EMUL_CONTINUE;
3642 struct __x86_intercept icpt_info;
3643 struct vmcb *vmcb = svm->vmcb;
3645 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3648 icpt_info = x86_intercept_map[info->intercept];
3650 if (stage != icpt_info.stage)
3653 switch (icpt_info.exit_code) {
3654 case SVM_EXIT_READ_CR0:
3655 if (info->intercept == x86_intercept_cr_read)
3656 icpt_info.exit_code += info->modrm_reg;
3658 case SVM_EXIT_WRITE_CR0: {
3659 unsigned long cr0, val;
3662 if (info->intercept == x86_intercept_cr_write)
3663 icpt_info.exit_code += info->modrm_reg;
3665 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3666 info->intercept == x86_intercept_clts)
3669 intercept = svm->nested.intercept;
3671 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3674 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3675 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3677 if (info->intercept == x86_intercept_lmsw) {
3680 /* lmsw can't clear PE - catch this here */
3681 if (cr0 & X86_CR0_PE)
3686 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3690 case SVM_EXIT_READ_DR0:
3691 case SVM_EXIT_WRITE_DR0:
3692 icpt_info.exit_code += info->modrm_reg;
3695 if (info->intercept == x86_intercept_wrmsr)
3696 vmcb->control.exit_info_1 = 1;
3698 vmcb->control.exit_info_1 = 0;
3700 case SVM_EXIT_PAUSE:
3702 * We get this for NOP only, but pause
3703 * is rep not, check this here
3705 if (info->rep_prefix != REPE_PREFIX)
3708 case SVM_EXIT_IOIO: {
3712 if (info->intercept == x86_intercept_in ||
3713 info->intercept == x86_intercept_ins) {
3714 exit_info = ((info->src_val & 0xffff) << 16) |
3716 bytes = info->dst_bytes;
3718 exit_info = (info->dst_val & 0xffff) << 16;
3719 bytes = info->src_bytes;
3722 if (info->intercept == x86_intercept_outs ||
3723 info->intercept == x86_intercept_ins)
3724 exit_info |= SVM_IOIO_STR_MASK;
3726 if (info->rep_prefix)
3727 exit_info |= SVM_IOIO_REP_MASK;
3729 bytes = min(bytes, 4u);
3731 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3733 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3735 vmcb->control.exit_info_1 = exit_info;
3736 vmcb->control.exit_info_2 = info->next_rip;
3744 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3745 if (static_cpu_has(X86_FEATURE_NRIPS))
3746 vmcb->control.next_rip = info->next_rip;
3747 vmcb->control.exit_code = icpt_info.exit_code;
3748 vmexit = nested_svm_exit_handled(svm);
3750 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3757 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3761 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3763 if (pause_filter_thresh)
3764 shrink_ple_window(vcpu);
3767 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3769 /* [63:9] are reserved. */
3770 vcpu->arch.mcg_cap &= 0x1ff;
3773 static bool svm_smi_allowed(struct kvm_vcpu *vcpu)
3775 struct vcpu_svm *svm = to_svm(vcpu);
3777 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3781 return !is_smm(vcpu);
3784 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3786 struct vcpu_svm *svm = to_svm(vcpu);
3789 if (is_guest_mode(vcpu)) {
3790 /* FED8h - SVM Guest */
3791 put_smstate(u64, smstate, 0x7ed8, 1);
3792 /* FEE0h - SVM Guest VMCB Physical Address */
3793 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3795 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3796 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3797 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3799 ret = nested_svm_vmexit(svm);
3806 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
3808 struct vcpu_svm *svm = to_svm(vcpu);
3809 struct vmcb *nested_vmcb;
3810 struct kvm_host_map map;
3814 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3815 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
3818 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
3820 nested_vmcb = map.hva;
3821 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
3826 static int enable_smi_window(struct kvm_vcpu *vcpu)
3828 struct vcpu_svm *svm = to_svm(vcpu);
3830 if (!gif_set(svm)) {
3831 if (vgif_enabled(svm))
3832 set_intercept(svm, INTERCEPT_STGI);
3833 /* STGI will cause a vm exit */
3839 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3841 unsigned long cr4 = kvm_read_cr4(vcpu);
3842 bool smep = cr4 & X86_CR4_SMEP;
3843 bool smap = cr4 & X86_CR4_SMAP;
3844 bool is_user = svm_get_cpl(vcpu) == 3;
3847 * If RIP is invalid, go ahead with emulation which will cause an
3848 * internal error exit.
3850 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3854 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3857 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3858 * possible that CPU microcode implementing DecodeAssist will fail
3859 * to read bytes of instruction which caused #NPF. In this case,
3860 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3861 * return 0 instead of the correct guest instruction bytes.
3863 * This happens because CPU microcode reading instruction bytes
3864 * uses a special opcode which attempts to read data using CPL=0
3865 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3866 * fault, it gives up and returns no instruction bytes.
3869 * We reach here in case CPU supports DecodeAssist, raised #NPF and
3870 * returned 0 in GuestIntrBytes field of the VMCB.
3871 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3872 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3873 * in case vCPU CPL==3 (Because otherwise guest would have triggered
3874 * a SMEP fault instead of #NPF).
3875 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3876 * As most guests enable SMAP if they have also enabled SMEP, use above
3877 * logic in order to attempt minimize false-positive of detecting errata
3878 * while still preserving all cases semantic correctness.
3881 * To determine what instruction the guest was executing, the hypervisor
3882 * will have to decode the instruction at the instruction pointer.
3884 * In non SEV guest, hypervisor will be able to read the guest
3885 * memory to decode the instruction pointer when insn_len is zero
3886 * so we return true to indicate that decoding is possible.
3888 * But in the SEV guest, the guest memory is encrypted with the
3889 * guest specific key and hypervisor will not be able to decode the
3890 * instruction pointer so we will not able to workaround it. Lets
3891 * print the error and request to kill the guest.
3893 if (smap && (!smep || is_user)) {
3894 if (!sev_guest(vcpu->kvm))
3897 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
3898 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3904 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3906 struct vcpu_svm *svm = to_svm(vcpu);
3909 * TODO: Last condition latch INIT signals on vCPU when
3910 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
3911 * To properly emulate the INIT intercept,
3912 * svm_check_nested_events() should call nested_svm_vmexit()
3913 * if an INIT signal is pending.
3915 return !gif_set(svm) ||
3916 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3919 static void svm_vm_destroy(struct kvm *kvm)
3921 avic_vm_destroy(kvm);
3922 sev_vm_destroy(kvm);
3925 static int svm_vm_init(struct kvm *kvm)
3928 int ret = avic_vm_init(kvm);
3933 kvm_apicv_init(kvm, avic);
3937 static struct kvm_x86_ops svm_x86_ops __initdata = {
3938 .hardware_unsetup = svm_hardware_teardown,
3939 .hardware_enable = svm_hardware_enable,
3940 .hardware_disable = svm_hardware_disable,
3941 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3942 .has_emulated_msr = svm_has_emulated_msr,
3944 .vcpu_create = svm_create_vcpu,
3945 .vcpu_free = svm_free_vcpu,
3946 .vcpu_reset = svm_vcpu_reset,
3948 .vm_size = sizeof(struct kvm_svm),
3949 .vm_init = svm_vm_init,
3950 .vm_destroy = svm_vm_destroy,
3952 .prepare_guest_switch = svm_prepare_guest_switch,
3953 .vcpu_load = svm_vcpu_load,
3954 .vcpu_put = svm_vcpu_put,
3955 .vcpu_blocking = svm_vcpu_blocking,
3956 .vcpu_unblocking = svm_vcpu_unblocking,
3958 .update_bp_intercept = update_bp_intercept,
3959 .get_msr_feature = svm_get_msr_feature,
3960 .get_msr = svm_get_msr,
3961 .set_msr = svm_set_msr,
3962 .get_segment_base = svm_get_segment_base,
3963 .get_segment = svm_get_segment,
3964 .set_segment = svm_set_segment,
3965 .get_cpl = svm_get_cpl,
3966 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3967 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3968 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3969 .set_cr0 = svm_set_cr0,
3970 .set_cr4 = svm_set_cr4,
3971 .set_efer = svm_set_efer,
3972 .get_idt = svm_get_idt,
3973 .set_idt = svm_set_idt,
3974 .get_gdt = svm_get_gdt,
3975 .set_gdt = svm_set_gdt,
3976 .set_dr7 = svm_set_dr7,
3977 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
3978 .cache_reg = svm_cache_reg,
3979 .get_rflags = svm_get_rflags,
3980 .set_rflags = svm_set_rflags,
3982 .tlb_flush_all = svm_flush_tlb,
3983 .tlb_flush_current = svm_flush_tlb,
3984 .tlb_flush_gva = svm_flush_tlb_gva,
3985 .tlb_flush_guest = svm_flush_tlb,
3987 .run = svm_vcpu_run,
3988 .handle_exit = handle_exit,
3989 .skip_emulated_instruction = skip_emulated_instruction,
3990 .update_emulated_instruction = NULL,
3991 .set_interrupt_shadow = svm_set_interrupt_shadow,
3992 .get_interrupt_shadow = svm_get_interrupt_shadow,
3993 .patch_hypercall = svm_patch_hypercall,
3994 .set_irq = svm_set_irq,
3995 .set_nmi = svm_inject_nmi,
3996 .queue_exception = svm_queue_exception,
3997 .cancel_injection = svm_cancel_injection,
3998 .interrupt_allowed = svm_interrupt_allowed,
3999 .nmi_allowed = svm_nmi_allowed,
4000 .get_nmi_mask = svm_get_nmi_mask,
4001 .set_nmi_mask = svm_set_nmi_mask,
4002 .enable_nmi_window = enable_nmi_window,
4003 .enable_irq_window = enable_irq_window,
4004 .update_cr8_intercept = update_cr8_intercept,
4005 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4006 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4007 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4008 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4009 .load_eoi_exitmap = svm_load_eoi_exitmap,
4010 .hwapic_irr_update = svm_hwapic_irr_update,
4011 .hwapic_isr_update = svm_hwapic_isr_update,
4012 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4013 .apicv_post_state_restore = avic_post_state_restore,
4015 .set_tss_addr = svm_set_tss_addr,
4016 .set_identity_map_addr = svm_set_identity_map_addr,
4017 .get_tdp_level = get_npt_level,
4018 .get_mt_mask = svm_get_mt_mask,
4020 .get_exit_info = svm_get_exit_info,
4022 .cpuid_update = svm_cpuid_update,
4024 .has_wbinvd_exit = svm_has_wbinvd_exit,
4026 .read_l1_tsc_offset = svm_read_l1_tsc_offset,
4027 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4029 .load_mmu_pgd = svm_load_mmu_pgd,
4031 .check_intercept = svm_check_intercept,
4032 .handle_exit_irqoff = svm_handle_exit_irqoff,
4034 .request_immediate_exit = __kvm_request_immediate_exit,
4036 .sched_in = svm_sched_in,
4038 .pmu_ops = &amd_pmu_ops,
4039 .nested_ops = &svm_nested_ops,
4041 .deliver_posted_interrupt = svm_deliver_avic_intr,
4042 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4043 .update_pi_irte = svm_update_pi_irte,
4044 .setup_mce = svm_setup_mce,
4046 .smi_allowed = svm_smi_allowed,
4047 .pre_enter_smm = svm_pre_enter_smm,
4048 .pre_leave_smm = svm_pre_leave_smm,
4049 .enable_smi_window = enable_smi_window,
4051 .mem_enc_op = svm_mem_enc_op,
4052 .mem_enc_reg_region = svm_register_enc_region,
4053 .mem_enc_unreg_region = svm_unregister_enc_region,
4055 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4057 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4060 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4061 .cpu_has_kvm_support = has_svm,
4062 .disabled_by_bios = is_disabled,
4063 .hardware_setup = svm_hardware_setup,
4064 .check_processor_compatibility = svm_check_processor_compat,
4066 .runtime_ops = &svm_x86_ops,
4069 static int __init svm_init(void)
4071 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4072 __alignof__(struct vcpu_svm), THIS_MODULE);
4075 static void __exit svm_exit(void)
4080 module_init(svm_init)
4081 module_exit(svm_exit)