arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44 #include "svm_ops.h"
  45
  46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  47
  48 MODULE_AUTHOR("Qumranet");
  49 MODULE_LICENSE("GPL");
  50
  51 #ifdef MODULE
  52 static const struct x86_cpu_id svm_cpu_id[] = {
  53         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  54         {}
  55 };
  56 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  57 #endif
  58
  59 #define SEG_TYPE_LDT 2
  60 #define SEG_TYPE_BUSY_TSS16 3
  61
  62 #define SVM_FEATURE_LBRV           (1 <<  1)
  63 #define SVM_FEATURE_SVML           (1 <<  2)
  64 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  65 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  66 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  67 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  68 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  69
  70 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  71
  72 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  73 #define TSC_RATIO_MIN           0x0000000000000001ULL
  74 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  75
  76 static bool erratum_383_found __read_mostly;
  77
  78 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  79
  80 /*
  81  * Set osvw_len to higher value when updated Revision Guides
  82  * are published and we know what the new status bits are
  83  */
  84 static uint64_t osvw_len = 4, osvw_status;
  85
  86 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  87 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  88
  89 static const struct svm_direct_access_msrs {
  90         u32 index;   /* Index of the MSR */
  91         bool always; /* True if intercept is initially cleared */
  92 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  93         { .index = MSR_STAR,                            .always = true  },
  94         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  95         { .index = MSR_IA32_SYSENTER_EIP,               .always = false },
  96         { .index = MSR_IA32_SYSENTER_ESP,               .always = false },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_EFER,                            .always = false },
 112         { .index = MSR_IA32_CR_PAT,                     .always = false },
 113         { .index = MSR_AMD64_SEV_ES_GHCB,               .always = true  },
 114         { .index = MSR_INVALID,                         .always = false },
 115 };
 116
 117 /*
 118  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 119  * pause_filter_count: On processors that support Pause filtering(indicated
 120  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 121  *      count value. On VMRUN this value is loaded into an internal counter.
 122  *      Each time a pause instruction is executed, this counter is decremented
 123  *      until it reaches zero at which time a #VMEXIT is generated if pause
 124  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 125  *      Intercept Filtering for more details.
 126  *      This also indicate if ple logic enabled.
 127  *
 128  * pause_filter_thresh: In addition, some processor families support advanced
 129  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 130  *      the amount of time a guest is allowed to execute in a pause loop.
 131  *      In this mode, a 16-bit pause filter threshold field is added in the
 132  *      VMCB. The threshold value is a cycle count that is used to reset the
 133  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 134  *      count value from VMCB into an internal counter. Then, on each pause
 135  *      instruction the hardware checks the elapsed number of cycles since
 136  *      the most recent pause instruction against the pause filter threshold.
 137  *      If the elapsed cycle count is greater than the pause filter threshold,
 138  *      then the internal pause count is reloaded from the VMCB and execution
 139  *      continues. If the elapsed cycle count is less than the pause filter
 140  *      threshold, then the internal pause count is decremented. If the count
 141  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 142  *      triggered. If advanced pause filtering is supported and pause filter
 143  *      threshold field is set to zero, the filter will operate in the simpler,
 144  *      count only mode.
 145  */
 146
 147 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 148 module_param(pause_filter_thresh, ushort, 0444);
 149
 150 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 151 module_param(pause_filter_count, ushort, 0444);
 152
 153 /* Default doubles per-vcpu window every exit. */
 154 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 155 module_param(pause_filter_count_grow, ushort, 0444);
 156
 157 /* Default resets per-vcpu window every exit to pause_filter_count. */
 158 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 159 module_param(pause_filter_count_shrink, ushort, 0444);
 160
 161 /* Default is to compute the maximum so we can never overflow. */
 162 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(pause_filter_count_max, ushort, 0444);
 164
 165 /*
 166  * Use nested page tables by default.  Note, NPT may get forced off by
 167  * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
 168  */
 169 bool npt_enabled = true;
 170 module_param_named(npt, npt_enabled, bool, 0444);
 171
 172 /* allow nested virtualization in KVM/SVM */
 173 static int nested = true;
 174 module_param(nested, int, S_IRUGO);
 175
 176 /* enable/disable Next RIP Save */
 177 static int nrips = true;
 178 module_param(nrips, int, 0444);
 179
 180 /* enable/disable Virtual VMLOAD VMSAVE */
 181 static int vls = true;
 182 module_param(vls, int, 0444);
 183
 184 /* enable/disable Virtual GIF */
 185 static int vgif = true;
 186 module_param(vgif, int, 0444);
 187
 188 bool __read_mostly dump_invalid_vmcb;
 189 module_param(dump_invalid_vmcb, bool, 0644);
 190
 191 static bool svm_gp_erratum_intercept = true;
 192
 193 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 194
 195 static unsigned long iopm_base;
 196
 197 struct kvm_ldttss_desc {
 198         u16 limit0;
 199         u16 base0;
 200         unsigned base1:8, type:5, dpl:2, p:1;
 201         unsigned limit1:4, zero0:3, g:1, base2:8;
 202         u32 base3;
 203         u32 zero1;
 204 } __attribute__((packed));
 205
 206 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 207
 208 /*
 209  * Only MSR_TSC_AUX is switched via the user return hook.  EFER is switched via
 210  * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
 211  *
 212  * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
 213  * defer the restoration of TSC_AUX until the CPU returns to userspace.
 214  */
 215 static int tsc_aux_uret_slot __read_mostly = -1;
 216
 217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 218
 219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 220 #define MSRS_RANGE_SIZE 2048
 221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 222
 223 u32 svm_msrpm_offset(u32 msr)
 224 {
 225         u32 offset;
 226         int i;
 227
 228         for (i = 0; i < NUM_MSR_MAPS; i++) {
 229                 if (msr < msrpm_ranges[i] ||
 230                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 231                         continue;
 232
 233                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 234                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 235
 236                 /* Now we have the u8 offset - but need the u32 offset */
 237                 return offset / 4;
 238         }
 239
 240         /* MSR not in any range */
 241         return MSR_INVALID;
 242 }
 243
 244 #define MAX_INST_SIZE 15
 245
 246 static int get_max_npt_level(void)
 247 {
 248 #ifdef CONFIG_X86_64
 249         return PT64_ROOT_4LEVEL;
 250 #else
 251         return PT32E_ROOT_LEVEL;
 252 #endif
 253 }
 254
 255 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 256 {
 257         struct vcpu_svm *svm = to_svm(vcpu);
 258         u64 old_efer = vcpu->arch.efer;
 259         vcpu->arch.efer = efer;
 260
 261         if (!npt_enabled) {
 262                 /* Shadow paging assumes NX to be available.  */
 263                 efer |= EFER_NX;
 264
 265                 if (!(efer & EFER_LMA))
 266                         efer &= ~EFER_LME;
 267         }
 268
 269         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 270                 if (!(efer & EFER_SVME)) {
 271                         svm_leave_nested(svm);
 272                         svm_set_gif(svm, true);
 273                         /* #GP intercept is still needed for vmware backdoor */
 274                         if (!enable_vmware_backdoor)
 275                                 clr_exception_intercept(svm, GP_VECTOR);
 276
 277                         /*
 278                          * Free the nested guest state, unless we are in SMM.
 279                          * In this case we will return to the nested guest
 280                          * as soon as we leave SMM.
 281                          */
 282                         if (!is_smm(vcpu))
 283                                 svm_free_nested(svm);
 284
 285                 } else {
 286                         int ret = svm_allocate_nested(svm);
 287
 288                         if (ret) {
 289                                 vcpu->arch.efer = old_efer;
 290                                 return ret;
 291                         }
 292
 293                         if (svm_gp_erratum_intercept)
 294                                 set_exception_intercept(svm, GP_VECTOR);
 295                 }
 296         }
 297
 298         svm->vmcb->save.efer = efer | EFER_SVME;
 299         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 300         return 0;
 301 }
 302
 303 static int is_external_interrupt(u32 info)
 304 {
 305         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 306         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 307 }
 308
 309 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 310 {
 311         struct vcpu_svm *svm = to_svm(vcpu);
 312         u32 ret = 0;
 313
 314         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 315                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 316         return ret;
 317 }
 318
 319 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (mask == 0)
 324                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 325         else
 326                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 327
 328 }
 329
 330 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 331 {
 332         struct vcpu_svm *svm = to_svm(vcpu);
 333
 334         /*
 335          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 336          * the type of exit and the #VC handler in the guest.
 337          */
 338         if (sev_es_guest(vcpu->kvm))
 339                 goto done;
 340
 341         if (nrips && svm->vmcb->control.next_rip != 0) {
 342                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 343                 svm->next_rip = svm->vmcb->control.next_rip;
 344         }
 345
 346         if (!svm->next_rip) {
 347                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 348                         return 0;
 349         } else {
 350                 kvm_rip_write(vcpu, svm->next_rip);
 351         }
 352
 353 done:
 354         svm_set_interrupt_shadow(vcpu, 0);
 355
 356         return 1;
 357 }
 358
 359 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 360 {
 361         struct vcpu_svm *svm = to_svm(vcpu);
 362         unsigned nr = vcpu->arch.exception.nr;
 363         bool has_error_code = vcpu->arch.exception.has_error_code;
 364         u32 error_code = vcpu->arch.exception.error_code;
 365
 366         kvm_deliver_exception_payload(vcpu);
 367
 368         if (nr == BP_VECTOR && !nrips) {
 369                 unsigned long rip, old_rip = kvm_rip_read(vcpu);
 370
 371                 /*
 372                  * For guest debugging where we have to reinject #BP if some
 373                  * INT3 is guest-owned:
 374                  * Emulate nRIP by moving RIP forward. Will fail if injection
 375                  * raises a fault that is not intercepted. Still better than
 376                  * failing in all cases.
 377                  */
 378                 (void)skip_emulated_instruction(vcpu);
 379                 rip = kvm_rip_read(vcpu);
 380                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 381                 svm->int3_injected = rip - old_rip;
 382         }
 383
 384         svm->vmcb->control.event_inj = nr
 385                 | SVM_EVTINJ_VALID
 386                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 387                 | SVM_EVTINJ_TYPE_EXEPT;
 388         svm->vmcb->control.event_inj_err = error_code;
 389 }
 390
 391 static void svm_init_erratum_383(void)
 392 {
 393         u32 low, high;
 394         int err;
 395         u64 val;
 396
 397         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 398                 return;
 399
 400         /* Use _safe variants to not break nested virtualization */
 401         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 402         if (err)
 403                 return;
 404
 405         val |= (1ULL << 47);
 406
 407         low  = lower_32_bits(val);
 408         high = upper_32_bits(val);
 409
 410         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 411
 412         erratum_383_found = true;
 413 }
 414
 415 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 416 {
 417         /*
 418          * Guests should see errata 400 and 415 as fixed (assuming that
 419          * HLT and IO instructions are intercepted).
 420          */
 421         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 422         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 423
 424         /*
 425          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 426          * all osvw.status bits inside that length, including bit 0 (which is
 427          * reserved for erratum 298), are valid. However, if host processor's
 428          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 429          * be conservative here and therefore we tell the guest that erratum 298
 430          * is present (because we really don't know).
 431          */
 432         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 433                 vcpu->arch.osvw.status |= 1;
 434 }
 435
 436 static int has_svm(void)
 437 {
 438         const char *msg;
 439
 440         if (!cpu_has_svm(&msg)) {
 441                 printk(KERN_INFO "has_svm: %s\n", msg);
 442                 return 0;
 443         }
 444
 445         if (sev_active()) {
 446                 pr_info("KVM is unsupported when running as an SEV guest\n");
 447                 return 0;
 448         }
 449
 450         if (pgtable_l5_enabled()) {
 451                 pr_info("KVM doesn't yet support 5-level paging on AMD SVM\n");
 452                 return 0;
 453         }
 454
 455         return 1;
 456 }
 457
 458 static void svm_hardware_disable(void)
 459 {
 460         /* Make sure we clean up behind us */
 461         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 462                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 463
 464         cpu_svm_disable();
 465
 466         amd_pmu_disable_virt();
 467 }
 468
 469 static int svm_hardware_enable(void)
 470 {
 471
 472         struct svm_cpu_data *sd;
 473         uint64_t efer;
 474         struct desc_struct *gdt;
 475         int me = raw_smp_processor_id();
 476
 477         rdmsrl(MSR_EFER, efer);
 478         if (efer & EFER_SVME)
 479                 return -EBUSY;
 480
 481         if (!has_svm()) {
 482                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 483                 return -EINVAL;
 484         }
 485         sd = per_cpu(svm_data, me);
 486         if (!sd) {
 487                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 488                 return -EINVAL;
 489         }
 490
 491         sd->asid_generation = 1;
 492         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 493         sd->next_asid = sd->max_asid + 1;
 494         sd->min_asid = max_sev_asid + 1;
 495
 496         gdt = get_current_gdt_rw();
 497         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 498
 499         wrmsrl(MSR_EFER, efer | EFER_SVME);
 500
 501         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 502
 503         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 504                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 505                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 506         }
 507
 508
 509         /*
 510          * Get OSVW bits.
 511          *
 512          * Note that it is possible to have a system with mixed processor
 513          * revisions and therefore different OSVW bits. If bits are not the same
 514          * on different processors then choose the worst case (i.e. if erratum
 515          * is present on one processor and not on another then assume that the
 516          * erratum is present everywhere).
 517          */
 518         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 519                 uint64_t len, status = 0;
 520                 int err;
 521
 522                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 523                 if (!err)
 524                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 525                                                       &err);
 526
 527                 if (err)
 528                         osvw_status = osvw_len = 0;
 529                 else {
 530                         if (len < osvw_len)
 531                                 osvw_len = len;
 532                         osvw_status |= status;
 533                         osvw_status &= (1ULL << osvw_len) - 1;
 534                 }
 535         } else
 536                 osvw_status = osvw_len = 0;
 537
 538         svm_init_erratum_383();
 539
 540         amd_pmu_enable_virt();
 541
 542         return 0;
 543 }
 544
 545 static void svm_cpu_uninit(int cpu)
 546 {
 547         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
 548
 549         if (!sd)
 550                 return;
 551
 552         per_cpu(svm_data, cpu) = NULL;
 553         kfree(sd->sev_vmcbs);
 554         __free_page(sd->save_area);
 555         kfree(sd);
 556 }
 557
 558 static int svm_cpu_init(int cpu)
 559 {
 560         struct svm_cpu_data *sd;
 561         int ret = -ENOMEM;
 562
 563         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 564         if (!sd)
 565                 return ret;
 566         sd->cpu = cpu;
 567         sd->save_area = alloc_page(GFP_KERNEL);
 568         if (!sd->save_area)
 569                 goto free_cpu_data;
 570
 571         clear_page(page_address(sd->save_area));
 572
 573         ret = sev_cpu_init(sd);
 574         if (ret)
 575                 goto free_save_area;
 576
 577         per_cpu(svm_data, cpu) = sd;
 578
 579         return 0;
 580
 581 free_save_area:
 582         __free_page(sd->save_area);
 583 free_cpu_data:
 584         kfree(sd);
 585         return ret;
 586
 587 }
 588
 589 static int direct_access_msr_slot(u32 msr)
 590 {
 591         u32 i;
 592
 593         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 594                 if (direct_access_msrs[i].index == msr)
 595                         return i;
 596
 597         return -ENOENT;
 598 }
 599
 600 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 601                                      int write)
 602 {
 603         struct vcpu_svm *svm = to_svm(vcpu);
 604         int slot = direct_access_msr_slot(msr);
 605
 606         if (slot == -ENOENT)
 607                 return;
 608
 609         /* Set the shadow bitmaps to the desired intercept states */
 610         if (read)
 611                 set_bit(slot, svm->shadow_msr_intercept.read);
 612         else
 613                 clear_bit(slot, svm->shadow_msr_intercept.read);
 614
 615         if (write)
 616                 set_bit(slot, svm->shadow_msr_intercept.write);
 617         else
 618                 clear_bit(slot, svm->shadow_msr_intercept.write);
 619 }
 620
 621 static bool valid_msr_intercept(u32 index)
 622 {
 623         return direct_access_msr_slot(index) != -ENOENT;
 624 }
 625
 626 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 627 {
 628         u8 bit_write;
 629         unsigned long tmp;
 630         u32 offset;
 631         u32 *msrpm;
 632
 633         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 634                                       to_svm(vcpu)->msrpm;
 635
 636         offset    = svm_msrpm_offset(msr);
 637         bit_write = 2 * (msr & 0x0f) + 1;
 638         tmp       = msrpm[offset];
 639
 640         BUG_ON(offset == MSR_INVALID);
 641
 642         return !!test_bit(bit_write,  &tmp);
 643 }
 644
 645 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 646                                         u32 msr, int read, int write)
 647 {
 648         u8 bit_read, bit_write;
 649         unsigned long tmp;
 650         u32 offset;
 651
 652         /*
 653          * If this warning triggers extend the direct_access_msrs list at the
 654          * beginning of the file
 655          */
 656         WARN_ON(!valid_msr_intercept(msr));
 657
 658         /* Enforce non allowed MSRs to trap */
 659         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 660                 read = 0;
 661
 662         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 663                 write = 0;
 664
 665         offset    = svm_msrpm_offset(msr);
 666         bit_read  = 2 * (msr & 0x0f);
 667         bit_write = 2 * (msr & 0x0f) + 1;
 668         tmp       = msrpm[offset];
 669
 670         BUG_ON(offset == MSR_INVALID);
 671
 672         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 673         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 674
 675         msrpm[offset] = tmp;
 676 }
 677
 678 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 679                           int read, int write)
 680 {
 681         set_shadow_msr_intercept(vcpu, msr, read, write);
 682         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 683 }
 684
 685 u32 *svm_vcpu_alloc_msrpm(void)
 686 {
 687         unsigned int order = get_order(MSRPM_SIZE);
 688         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
 689         u32 *msrpm;
 690
 691         if (!pages)
 692                 return NULL;
 693
 694         msrpm = page_address(pages);
 695         memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
 696
 697         return msrpm;
 698 }
 699
 700 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 701 {
 702         int i;
 703
 704         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 705                 if (!direct_access_msrs[i].always)
 706                         continue;
 707                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 708         }
 709 }
 710
 711
 712 void svm_vcpu_free_msrpm(u32 *msrpm)
 713 {
 714         __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
 715 }
 716
 717 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 718 {
 719         struct vcpu_svm *svm = to_svm(vcpu);
 720         u32 i;
 721
 722         /*
 723          * Set intercept permissions for all direct access MSRs again. They
 724          * will automatically get filtered through the MSR filter, so we are
 725          * back in sync after this.
 726          */
 727         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 728                 u32 msr = direct_access_msrs[i].index;
 729                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 730                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 731
 732                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 733         }
 734 }
 735
 736 static void add_msr_offset(u32 offset)
 737 {
 738         int i;
 739
 740         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 741
 742                 /* Offset already in list? */
 743                 if (msrpm_offsets[i] == offset)
 744                         return;
 745
 746                 /* Slot used by another offset? */
 747                 if (msrpm_offsets[i] != MSR_INVALID)
 748                         continue;
 749
 750                 /* Add offset to list */
 751                 msrpm_offsets[i] = offset;
 752
 753                 return;
 754         }
 755
 756         /*
 757          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 758          * increase MSRPM_OFFSETS in this case.
 759          */
 760         BUG();
 761 }
 762
 763 static void init_msrpm_offsets(void)
 764 {
 765         int i;
 766
 767         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 768
 769         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 770                 u32 offset;
 771
 772                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 773                 BUG_ON(offset == MSR_INVALID);
 774
 775                 add_msr_offset(offset);
 776         }
 777 }
 778
 779 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 780 {
 781         struct vcpu_svm *svm = to_svm(vcpu);
 782
 783         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 784         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 785         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 786         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 787         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 788 }
 789
 790 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 791 {
 792         struct vcpu_svm *svm = to_svm(vcpu);
 793
 794         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 795         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 796         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 797         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 798         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 799 }
 800
 801 void disable_nmi_singlestep(struct vcpu_svm *svm)
 802 {
 803         svm->nmi_singlestep = false;
 804
 805         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 806                 /* Clear our flags if they were not set by the guest */
 807                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 808                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 809                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 810                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 811         }
 812 }
 813
 814 static void grow_ple_window(struct kvm_vcpu *vcpu)
 815 {
 816         struct vcpu_svm *svm = to_svm(vcpu);
 817         struct vmcb_control_area *control = &svm->vmcb->control;
 818         int old = control->pause_filter_count;
 819
 820         control->pause_filter_count = __grow_ple_window(old,
 821                                                         pause_filter_count,
 822                                                         pause_filter_count_grow,
 823                                                         pause_filter_count_max);
 824
 825         if (control->pause_filter_count != old) {
 826                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 827                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 828                                             control->pause_filter_count, old);
 829         }
 830 }
 831
 832 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 833 {
 834         struct vcpu_svm *svm = to_svm(vcpu);
 835         struct vmcb_control_area *control = &svm->vmcb->control;
 836         int old = control->pause_filter_count;
 837
 838         control->pause_filter_count =
 839                                 __shrink_ple_window(old,
 840                                                     pause_filter_count,
 841                                                     pause_filter_count_shrink,
 842                                                     pause_filter_count);
 843         if (control->pause_filter_count != old) {
 844                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 845                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 846                                             control->pause_filter_count, old);
 847         }
 848 }
 849
 850 /*
 851  * The default MMIO mask is a single bit (excluding the present bit),
 852  * which could conflict with the memory encryption bit. Check for
 853  * memory encryption support and override the default MMIO mask if
 854  * memory encryption is enabled.
 855  */
 856 static __init void svm_adjust_mmio_mask(void)
 857 {
 858         unsigned int enc_bit, mask_bit;
 859         u64 msr, mask;
 860
 861         /* If there is no memory encryption support, use existing mask */
 862         if (cpuid_eax(0x80000000) < 0x8000001f)
 863                 return;
 864
 865         /* If memory encryption is not enabled, use existing mask */
 866         rdmsrl(MSR_AMD64_SYSCFG, msr);
 867         if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
 868                 return;
 869
 870         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 871         mask_bit = boot_cpu_data.x86_phys_bits;
 872
 873         /* Increment the mask bit if it is the same as the encryption bit */
 874         if (enc_bit == mask_bit)
 875                 mask_bit++;
 876
 877         /*
 878          * If the mask bit location is below 52, then some bits above the
 879          * physical addressing limit will always be reserved, so use the
 880          * rsvd_bits() function to generate the mask. This mask, along with
 881          * the present bit, will be used to generate a page fault with
 882          * PFER.RSV = 1.
 883          *
 884          * If the mask bit location is 52 (or above), then clear the mask.
 885          */
 886         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 887
 888         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 889 }
 890
 891 static void svm_hardware_teardown(void)
 892 {
 893         int cpu;
 894
 895         sev_hardware_teardown();
 896
 897         for_each_possible_cpu(cpu)
 898                 svm_cpu_uninit(cpu);
 899
 900         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
 901         get_order(IOPM_SIZE));
 902         iopm_base = 0;
 903 }
 904
 905 static __init void svm_set_cpu_caps(void)
 906 {
 907         kvm_set_cpu_caps();
 908
 909         supported_xss = 0;
 910
 911         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 912         if (nested) {
 913                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 914
 915                 if (nrips)
 916                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 917
 918                 if (npt_enabled)
 919                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 920
 921                 /* Nested VM can receive #VMEXIT instead of triggering #GP */
 922                 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
 923         }
 924
 925         /* CPUID 0x80000008 */
 926         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 927             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 928                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 929
 930         /* CPUID 0x8000001F (SME/SEV features) */
 931         sev_set_cpu_caps();
 932 }
 933
 934 static __init int svm_hardware_setup(void)
 935 {
 936         int cpu;
 937         struct page *iopm_pages;
 938         void *iopm_va;
 939         int r;
 940         unsigned int order = get_order(IOPM_SIZE);
 941
 942         iopm_pages = alloc_pages(GFP_KERNEL, order);
 943
 944         if (!iopm_pages)
 945                 return -ENOMEM;
 946
 947         iopm_va = page_address(iopm_pages);
 948         memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
 949         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 950
 951         init_msrpm_offsets();
 952
 953         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 954
 955         if (boot_cpu_has(X86_FEATURE_NX))
 956                 kvm_enable_efer_bits(EFER_NX);
 957
 958         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 959                 kvm_enable_efer_bits(EFER_FFXSR);
 960
 961         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 962                 kvm_has_tsc_control = true;
 963                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 964                 kvm_tsc_scaling_ratio_frac_bits = 32;
 965         }
 966
 967         tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
 968
 969         /* Check for pause filtering support */
 970         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 971                 pause_filter_count = 0;
 972                 pause_filter_thresh = 0;
 973         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 974                 pause_filter_thresh = 0;
 975         }
 976
 977         if (nested) {
 978                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 979                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 980         }
 981
 982         /*
 983          * KVM's MMU doesn't support using 2-level paging for itself, and thus
 984          * NPT isn't supported if the host is using 2-level paging since host
 985          * CR4 is unchanged on VMRUN.
 986          */
 987         if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
 988                 npt_enabled = false;
 989
 990         if (!boot_cpu_has(X86_FEATURE_NPT))
 991                 npt_enabled = false;
 992
 993         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 994         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 995
 996         /* Note, SEV setup consumes npt_enabled. */
 997         sev_hardware_setup();
 998
 999         svm_adjust_mmio_mask();
1000
1001         for_each_possible_cpu(cpu) {
1002                 r = svm_cpu_init(cpu);
1003                 if (r)
1004                         goto err;
1005         }
1006
1007         if (nrips) {
1008                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1009                         nrips = false;
1010         }
1011
1012         if (avic) {
1013                 if (!npt_enabled || !boot_cpu_has(X86_FEATURE_AVIC)) {
1014                         avic = false;
1015                 } else {
1016                         pr_info("AVIC enabled\n");
1017
1018                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1019                 }
1020         }
1021
1022         if (vls) {
1023                 if (!npt_enabled ||
1024                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1025                     !IS_ENABLED(CONFIG_X86_64)) {
1026                         vls = false;
1027                 } else {
1028                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1029                 }
1030         }
1031
1032         if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
1033                 svm_gp_erratum_intercept = false;
1034
1035         if (vgif) {
1036                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1037                         vgif = false;
1038                 else
1039                         pr_info("Virtual GIF supported\n");
1040         }
1041
1042         svm_set_cpu_caps();
1043
1044         /*
1045          * It seems that on AMD processors PTE's accessed bit is
1046          * being set by the CPU hardware before the NPF vmexit.
1047          * This is not expected behaviour and our tests fail because
1048          * of it.
1049          * A workaround here is to disable support for
1050          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1051          * In this case userspace can know if there is support using
1052          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1053          * it
1054          * If future AMD CPU models change the behaviour described above,
1055          * this variable can be changed accordingly
1056          */
1057         allow_smaller_maxphyaddr = !npt_enabled;
1058
1059         return 0;
1060
1061 err:
1062         svm_hardware_teardown();
1063         return r;
1064 }
1065
1066 static void init_seg(struct vmcb_seg *seg)
1067 {
1068         seg->selector = 0;
1069         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1070                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1071         seg->limit = 0xffff;
1072         seg->base = 0;
1073 }
1074
1075 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1076 {
1077         seg->selector = 0;
1078         seg->attrib = SVM_SELECTOR_P_MASK | type;
1079         seg->limit = 0xffff;
1080         seg->base = 0;
1081 }
1082
1083 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1084 {
1085         struct vcpu_svm *svm = to_svm(vcpu);
1086         u64 g_tsc_offset = 0;
1087
1088         if (is_guest_mode(vcpu)) {
1089                 /* Write L1's TSC offset.  */
1090                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1091                                svm->vmcb01.ptr->control.tsc_offset;
1092                 svm->vmcb01.ptr->control.tsc_offset = offset;
1093         }
1094
1095         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1096                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1097                                    offset);
1098
1099         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1100
1101         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1102         return svm->vmcb->control.tsc_offset;
1103 }
1104
1105 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1106 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1107                                               struct vcpu_svm *svm)
1108 {
1109         /*
1110          * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1111          * roots, or if INVPCID is disabled in the guest to inject #UD.
1112          */
1113         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1114                 if (!npt_enabled ||
1115                     !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1116                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1117                 else
1118                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1119         }
1120
1121         if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1122                 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1123                         svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1124                 else
1125                         svm_set_intercept(svm, INTERCEPT_RDTSCP);
1126         }
1127 }
1128
1129 static void init_vmcb(struct kvm_vcpu *vcpu)
1130 {
1131         struct vcpu_svm *svm = to_svm(vcpu);
1132         struct vmcb_control_area *control = &svm->vmcb->control;
1133         struct vmcb_save_area *save = &svm->vmcb->save;
1134
1135         vcpu->arch.hflags = 0;
1136
1137         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1138         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1139         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1140         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1141         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1142         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1143         if (!kvm_vcpu_apicv_active(vcpu))
1144                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1145
1146         set_dr_intercepts(svm);
1147
1148         set_exception_intercept(svm, PF_VECTOR);
1149         set_exception_intercept(svm, UD_VECTOR);
1150         set_exception_intercept(svm, MC_VECTOR);
1151         set_exception_intercept(svm, AC_VECTOR);
1152         set_exception_intercept(svm, DB_VECTOR);
1153         /*
1154          * Guest access to VMware backdoor ports could legitimately
1155          * trigger #GP because of TSS I/O permission bitmap.
1156          * We intercept those #GP and allow access to them anyway
1157          * as VMware does.
1158          */
1159         if (enable_vmware_backdoor)
1160                 set_exception_intercept(svm, GP_VECTOR);
1161
1162         svm_set_intercept(svm, INTERCEPT_INTR);
1163         svm_set_intercept(svm, INTERCEPT_NMI);
1164         svm_set_intercept(svm, INTERCEPT_SMI);
1165         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1166         svm_set_intercept(svm, INTERCEPT_RDPMC);
1167         svm_set_intercept(svm, INTERCEPT_CPUID);
1168         svm_set_intercept(svm, INTERCEPT_INVD);
1169         svm_set_intercept(svm, INTERCEPT_INVLPG);
1170         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1171         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1172         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1173         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1174         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1175         svm_set_intercept(svm, INTERCEPT_VMRUN);
1176         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1177         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1178         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1179         svm_set_intercept(svm, INTERCEPT_STGI);
1180         svm_set_intercept(svm, INTERCEPT_CLGI);
1181         svm_set_intercept(svm, INTERCEPT_SKINIT);
1182         svm_set_intercept(svm, INTERCEPT_WBINVD);
1183         svm_set_intercept(svm, INTERCEPT_XSETBV);
1184         svm_set_intercept(svm, INTERCEPT_RDPRU);
1185         svm_set_intercept(svm, INTERCEPT_RSM);
1186
1187         if (!kvm_mwait_in_guest(vcpu->kvm)) {
1188                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1189                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1190         }
1191
1192         if (!kvm_hlt_in_guest(vcpu->kvm))
1193                 svm_set_intercept(svm, INTERCEPT_HLT);
1194
1195         control->iopm_base_pa = __sme_set(iopm_base);
1196         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1197         control->int_ctl = V_INTR_MASKING_MASK;
1198
1199         init_seg(&save->es);
1200         init_seg(&save->ss);
1201         init_seg(&save->ds);
1202         init_seg(&save->fs);
1203         init_seg(&save->gs);
1204
1205         save->cs.selector = 0xf000;
1206         save->cs.base = 0xffff0000;
1207         /* Executable/Readable Code Segment */
1208         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1209                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1210         save->cs.limit = 0xffff;
1211
1212         save->gdtr.limit = 0xffff;
1213         save->idtr.limit = 0xffff;
1214
1215         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1216         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1217
1218         svm_set_cr4(vcpu, 0);
1219         svm_set_efer(vcpu, 0);
1220         save->dr6 = 0xffff0ff0;
1221         kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
1222         save->rip = 0x0000fff0;
1223         vcpu->arch.regs[VCPU_REGS_RIP] = save->rip;
1224
1225         /*
1226          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1227          * It also updates the guest-visible cr0 value.
1228          */
1229         svm_set_cr0(vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1230         kvm_mmu_reset_context(vcpu);
1231
1232         save->cr4 = X86_CR4_PAE;
1233         /* rdx = ?? */
1234
1235         if (npt_enabled) {
1236                 /* Setup VMCB for Nested Paging */
1237                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1238                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1239                 clr_exception_intercept(svm, PF_VECTOR);
1240                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1241                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1242                 save->g_pat = vcpu->arch.pat;
1243                 save->cr3 = 0;
1244                 save->cr4 = 0;
1245         }
1246         svm->current_vmcb->asid_generation = 0;
1247         svm->asid = 0;
1248
1249         svm->nested.vmcb12_gpa = INVALID_GPA;
1250         svm->nested.last_vmcb12_gpa = INVALID_GPA;
1251         vcpu->arch.hflags = 0;
1252
1253         if (!kvm_pause_in_guest(vcpu->kvm)) {
1254                 control->pause_filter_count = pause_filter_count;
1255                 if (pause_filter_thresh)
1256                         control->pause_filter_thresh = pause_filter_thresh;
1257                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1258         } else {
1259                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1260         }
1261
1262         svm_recalc_instruction_intercepts(vcpu, svm);
1263
1264         /*
1265          * If the host supports V_SPEC_CTRL then disable the interception
1266          * of MSR_IA32_SPEC_CTRL.
1267          */
1268         if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1269                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1270
1271         if (kvm_vcpu_apicv_active(vcpu))
1272                 avic_init_vmcb(svm);
1273
1274         if (vgif) {
1275                 svm_clr_intercept(svm, INTERCEPT_STGI);
1276                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1277                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1278         }
1279
1280         if (sev_guest(vcpu->kvm)) {
1281                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1282                 clr_exception_intercept(svm, UD_VECTOR);
1283
1284                 if (sev_es_guest(vcpu->kvm)) {
1285                         /* Perform SEV-ES specific VMCB updates */
1286                         sev_es_init_vmcb(svm);
1287                 }
1288         }
1289
1290         vmcb_mark_all_dirty(svm->vmcb);
1291
1292         enable_gif(svm);
1293
1294 }
1295
1296 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1297 {
1298         struct vcpu_svm *svm = to_svm(vcpu);
1299         u32 dummy;
1300         u32 eax = 1;
1301
1302         svm->spec_ctrl = 0;
1303         svm->virt_spec_ctrl = 0;
1304
1305         if (!init_event) {
1306                 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1307                                        MSR_IA32_APICBASE_ENABLE;
1308                 if (kvm_vcpu_is_reset_bsp(vcpu))
1309                         vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1310         }
1311         init_vmcb(vcpu);
1312
1313         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1314         kvm_rdx_write(vcpu, eax);
1315
1316         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1317                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1318 }
1319
1320 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1321 {
1322         svm->current_vmcb = target_vmcb;
1323         svm->vmcb = target_vmcb->ptr;
1324 }
1325
1326 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1327 {
1328         struct vcpu_svm *svm;
1329         struct page *vmcb01_page;
1330         struct page *vmsa_page = NULL;
1331         int err;
1332
1333         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1334         svm = to_svm(vcpu);
1335
1336         err = -ENOMEM;
1337         vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1338         if (!vmcb01_page)
1339                 goto out;
1340
1341         if (sev_es_guest(vcpu->kvm)) {
1342                 /*
1343                  * SEV-ES guests require a separate VMSA page used to contain
1344                  * the encrypted register state of the guest.
1345                  */
1346                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1347                 if (!vmsa_page)
1348                         goto error_free_vmcb_page;
1349
1350                 /*
1351                  * SEV-ES guests maintain an encrypted version of their FPU
1352                  * state which is restored and saved on VMRUN and VMEXIT.
1353                  * Free the fpu structure to prevent KVM from attempting to
1354                  * access the FPU state.
1355                  */
1356                 kvm_free_guest_fpu(vcpu);
1357         }
1358
1359         err = avic_init_vcpu(svm);
1360         if (err)
1361                 goto error_free_vmsa_page;
1362
1363         /* We initialize this flag to true to make sure that the is_running
1364          * bit would be set the first time the vcpu is loaded.
1365          */
1366         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1367                 svm->avic_is_running = true;
1368
1369         svm->msrpm = svm_vcpu_alloc_msrpm();
1370         if (!svm->msrpm) {
1371                 err = -ENOMEM;
1372                 goto error_free_vmsa_page;
1373         }
1374
1375         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1376
1377         svm->vmcb01.ptr = page_address(vmcb01_page);
1378         svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1379
1380         if (vmsa_page)
1381                 svm->vmsa = page_address(vmsa_page);
1382
1383         svm->guest_state_loaded = false;
1384
1385         svm_switch_vmcb(svm, &svm->vmcb01);
1386         init_vmcb(vcpu);
1387
1388         svm_init_osvw(vcpu);
1389         vcpu->arch.microcode_version = 0x01000065;
1390
1391         if (sev_es_guest(vcpu->kvm))
1392                 /* Perform SEV-ES specific VMCB creation updates */
1393                 sev_es_create_vcpu(svm);
1394
1395         return 0;
1396
1397 error_free_vmsa_page:
1398         if (vmsa_page)
1399                 __free_page(vmsa_page);
1400 error_free_vmcb_page:
1401         __free_page(vmcb01_page);
1402 out:
1403         return err;
1404 }
1405
1406 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1407 {
1408         int i;
1409
1410         for_each_online_cpu(i)
1411                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1412 }
1413
1414 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1415 {
1416         struct vcpu_svm *svm = to_svm(vcpu);
1417
1418         /*
1419          * The vmcb page can be recycled, causing a false negative in
1420          * svm_vcpu_load(). So, ensure that no logical CPU has this
1421          * vmcb page recorded as its current vmcb.
1422          */
1423         svm_clear_current_vmcb(svm->vmcb);
1424
1425         svm_free_nested(svm);
1426
1427         sev_free_vcpu(vcpu);
1428
1429         __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1430         __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1431 }
1432
1433 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
1434 {
1435         struct vcpu_svm *svm = to_svm(vcpu);
1436         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1437
1438         if (sev_es_guest(vcpu->kvm))
1439                 sev_es_unmap_ghcb(svm);
1440
1441         if (svm->guest_state_loaded)
1442                 return;
1443
1444         /*
1445          * Save additional host state that will be restored on VMEXIT (sev-es)
1446          * or subsequent vmload of host save area.
1447          */
1448         if (sev_es_guest(vcpu->kvm)) {
1449                 sev_es_prepare_guest_switch(svm, vcpu->cpu);
1450         } else {
1451                 vmsave(__sme_page_pa(sd->save_area));
1452         }
1453
1454         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1455                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1456                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1457                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1458                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1459                 }
1460         }
1461
1462         if (likely(tsc_aux_uret_slot >= 0))
1463                 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1464
1465         svm->guest_state_loaded = true;
1466 }
1467
1468 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1469 {
1470         to_svm(vcpu)->guest_state_loaded = false;
1471 }
1472
1473 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1474 {
1475         struct vcpu_svm *svm = to_svm(vcpu);
1476         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1477
1478         if (sd->current_vmcb != svm->vmcb) {
1479                 sd->current_vmcb = svm->vmcb;
1480                 indirect_branch_prediction_barrier();
1481         }
1482         avic_vcpu_load(vcpu, cpu);
1483 }
1484
1485 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1486 {
1487         avic_vcpu_put(vcpu);
1488         svm_prepare_host_switch(vcpu);
1489
1490         ++vcpu->stat.host_state_reload;
1491 }
1492
1493 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1494 {
1495         struct vcpu_svm *svm = to_svm(vcpu);
1496         unsigned long rflags = svm->vmcb->save.rflags;
1497
1498         if (svm->nmi_singlestep) {
1499                 /* Hide our flags if they were not set by the guest */
1500                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1501                         rflags &= ~X86_EFLAGS_TF;
1502                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1503                         rflags &= ~X86_EFLAGS_RF;
1504         }
1505         return rflags;
1506 }
1507
1508 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1509 {
1510         if (to_svm(vcpu)->nmi_singlestep)
1511                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1512
1513        /*
1514         * Any change of EFLAGS.VM is accompanied by a reload of SS
1515         * (caused by either a task switch or an inter-privilege IRET),
1516         * so we do not need to update the CPL here.
1517         */
1518         to_svm(vcpu)->vmcb->save.rflags = rflags;
1519 }
1520
1521 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1522 {
1523         switch (reg) {
1524         case VCPU_EXREG_PDPTR:
1525                 BUG_ON(!npt_enabled);
1526                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1527                 break;
1528         default:
1529                 WARN_ON_ONCE(1);
1530         }
1531 }
1532
1533 static void svm_set_vintr(struct vcpu_svm *svm)
1534 {
1535         struct vmcb_control_area *control;
1536
1537         /* The following fields are ignored when AVIC is enabled */
1538         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1539         svm_set_intercept(svm, INTERCEPT_VINTR);
1540
1541         /*
1542          * This is just a dummy VINTR to actually cause a vmexit to happen.
1543          * Actual injection of virtual interrupts happens through EVENTINJ.
1544          */
1545         control = &svm->vmcb->control;
1546         control->int_vector = 0x0;
1547         control->int_ctl &= ~V_INTR_PRIO_MASK;
1548         control->int_ctl |= V_IRQ_MASK |
1549                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1550         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1551 }
1552
1553 static void svm_clear_vintr(struct vcpu_svm *svm)
1554 {
1555         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1556         svm_clr_intercept(svm, INTERCEPT_VINTR);
1557
1558         /* Drop int_ctl fields related to VINTR injection.  */
1559         svm->vmcb->control.int_ctl &= mask;
1560         if (is_guest_mode(&svm->vcpu)) {
1561                 svm->vmcb01.ptr->control.int_ctl &= mask;
1562
1563                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1564                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1565                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1566         }
1567
1568         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1569 }
1570
1571 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1572 {
1573         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1574         struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1575
1576         switch (seg) {
1577         case VCPU_SREG_CS: return &save->cs;
1578         case VCPU_SREG_DS: return &save->ds;
1579         case VCPU_SREG_ES: return &save->es;
1580         case VCPU_SREG_FS: return &save01->fs;
1581         case VCPU_SREG_GS: return &save01->gs;
1582         case VCPU_SREG_SS: return &save->ss;
1583         case VCPU_SREG_TR: return &save01->tr;
1584         case VCPU_SREG_LDTR: return &save01->ldtr;
1585         }
1586         BUG();
1587         return NULL;
1588 }
1589
1590 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1591 {
1592         struct vmcb_seg *s = svm_seg(vcpu, seg);
1593
1594         return s->base;
1595 }
1596
1597 static void svm_get_segment(struct kvm_vcpu *vcpu,
1598                             struct kvm_segment *var, int seg)
1599 {
1600         struct vmcb_seg *s = svm_seg(vcpu, seg);
1601
1602         var->base = s->base;
1603         var->limit = s->limit;
1604         var->selector = s->selector;
1605         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1606         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1607         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1608         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1609         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1610         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1611         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1612
1613         /*
1614          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1615          * However, the SVM spec states that the G bit is not observed by the
1616          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1617          * So let's synthesize a legal G bit for all segments, this helps
1618          * running KVM nested. It also helps cross-vendor migration, because
1619          * Intel's vmentry has a check on the 'G' bit.
1620          */
1621         var->g = s->limit > 0xfffff;
1622
1623         /*
1624          * AMD's VMCB does not have an explicit unusable field, so emulate it
1625          * for cross vendor migration purposes by "not present"
1626          */
1627         var->unusable = !var->present;
1628
1629         switch (seg) {
1630         case VCPU_SREG_TR:
1631                 /*
1632                  * Work around a bug where the busy flag in the tr selector
1633                  * isn't exposed
1634                  */
1635                 var->type |= 0x2;
1636                 break;
1637         case VCPU_SREG_DS:
1638         case VCPU_SREG_ES:
1639         case VCPU_SREG_FS:
1640         case VCPU_SREG_GS:
1641                 /*
1642                  * The accessed bit must always be set in the segment
1643                  * descriptor cache, although it can be cleared in the
1644                  * descriptor, the cached bit always remains at 1. Since
1645                  * Intel has a check on this, set it here to support
1646                  * cross-vendor migration.
1647                  */
1648                 if (!var->unusable)
1649                         var->type |= 0x1;
1650                 break;
1651         case VCPU_SREG_SS:
1652                 /*
1653                  * On AMD CPUs sometimes the DB bit in the segment
1654                  * descriptor is left as 1, although the whole segment has
1655                  * been made unusable. Clear it here to pass an Intel VMX
1656                  * entry check when cross vendor migrating.
1657                  */
1658                 if (var->unusable)
1659                         var->db = 0;
1660                 /* This is symmetric with svm_set_segment() */
1661                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1662                 break;
1663         }
1664 }
1665
1666 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1667 {
1668         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1669
1670         return save->cpl;
1671 }
1672
1673 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1674 {
1675         struct vcpu_svm *svm = to_svm(vcpu);
1676
1677         dt->size = svm->vmcb->save.idtr.limit;
1678         dt->address = svm->vmcb->save.idtr.base;
1679 }
1680
1681 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1682 {
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684
1685         svm->vmcb->save.idtr.limit = dt->size;
1686         svm->vmcb->save.idtr.base = dt->address ;
1687         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1688 }
1689
1690 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1691 {
1692         struct vcpu_svm *svm = to_svm(vcpu);
1693
1694         dt->size = svm->vmcb->save.gdtr.limit;
1695         dt->address = svm->vmcb->save.gdtr.base;
1696 }
1697
1698 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1699 {
1700         struct vcpu_svm *svm = to_svm(vcpu);
1701
1702         svm->vmcb->save.gdtr.limit = dt->size;
1703         svm->vmcb->save.gdtr.base = dt->address ;
1704         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1705 }
1706
1707 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1708 {
1709         struct vcpu_svm *svm = to_svm(vcpu);
1710         u64 hcr0 = cr0;
1711
1712 #ifdef CONFIG_X86_64
1713         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1714                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1715                         vcpu->arch.efer |= EFER_LMA;
1716                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1717                 }
1718
1719                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1720                         vcpu->arch.efer &= ~EFER_LMA;
1721                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1722                 }
1723         }
1724 #endif
1725         vcpu->arch.cr0 = cr0;
1726
1727         if (!npt_enabled)
1728                 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1729
1730         /*
1731          * re-enable caching here because the QEMU bios
1732          * does not do it - this results in some delay at
1733          * reboot
1734          */
1735         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1736                 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1737
1738         svm->vmcb->save.cr0 = hcr0;
1739         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1740
1741         /*
1742          * SEV-ES guests must always keep the CR intercepts cleared. CR
1743          * tracking is done using the CR write traps.
1744          */
1745         if (sev_es_guest(vcpu->kvm))
1746                 return;
1747
1748         if (hcr0 == cr0) {
1749                 /* Selective CR0 write remains on.  */
1750                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1751                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1752         } else {
1753                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1754                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1755         }
1756 }
1757
1758 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1759 {
1760         return true;
1761 }
1762
1763 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1764 {
1765         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1766         unsigned long old_cr4 = vcpu->arch.cr4;
1767
1768         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1769                 svm_flush_tlb(vcpu);
1770
1771         vcpu->arch.cr4 = cr4;
1772         if (!npt_enabled)
1773                 cr4 |= X86_CR4_PAE;
1774         cr4 |= host_cr4_mce;
1775         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1776         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1777
1778         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1779                 kvm_update_cpuid_runtime(vcpu);
1780 }
1781
1782 static void svm_set_segment(struct kvm_vcpu *vcpu,
1783                             struct kvm_segment *var, int seg)
1784 {
1785         struct vcpu_svm *svm = to_svm(vcpu);
1786         struct vmcb_seg *s = svm_seg(vcpu, seg);
1787
1788         s->base = var->base;
1789         s->limit = var->limit;
1790         s->selector = var->selector;
1791         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1792         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1793         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1794         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1795         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1796         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1797         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1798         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1799
1800         /*
1801          * This is always accurate, except if SYSRET returned to a segment
1802          * with SS.DPL != 3.  Intel does not have this quirk, and always
1803          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1804          * would entail passing the CPL to userspace and back.
1805          */
1806         if (seg == VCPU_SREG_SS)
1807                 /* This is symmetric with svm_get_segment() */
1808                 svm->vmcb->save.cpl = (var->dpl & 3);
1809
1810         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1811 }
1812
1813 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1814 {
1815         struct vcpu_svm *svm = to_svm(vcpu);
1816
1817         clr_exception_intercept(svm, BP_VECTOR);
1818
1819         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1820                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1821                         set_exception_intercept(svm, BP_VECTOR);
1822         }
1823 }
1824
1825 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1826 {
1827         if (sd->next_asid > sd->max_asid) {
1828                 ++sd->asid_generation;
1829                 sd->next_asid = sd->min_asid;
1830                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1831                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1832         }
1833
1834         svm->current_vmcb->asid_generation = sd->asid_generation;
1835         svm->asid = sd->next_asid++;
1836 }
1837
1838 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1839 {
1840         struct vmcb *vmcb = svm->vmcb;
1841
1842         if (svm->vcpu.arch.guest_state_protected)
1843                 return;
1844
1845         if (unlikely(value != vmcb->save.dr6)) {
1846                 vmcb->save.dr6 = value;
1847                 vmcb_mark_dirty(vmcb, VMCB_DR);
1848         }
1849 }
1850
1851 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1852 {
1853         struct vcpu_svm *svm = to_svm(vcpu);
1854
1855         if (vcpu->arch.guest_state_protected)
1856                 return;
1857
1858         get_debugreg(vcpu->arch.db[0], 0);
1859         get_debugreg(vcpu->arch.db[1], 1);
1860         get_debugreg(vcpu->arch.db[2], 2);
1861         get_debugreg(vcpu->arch.db[3], 3);
1862         /*
1863          * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1864          * because db_interception might need it.  We can do it before vmentry.
1865          */
1866         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1867         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1868         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1869         set_dr_intercepts(svm);
1870 }
1871
1872 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1873 {
1874         struct vcpu_svm *svm = to_svm(vcpu);
1875
1876         if (vcpu->arch.guest_state_protected)
1877                 return;
1878
1879         svm->vmcb->save.dr7 = value;
1880         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1881 }
1882
1883 static int pf_interception(struct kvm_vcpu *vcpu)
1884 {
1885         struct vcpu_svm *svm = to_svm(vcpu);
1886
1887         u64 fault_address = svm->vmcb->control.exit_info_2;
1888         u64 error_code = svm->vmcb->control.exit_info_1;
1889
1890         return kvm_handle_page_fault(vcpu, error_code, fault_address,
1891                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1892                         svm->vmcb->control.insn_bytes : NULL,
1893                         svm->vmcb->control.insn_len);
1894 }
1895
1896 static int npf_interception(struct kvm_vcpu *vcpu)
1897 {
1898         struct vcpu_svm *svm = to_svm(vcpu);
1899
1900         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1901         u64 error_code = svm->vmcb->control.exit_info_1;
1902
1903         trace_kvm_page_fault(fault_address, error_code);
1904         return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1905                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1906                         svm->vmcb->control.insn_bytes : NULL,
1907                         svm->vmcb->control.insn_len);
1908 }
1909
1910 static int db_interception(struct kvm_vcpu *vcpu)
1911 {
1912         struct kvm_run *kvm_run = vcpu->run;
1913         struct vcpu_svm *svm = to_svm(vcpu);
1914
1915         if (!(vcpu->guest_debug &
1916               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1917                 !svm->nmi_singlestep) {
1918                 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
1919                 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
1920                 return 1;
1921         }
1922
1923         if (svm->nmi_singlestep) {
1924                 disable_nmi_singlestep(svm);
1925                 /* Make sure we check for pending NMIs upon entry */
1926                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1927         }
1928
1929         if (vcpu->guest_debug &
1930             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1931                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1932                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1933                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1934                 kvm_run->debug.arch.pc =
1935                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1936                 kvm_run->debug.arch.exception = DB_VECTOR;
1937                 return 0;
1938         }
1939
1940         return 1;
1941 }
1942
1943 static int bp_interception(struct kvm_vcpu *vcpu)
1944 {
1945         struct vcpu_svm *svm = to_svm(vcpu);
1946         struct kvm_run *kvm_run = vcpu->run;
1947
1948         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1949         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1950         kvm_run->debug.arch.exception = BP_VECTOR;
1951         return 0;
1952 }
1953
1954 static int ud_interception(struct kvm_vcpu *vcpu)
1955 {
1956         return handle_ud(vcpu);
1957 }
1958
1959 static int ac_interception(struct kvm_vcpu *vcpu)
1960 {
1961         kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
1962         return 1;
1963 }
1964
1965 static bool is_erratum_383(void)
1966 {
1967         int err, i;
1968         u64 value;
1969
1970         if (!erratum_383_found)
1971                 return false;
1972
1973         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1974         if (err)
1975                 return false;
1976
1977         /* Bit 62 may or may not be set for this mce */
1978         value &= ~(1ULL << 62);
1979
1980         if (value != 0xb600000000010015ULL)
1981                 return false;
1982
1983         /* Clear MCi_STATUS registers */
1984         for (i = 0; i < 6; ++i)
1985                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1986
1987         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1988         if (!err) {
1989                 u32 low, high;
1990
1991                 value &= ~(1ULL << 2);
1992                 low    = lower_32_bits(value);
1993                 high   = upper_32_bits(value);
1994
1995                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1996         }
1997
1998         /* Flush tlb to evict multi-match entries */
1999         __flush_tlb_all();
2000
2001         return true;
2002 }
2003
2004 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2005 {
2006         if (is_erratum_383()) {
2007                 /*
2008                  * Erratum 383 triggered. Guest state is corrupt so kill the
2009                  * guest.
2010                  */
2011                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2012
2013                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2014
2015                 return;
2016         }
2017
2018         /*
2019          * On an #MC intercept the MCE handler is not called automatically in
2020          * the host. So do it by hand here.
2021          */
2022         kvm_machine_check();
2023 }
2024
2025 static int mc_interception(struct kvm_vcpu *vcpu)
2026 {
2027         return 1;
2028 }
2029
2030 static int shutdown_interception(struct kvm_vcpu *vcpu)
2031 {
2032         struct kvm_run *kvm_run = vcpu->run;
2033         struct vcpu_svm *svm = to_svm(vcpu);
2034
2035         /*
2036          * The VM save area has already been encrypted so it
2037          * cannot be reinitialized - just terminate.
2038          */
2039         if (sev_es_guest(vcpu->kvm))
2040                 return -EINVAL;
2041
2042         /*
2043          * VMCB is undefined after a SHUTDOWN intercept
2044          * so reinitialize it.
2045          */
2046         clear_page(svm->vmcb);
2047         init_vmcb(vcpu);
2048
2049         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2050         return 0;
2051 }
2052
2053 static int io_interception(struct kvm_vcpu *vcpu)
2054 {
2055         struct vcpu_svm *svm = to_svm(vcpu);
2056         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2057         int size, in, string;
2058         unsigned port;
2059
2060         ++vcpu->stat.io_exits;
2061         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2062         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2063         port = io_info >> 16;
2064         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2065
2066         if (string) {
2067                 if (sev_es_guest(vcpu->kvm))
2068                         return sev_es_string_io(svm, size, port, in);
2069                 else
2070                         return kvm_emulate_instruction(vcpu, 0);
2071         }
2072
2073         svm->next_rip = svm->vmcb->control.exit_info_2;
2074
2075         return kvm_fast_pio(vcpu, size, port, in);
2076 }
2077
2078 static int nmi_interception(struct kvm_vcpu *vcpu)
2079 {
2080         return 1;
2081 }
2082
2083 static int intr_interception(struct kvm_vcpu *vcpu)
2084 {
2085         ++vcpu->stat.irq_exits;
2086         return 1;
2087 }
2088
2089 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2090 {
2091         struct vcpu_svm *svm = to_svm(vcpu);
2092         struct vmcb *vmcb12;
2093         struct kvm_host_map map;
2094         int ret;
2095
2096         if (nested_svm_check_permissions(vcpu))
2097                 return 1;
2098
2099         ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2100         if (ret) {
2101                 if (ret == -EINVAL)
2102                         kvm_inject_gp(vcpu, 0);
2103                 return 1;
2104         }
2105
2106         vmcb12 = map.hva;
2107
2108         ret = kvm_skip_emulated_instruction(vcpu);
2109
2110         if (vmload) {
2111                 nested_svm_vmloadsave(vmcb12, svm->vmcb);
2112                 svm->sysenter_eip_hi = 0;
2113                 svm->sysenter_esp_hi = 0;
2114         } else
2115                 nested_svm_vmloadsave(svm->vmcb, vmcb12);
2116
2117         kvm_vcpu_unmap(vcpu, &map, true);
2118
2119         return ret;
2120 }
2121
2122 static int vmload_interception(struct kvm_vcpu *vcpu)
2123 {
2124         return vmload_vmsave_interception(vcpu, true);
2125 }
2126
2127 static int vmsave_interception(struct kvm_vcpu *vcpu)
2128 {
2129         return vmload_vmsave_interception(vcpu, false);
2130 }
2131
2132 static int vmrun_interception(struct kvm_vcpu *vcpu)
2133 {
2134         if (nested_svm_check_permissions(vcpu))
2135                 return 1;
2136
2137         return nested_svm_vmrun(vcpu);
2138 }
2139
2140 enum {
2141         NONE_SVM_INSTR,
2142         SVM_INSTR_VMRUN,
2143         SVM_INSTR_VMLOAD,
2144         SVM_INSTR_VMSAVE,
2145 };
2146
2147 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2148 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2149 {
2150         struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2151
2152         if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2153                 return NONE_SVM_INSTR;
2154
2155         switch (ctxt->modrm) {
2156         case 0xd8: /* VMRUN */
2157                 return SVM_INSTR_VMRUN;
2158         case 0xda: /* VMLOAD */
2159                 return SVM_INSTR_VMLOAD;
2160         case 0xdb: /* VMSAVE */
2161                 return SVM_INSTR_VMSAVE;
2162         default:
2163                 break;
2164         }
2165
2166         return NONE_SVM_INSTR;
2167 }
2168
2169 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2170 {
2171         const int guest_mode_exit_codes[] = {
2172                 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2173                 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2174                 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2175         };
2176         int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2177                 [SVM_INSTR_VMRUN] = vmrun_interception,
2178                 [SVM_INSTR_VMLOAD] = vmload_interception,
2179                 [SVM_INSTR_VMSAVE] = vmsave_interception,
2180         };
2181         struct vcpu_svm *svm = to_svm(vcpu);
2182         int ret;
2183
2184         if (is_guest_mode(vcpu)) {
2185                 /* Returns '1' or -errno on failure, '0' on success. */
2186                 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2187                 if (ret)
2188                         return ret;
2189                 return 1;
2190         }
2191         return svm_instr_handlers[opcode](vcpu);
2192 }
2193
2194 /*
2195  * #GP handling code. Note that #GP can be triggered under the following two
2196  * cases:
2197  *   1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2198  *      some AMD CPUs when EAX of these instructions are in the reserved memory
2199  *      regions (e.g. SMM memory on host).
2200  *   2) VMware backdoor
2201  */
2202 static int gp_interception(struct kvm_vcpu *vcpu)
2203 {
2204         struct vcpu_svm *svm = to_svm(vcpu);
2205         u32 error_code = svm->vmcb->control.exit_info_1;
2206         int opcode;
2207
2208         /* Both #GP cases have zero error_code */
2209         if (error_code)
2210                 goto reinject;
2211
2212         /* Decode the instruction for usage later */
2213         if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2214                 goto reinject;
2215
2216         opcode = svm_instr_opcode(vcpu);
2217
2218         if (opcode == NONE_SVM_INSTR) {
2219                 if (!enable_vmware_backdoor)
2220                         goto reinject;
2221
2222                 /*
2223                  * VMware backdoor emulation on #GP interception only handles
2224                  * IN{S}, OUT{S}, and RDPMC.
2225                  */
2226                 if (!is_guest_mode(vcpu))
2227                         return kvm_emulate_instruction(vcpu,
2228                                 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2229         } else
2230                 return emulate_svm_instr(vcpu, opcode);
2231
2232 reinject:
2233         kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2234         return 1;
2235 }
2236
2237 void svm_set_gif(struct vcpu_svm *svm, bool value)
2238 {
2239         if (value) {
2240                 /*
2241                  * If VGIF is enabled, the STGI intercept is only added to
2242                  * detect the opening of the SMI/NMI window; remove it now.
2243                  * Likewise, clear the VINTR intercept, we will set it
2244                  * again while processing KVM_REQ_EVENT if needed.
2245                  */
2246                 if (vgif_enabled(svm))
2247                         svm_clr_intercept(svm, INTERCEPT_STGI);
2248                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2249                         svm_clear_vintr(svm);
2250
2251                 enable_gif(svm);
2252                 if (svm->vcpu.arch.smi_pending ||
2253                     svm->vcpu.arch.nmi_pending ||
2254                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2255                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2256         } else {
2257                 disable_gif(svm);
2258
2259                 /*
2260                  * After a CLGI no interrupts should come.  But if vGIF is
2261                  * in use, we still rely on the VINTR intercept (rather than
2262                  * STGI) to detect an open interrupt window.
2263                 */
2264                 if (!vgif_enabled(svm))
2265                         svm_clear_vintr(svm);
2266         }
2267 }
2268
2269 static int stgi_interception(struct kvm_vcpu *vcpu)
2270 {
2271         int ret;
2272
2273         if (nested_svm_check_permissions(vcpu))
2274                 return 1;
2275
2276         ret = kvm_skip_emulated_instruction(vcpu);
2277         svm_set_gif(to_svm(vcpu), true);
2278         return ret;
2279 }
2280
2281 static int clgi_interception(struct kvm_vcpu *vcpu)
2282 {
2283         int ret;
2284
2285         if (nested_svm_check_permissions(vcpu))
2286                 return 1;
2287
2288         ret = kvm_skip_emulated_instruction(vcpu);
2289         svm_set_gif(to_svm(vcpu), false);
2290         return ret;
2291 }
2292
2293 static int invlpga_interception(struct kvm_vcpu *vcpu)
2294 {
2295         gva_t gva = kvm_rax_read(vcpu);
2296         u32 asid = kvm_rcx_read(vcpu);
2297
2298         /* FIXME: Handle an address size prefix. */
2299         if (!is_long_mode(vcpu))
2300                 gva = (u32)gva;
2301
2302         trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2303
2304         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2305         kvm_mmu_invlpg(vcpu, gva);
2306
2307         return kvm_skip_emulated_instruction(vcpu);
2308 }
2309
2310 static int skinit_interception(struct kvm_vcpu *vcpu)
2311 {
2312         trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2313
2314         kvm_queue_exception(vcpu, UD_VECTOR);
2315         return 1;
2316 }
2317
2318 static int task_switch_interception(struct kvm_vcpu *vcpu)
2319 {
2320         struct vcpu_svm *svm = to_svm(vcpu);
2321         u16 tss_selector;
2322         int reason;
2323         int int_type = svm->vmcb->control.exit_int_info &
2324                 SVM_EXITINTINFO_TYPE_MASK;
2325         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2326         uint32_t type =
2327                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2328         uint32_t idt_v =
2329                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2330         bool has_error_code = false;
2331         u32 error_code = 0;
2332
2333         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2334
2335         if (svm->vmcb->control.exit_info_2 &
2336             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2337                 reason = TASK_SWITCH_IRET;
2338         else if (svm->vmcb->control.exit_info_2 &
2339                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2340                 reason = TASK_SWITCH_JMP;
2341         else if (idt_v)
2342                 reason = TASK_SWITCH_GATE;
2343         else
2344                 reason = TASK_SWITCH_CALL;
2345
2346         if (reason == TASK_SWITCH_GATE) {
2347                 switch (type) {
2348                 case SVM_EXITINTINFO_TYPE_NMI:
2349                         vcpu->arch.nmi_injected = false;
2350                         break;
2351                 case SVM_EXITINTINFO_TYPE_EXEPT:
2352                         if (svm->vmcb->control.exit_info_2 &
2353                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2354                                 has_error_code = true;
2355                                 error_code =
2356                                         (u32)svm->vmcb->control.exit_info_2;
2357                         }
2358                         kvm_clear_exception_queue(vcpu);
2359                         break;
2360                 case SVM_EXITINTINFO_TYPE_INTR:
2361                         kvm_clear_interrupt_queue(vcpu);
2362                         break;
2363                 default:
2364                         break;
2365                 }
2366         }
2367
2368         if (reason != TASK_SWITCH_GATE ||
2369             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2370             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2371              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2372                 if (!skip_emulated_instruction(vcpu))
2373                         return 0;
2374         }
2375
2376         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2377                 int_vec = -1;
2378
2379         return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2380                                has_error_code, error_code);
2381 }
2382
2383 static int iret_interception(struct kvm_vcpu *vcpu)
2384 {
2385         struct vcpu_svm *svm = to_svm(vcpu);
2386
2387         ++vcpu->stat.nmi_window_exits;
2388         vcpu->arch.hflags |= HF_IRET_MASK;
2389         if (!sev_es_guest(vcpu->kvm)) {
2390                 svm_clr_intercept(svm, INTERCEPT_IRET);
2391                 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2392         }
2393         kvm_make_request(KVM_REQ_EVENT, vcpu);
2394         return 1;
2395 }
2396
2397 static int invlpg_interception(struct kvm_vcpu *vcpu)
2398 {
2399         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2400                 return kvm_emulate_instruction(vcpu, 0);
2401
2402         kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2403         return kvm_skip_emulated_instruction(vcpu);
2404 }
2405
2406 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2407 {
2408         return kvm_emulate_instruction(vcpu, 0);
2409 }
2410
2411 static int rsm_interception(struct kvm_vcpu *vcpu)
2412 {
2413         return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2414 }
2415
2416 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2417                                             unsigned long val)
2418 {
2419         struct vcpu_svm *svm = to_svm(vcpu);
2420         unsigned long cr0 = vcpu->arch.cr0;
2421         bool ret = false;
2422
2423         if (!is_guest_mode(vcpu) ||
2424             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2425                 return false;
2426
2427         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2428         val &= ~SVM_CR0_SELECTIVE_MASK;
2429
2430         if (cr0 ^ val) {
2431                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2432                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2433         }
2434
2435         return ret;
2436 }
2437
2438 #define CR_VALID (1ULL << 63)
2439
2440 static int cr_interception(struct kvm_vcpu *vcpu)
2441 {
2442         struct vcpu_svm *svm = to_svm(vcpu);
2443         int reg, cr;
2444         unsigned long val;
2445         int err;
2446
2447         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2448                 return emulate_on_interception(vcpu);
2449
2450         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2451                 return emulate_on_interception(vcpu);
2452
2453         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2454         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2455                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2456         else
2457                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2458
2459         err = 0;
2460         if (cr >= 16) { /* mov to cr */
2461                 cr -= 16;
2462                 val = kvm_register_read(vcpu, reg);
2463                 trace_kvm_cr_write(cr, val);
2464                 switch (cr) {
2465                 case 0:
2466                         if (!check_selective_cr0_intercepted(vcpu, val))
2467                                 err = kvm_set_cr0(vcpu, val);
2468                         else
2469                                 return 1;
2470
2471                         break;
2472                 case 3:
2473                         err = kvm_set_cr3(vcpu, val);
2474                         break;
2475                 case 4:
2476                         err = kvm_set_cr4(vcpu, val);
2477                         break;
2478                 case 8:
2479                         err = kvm_set_cr8(vcpu, val);
2480                         break;
2481                 default:
2482                         WARN(1, "unhandled write to CR%d", cr);
2483                         kvm_queue_exception(vcpu, UD_VECTOR);
2484                         return 1;
2485                 }
2486         } else { /* mov from cr */
2487                 switch (cr) {
2488                 case 0:
2489                         val = kvm_read_cr0(vcpu);
2490                         break;
2491                 case 2:
2492                         val = vcpu->arch.cr2;
2493                         break;
2494                 case 3:
2495                         val = kvm_read_cr3(vcpu);
2496                         break;
2497                 case 4:
2498                         val = kvm_read_cr4(vcpu);
2499                         break;
2500                 case 8:
2501                         val = kvm_get_cr8(vcpu);
2502                         break;
2503                 default:
2504                         WARN(1, "unhandled read from CR%d", cr);
2505                         kvm_queue_exception(vcpu, UD_VECTOR);
2506                         return 1;
2507                 }
2508                 kvm_register_write(vcpu, reg, val);
2509                 trace_kvm_cr_read(cr, val);
2510         }
2511         return kvm_complete_insn_gp(vcpu, err);
2512 }
2513
2514 static int cr_trap(struct kvm_vcpu *vcpu)
2515 {
2516         struct vcpu_svm *svm = to_svm(vcpu);
2517         unsigned long old_value, new_value;
2518         unsigned int cr;
2519         int ret = 0;
2520
2521         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2522
2523         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2524         switch (cr) {
2525         case 0:
2526                 old_value = kvm_read_cr0(vcpu);
2527                 svm_set_cr0(vcpu, new_value);
2528
2529                 kvm_post_set_cr0(vcpu, old_value, new_value);
2530                 break;
2531         case 4:
2532                 old_value = kvm_read_cr4(vcpu);
2533                 svm_set_cr4(vcpu, new_value);
2534
2535                 kvm_post_set_cr4(vcpu, old_value, new_value);
2536                 break;
2537         case 8:
2538                 ret = kvm_set_cr8(vcpu, new_value);
2539                 break;
2540         default:
2541                 WARN(1, "unhandled CR%d write trap", cr);
2542                 kvm_queue_exception(vcpu, UD_VECTOR);
2543                 return 1;
2544         }
2545
2546         return kvm_complete_insn_gp(vcpu, ret);
2547 }
2548
2549 static int dr_interception(struct kvm_vcpu *vcpu)
2550 {
2551         struct vcpu_svm *svm = to_svm(vcpu);
2552         int reg, dr;
2553         unsigned long val;
2554         int err = 0;
2555
2556         if (vcpu->guest_debug == 0) {
2557                 /*
2558                  * No more DR vmexits; force a reload of the debug registers
2559                  * and reenter on this instruction.  The next vmexit will
2560                  * retrieve the full state of the debug registers.
2561                  */
2562                 clr_dr_intercepts(svm);
2563                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2564                 return 1;
2565         }
2566
2567         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2568                 return emulate_on_interception(vcpu);
2569
2570         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2571         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2572         if (dr >= 16) { /* mov to DRn  */
2573                 dr -= 16;
2574                 val = kvm_register_read(vcpu, reg);
2575                 err = kvm_set_dr(vcpu, dr, val);
2576         } else {
2577                 kvm_get_dr(vcpu, dr, &val);
2578                 kvm_register_write(vcpu, reg, val);
2579         }
2580
2581         return kvm_complete_insn_gp(vcpu, err);
2582 }
2583
2584 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2585 {
2586         int r;
2587
2588         u8 cr8_prev = kvm_get_cr8(vcpu);
2589         /* instruction emulation calls kvm_set_cr8() */
2590         r = cr_interception(vcpu);
2591         if (lapic_in_kernel(vcpu))
2592                 return r;
2593         if (cr8_prev <= kvm_get_cr8(vcpu))
2594                 return r;
2595         vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2596         return 0;
2597 }
2598
2599 static int efer_trap(struct kvm_vcpu *vcpu)
2600 {
2601         struct msr_data msr_info;
2602         int ret;
2603
2604         /*
2605          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2606          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2607          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2608          * the guest doesn't have X86_FEATURE_SVM.
2609          */
2610         msr_info.host_initiated = false;
2611         msr_info.index = MSR_EFER;
2612         msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2613         ret = kvm_set_msr_common(vcpu, &msr_info);
2614
2615         return kvm_complete_insn_gp(vcpu, ret);
2616 }
2617
2618 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2619 {
2620         msr->data = 0;
2621
2622         switch (msr->index) {
2623         case MSR_F10H_DECFG:
2624                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2625                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2626                 break;
2627         case MSR_IA32_PERF_CAPABILITIES:
2628                 return 0;
2629         default:
2630                 return KVM_MSR_RET_INVALID;
2631         }
2632
2633         return 0;
2634 }
2635
2636 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2637 {
2638         struct vcpu_svm *svm = to_svm(vcpu);
2639
2640         switch (msr_info->index) {
2641         case MSR_STAR:
2642                 msr_info->data = svm->vmcb01.ptr->save.star;
2643                 break;
2644 #ifdef CONFIG_X86_64
2645         case MSR_LSTAR:
2646                 msr_info->data = svm->vmcb01.ptr->save.lstar;
2647                 break;
2648         case MSR_CSTAR:
2649                 msr_info->data = svm->vmcb01.ptr->save.cstar;
2650                 break;
2651         case MSR_KERNEL_GS_BASE:
2652                 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2653                 break;
2654         case MSR_SYSCALL_MASK:
2655                 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2656                 break;
2657 #endif
2658         case MSR_IA32_SYSENTER_CS:
2659                 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2660                 break;
2661         case MSR_IA32_SYSENTER_EIP:
2662                 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2663                 if (guest_cpuid_is_intel(vcpu))
2664                         msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2665                 break;
2666         case MSR_IA32_SYSENTER_ESP:
2667                 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2668                 if (guest_cpuid_is_intel(vcpu))
2669                         msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2670                 break;
2671         case MSR_TSC_AUX:
2672                 msr_info->data = svm->tsc_aux;
2673                 break;
2674         /*
2675          * Nobody will change the following 5 values in the VMCB so we can
2676          * safely return them on rdmsr. They will always be 0 until LBRV is
2677          * implemented.
2678          */
2679         case MSR_IA32_DEBUGCTLMSR:
2680                 msr_info->data = svm->vmcb->save.dbgctl;
2681                 break;
2682         case MSR_IA32_LASTBRANCHFROMIP:
2683                 msr_info->data = svm->vmcb->save.br_from;
2684                 break;
2685         case MSR_IA32_LASTBRANCHTOIP:
2686                 msr_info->data = svm->vmcb->save.br_to;
2687                 break;
2688         case MSR_IA32_LASTINTFROMIP:
2689                 msr_info->data = svm->vmcb->save.last_excp_from;
2690                 break;
2691         case MSR_IA32_LASTINTTOIP:
2692                 msr_info->data = svm->vmcb->save.last_excp_to;
2693                 break;
2694         case MSR_VM_HSAVE_PA:
2695                 msr_info->data = svm->nested.hsave_msr;
2696                 break;
2697         case MSR_VM_CR:
2698                 msr_info->data = svm->nested.vm_cr_msr;
2699                 break;
2700         case MSR_IA32_SPEC_CTRL:
2701                 if (!msr_info->host_initiated &&
2702                     !guest_has_spec_ctrl_msr(vcpu))
2703                         return 1;
2704
2705                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2706                         msr_info->data = svm->vmcb->save.spec_ctrl;
2707                 else
2708                         msr_info->data = svm->spec_ctrl;
2709                 break;
2710         case MSR_AMD64_VIRT_SPEC_CTRL:
2711                 if (!msr_info->host_initiated &&
2712                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2713                         return 1;
2714
2715                 msr_info->data = svm->virt_spec_ctrl;
2716                 break;
2717         case MSR_F15H_IC_CFG: {
2718
2719                 int family, model;
2720
2721                 family = guest_cpuid_family(vcpu);
2722                 model  = guest_cpuid_model(vcpu);
2723
2724                 if (family < 0 || model < 0)
2725                         return kvm_get_msr_common(vcpu, msr_info);
2726
2727                 msr_info->data = 0;
2728
2729                 if (family == 0x15 &&
2730                     (model >= 0x2 && model < 0x20))
2731                         msr_info->data = 0x1E;
2732                 }
2733                 break;
2734         case MSR_F10H_DECFG:
2735                 msr_info->data = svm->msr_decfg;
2736                 break;
2737         default:
2738                 return kvm_get_msr_common(vcpu, msr_info);
2739         }
2740         return 0;
2741 }
2742
2743 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2744 {
2745         struct vcpu_svm *svm = to_svm(vcpu);
2746         if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->ghcb))
2747                 return kvm_complete_insn_gp(vcpu, err);
2748
2749         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2750         ghcb_set_sw_exit_info_2(svm->ghcb,
2751                                 X86_TRAP_GP |
2752                                 SVM_EVTINJ_TYPE_EXEPT |
2753                                 SVM_EVTINJ_VALID);
2754         return 1;
2755 }
2756
2757 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2758 {
2759         struct vcpu_svm *svm = to_svm(vcpu);
2760         int svm_dis, chg_mask;
2761
2762         if (data & ~SVM_VM_CR_VALID_MASK)
2763                 return 1;
2764
2765         chg_mask = SVM_VM_CR_VALID_MASK;
2766
2767         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2768                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2769
2770         svm->nested.vm_cr_msr &= ~chg_mask;
2771         svm->nested.vm_cr_msr |= (data & chg_mask);
2772
2773         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2774
2775         /* check for svm_disable while efer.svme is set */
2776         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2777                 return 1;
2778
2779         return 0;
2780 }
2781
2782 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2783 {
2784         struct vcpu_svm *svm = to_svm(vcpu);
2785         int r;
2786
2787         u32 ecx = msr->index;
2788         u64 data = msr->data;
2789         switch (ecx) {
2790         case MSR_IA32_CR_PAT:
2791                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2792                         return 1;
2793                 vcpu->arch.pat = data;
2794                 svm->vmcb01.ptr->save.g_pat = data;
2795                 if (is_guest_mode(vcpu))
2796                         nested_vmcb02_compute_g_pat(svm);
2797                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2798                 break;
2799         case MSR_IA32_SPEC_CTRL:
2800                 if (!msr->host_initiated &&
2801                     !guest_has_spec_ctrl_msr(vcpu))
2802                         return 1;
2803
2804                 if (kvm_spec_ctrl_test_value(data))
2805                         return 1;
2806
2807                 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2808                         svm->vmcb->save.spec_ctrl = data;
2809                 else
2810                         svm->spec_ctrl = data;
2811                 if (!data)
2812                         break;
2813
2814                 /*
2815                  * For non-nested:
2816                  * When it's written (to non-zero) for the first time, pass
2817                  * it through.
2818                  *
2819                  * For nested:
2820                  * The handling of the MSR bitmap for L2 guests is done in
2821                  * nested_svm_vmrun_msrpm.
2822                  * We update the L1 MSR bit as well since it will end up
2823                  * touching the MSR anyway now.
2824                  */
2825                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2826                 break;
2827         case MSR_IA32_PRED_CMD:
2828                 if (!msr->host_initiated &&
2829                     !guest_has_pred_cmd_msr(vcpu))
2830                         return 1;
2831
2832                 if (data & ~PRED_CMD_IBPB)
2833                         return 1;
2834                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2835                         return 1;
2836                 if (!data)
2837                         break;
2838
2839                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2840                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2841                 break;
2842         case MSR_AMD64_VIRT_SPEC_CTRL:
2843                 if (!msr->host_initiated &&
2844                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2845                         return 1;
2846
2847                 if (data & ~SPEC_CTRL_SSBD)
2848                         return 1;
2849
2850                 svm->virt_spec_ctrl = data;
2851                 break;
2852         case MSR_STAR:
2853                 svm->vmcb01.ptr->save.star = data;
2854                 break;
2855 #ifdef CONFIG_X86_64
2856         case MSR_LSTAR:
2857                 svm->vmcb01.ptr->save.lstar = data;
2858                 break;
2859         case MSR_CSTAR:
2860                 svm->vmcb01.ptr->save.cstar = data;
2861                 break;
2862         case MSR_KERNEL_GS_BASE:
2863                 svm->vmcb01.ptr->save.kernel_gs_base = data;
2864                 break;
2865         case MSR_SYSCALL_MASK:
2866                 svm->vmcb01.ptr->save.sfmask = data;
2867                 break;
2868 #endif
2869         case MSR_IA32_SYSENTER_CS:
2870                 svm->vmcb01.ptr->save.sysenter_cs = data;
2871                 break;
2872         case MSR_IA32_SYSENTER_EIP:
2873                 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2874                 /*
2875                  * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2876                  * when we spoof an Intel vendor ID (for cross vendor migration).
2877                  * In this case we use this intercept to track the high
2878                  * 32 bit part of these msrs to support Intel's
2879                  * implementation of SYSENTER/SYSEXIT.
2880                  */
2881                 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2882                 break;
2883         case MSR_IA32_SYSENTER_ESP:
2884                 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
2885                 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
2886                 break;
2887         case MSR_TSC_AUX:
2888                 /*
2889                  * TSC_AUX is usually changed only during boot and never read
2890                  * directly.  Intercept TSC_AUX instead of exposing it to the
2891                  * guest via direct_access_msrs, and switch it via user return.
2892                  */
2893                 preempt_disable();
2894                 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
2895                 preempt_enable();
2896                 if (r)
2897                         return 1;
2898
2899                 svm->tsc_aux = data;
2900                 break;
2901         case MSR_IA32_DEBUGCTLMSR:
2902                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2903                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2904                                     __func__, data);
2905                         break;
2906                 }
2907                 if (data & DEBUGCTL_RESERVED_BITS)
2908                         return 1;
2909
2910                 svm->vmcb->save.dbgctl = data;
2911                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2912                 if (data & (1ULL<<0))
2913                         svm_enable_lbrv(vcpu);
2914                 else
2915                         svm_disable_lbrv(vcpu);
2916                 break;
2917         case MSR_VM_HSAVE_PA:
2918                 svm->nested.hsave_msr = data;
2919                 break;
2920         case MSR_VM_CR:
2921                 return svm_set_vm_cr(vcpu, data);
2922         case MSR_VM_IGNNE:
2923                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2924                 break;
2925         case MSR_F10H_DECFG: {
2926                 struct kvm_msr_entry msr_entry;
2927
2928                 msr_entry.index = msr->index;
2929                 if (svm_get_msr_feature(&msr_entry))
2930                         return 1;
2931
2932                 /* Check the supported bits */
2933                 if (data & ~msr_entry.data)
2934                         return 1;
2935
2936                 /* Don't allow the guest to change a bit, #GP */
2937                 if (!msr->host_initiated && (data ^ msr_entry.data))
2938                         return 1;
2939
2940                 svm->msr_decfg = data;
2941                 break;
2942         }
2943         case MSR_IA32_APICBASE:
2944                 if (kvm_vcpu_apicv_active(vcpu))
2945                         avic_update_vapic_bar(to_svm(vcpu), data);
2946                 fallthrough;
2947         default:
2948                 return kvm_set_msr_common(vcpu, msr);
2949         }
2950         return 0;
2951 }
2952
2953 static int msr_interception(struct kvm_vcpu *vcpu)
2954 {
2955         if (to_svm(vcpu)->vmcb->control.exit_info_1)
2956                 return kvm_emulate_wrmsr(vcpu);
2957         else
2958                 return kvm_emulate_rdmsr(vcpu);
2959 }
2960
2961 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
2962 {
2963         kvm_make_request(KVM_REQ_EVENT, vcpu);
2964         svm_clear_vintr(to_svm(vcpu));
2965
2966         /*
2967          * For AVIC, the only reason to end up here is ExtINTs.
2968          * In this case AVIC was temporarily disabled for
2969          * requesting the IRQ window and we have to re-enable it.
2970          */
2971         svm_toggle_avic_for_irq_window(vcpu, true);
2972
2973         ++vcpu->stat.irq_window_exits;
2974         return 1;
2975 }
2976
2977 static int pause_interception(struct kvm_vcpu *vcpu)
2978 {
2979         bool in_kernel;
2980
2981         /*
2982          * CPL is not made available for an SEV-ES guest, therefore
2983          * vcpu->arch.preempted_in_kernel can never be true.  Just
2984          * set in_kernel to false as well.
2985          */
2986         in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
2987
2988         if (!kvm_pause_in_guest(vcpu->kvm))
2989                 grow_ple_window(vcpu);
2990
2991         kvm_vcpu_on_spin(vcpu, in_kernel);
2992         return kvm_skip_emulated_instruction(vcpu);
2993 }
2994
2995 static int invpcid_interception(struct kvm_vcpu *vcpu)
2996 {
2997         struct vcpu_svm *svm = to_svm(vcpu);
2998         unsigned long type;
2999         gva_t gva;
3000
3001         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3002                 kvm_queue_exception(vcpu, UD_VECTOR);
3003                 return 1;
3004         }
3005
3006         /*
3007          * For an INVPCID intercept:
3008          * EXITINFO1 provides the linear address of the memory operand.
3009          * EXITINFO2 provides the contents of the register operand.
3010          */
3011         type = svm->vmcb->control.exit_info_2;
3012         gva = svm->vmcb->control.exit_info_1;
3013
3014         if (type > 3) {
3015                 kvm_inject_gp(vcpu, 0);
3016                 return 1;
3017         }
3018
3019         return kvm_handle_invpcid(vcpu, type, gva);
3020 }
3021
3022 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3023         [SVM_EXIT_READ_CR0]                     = cr_interception,
3024         [SVM_EXIT_READ_CR3]                     = cr_interception,
3025         [SVM_EXIT_READ_CR4]                     = cr_interception,
3026         [SVM_EXIT_READ_CR8]                     = cr_interception,
3027         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
3028         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
3029         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
3030         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
3031         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
3032         [SVM_EXIT_READ_DR0]                     = dr_interception,
3033         [SVM_EXIT_READ_DR1]                     = dr_interception,
3034         [SVM_EXIT_READ_DR2]                     = dr_interception,
3035         [SVM_EXIT_READ_DR3]                     = dr_interception,
3036         [SVM_EXIT_READ_DR4]                     = dr_interception,
3037         [SVM_EXIT_READ_DR5]                     = dr_interception,
3038         [SVM_EXIT_READ_DR6]                     = dr_interception,
3039         [SVM_EXIT_READ_DR7]                     = dr_interception,
3040         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3041         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3042         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3043         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3044         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3045         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3046         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3047         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3048         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3049         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3050         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3051         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3052         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3053         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3054         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3055         [SVM_EXIT_INTR]                         = intr_interception,
3056         [SVM_EXIT_NMI]                          = nmi_interception,
3057         [SVM_EXIT_SMI]                          = kvm_emulate_as_nop,
3058         [SVM_EXIT_INIT]                         = kvm_emulate_as_nop,
3059         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3060         [SVM_EXIT_RDPMC]                        = kvm_emulate_rdpmc,
3061         [SVM_EXIT_CPUID]                        = kvm_emulate_cpuid,
3062         [SVM_EXIT_IRET]                         = iret_interception,
3063         [SVM_EXIT_INVD]                         = kvm_emulate_invd,
3064         [SVM_EXIT_PAUSE]                        = pause_interception,
3065         [SVM_EXIT_HLT]                          = kvm_emulate_halt,
3066         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3067         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3068         [SVM_EXIT_IOIO]                         = io_interception,
3069         [SVM_EXIT_MSR]                          = msr_interception,
3070         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3071         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3072         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3073         [SVM_EXIT_VMMCALL]                      = kvm_emulate_hypercall,
3074         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3075         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3076         [SVM_EXIT_STGI]                         = stgi_interception,
3077         [SVM_EXIT_CLGI]                         = clgi_interception,
3078         [SVM_EXIT_SKINIT]                       = skinit_interception,
3079         [SVM_EXIT_RDTSCP]                       = kvm_handle_invalid_op,
3080         [SVM_EXIT_WBINVD]                       = kvm_emulate_wbinvd,
3081         [SVM_EXIT_MONITOR]                      = kvm_emulate_monitor,
3082         [SVM_EXIT_MWAIT]                        = kvm_emulate_mwait,
3083         [SVM_EXIT_XSETBV]                       = kvm_emulate_xsetbv,
3084         [SVM_EXIT_RDPRU]                        = kvm_handle_invalid_op,
3085         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3086         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3087         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3088         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3089         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3090         [SVM_EXIT_NPF]                          = npf_interception,
3091         [SVM_EXIT_RSM]                          = rsm_interception,
3092         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3093         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3094         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3095 };
3096
3097 static void dump_vmcb(struct kvm_vcpu *vcpu)
3098 {
3099         struct vcpu_svm *svm = to_svm(vcpu);
3100         struct vmcb_control_area *control = &svm->vmcb->control;
3101         struct vmcb_save_area *save = &svm->vmcb->save;
3102         struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3103
3104         if (!dump_invalid_vmcb) {
3105                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3106                 return;
3107         }
3108
3109         pr_err("VMCB Control Area:\n");
3110         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3111         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3112         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3113         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3114         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3115         pr_err("%-20s%08x %08x\n", "intercepts:",
3116               control->intercepts[INTERCEPT_WORD3],
3117                control->intercepts[INTERCEPT_WORD4]);
3118         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3119         pr_err("%-20s%d\n", "pause filter threshold:",
3120                control->pause_filter_thresh);
3121         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3122         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3123         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3124         pr_err("%-20s%d\n", "asid:", control->asid);
3125         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3126         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3127         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3128         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3129         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3130         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3131         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3132         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3133         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3134         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3135         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3136         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3137         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3138         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3139         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3140         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3141         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3142         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3143         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3144         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3145         pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3146         pr_err("VMCB State Save Area:\n");
3147         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3148                "es:",
3149                save->es.selector, save->es.attrib,
3150                save->es.limit, save->es.base);
3151         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3152                "cs:",
3153                save->cs.selector, save->cs.attrib,
3154                save->cs.limit, save->cs.base);
3155         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3156                "ss:",
3157                save->ss.selector, save->ss.attrib,
3158                save->ss.limit, save->ss.base);
3159         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3160                "ds:",
3161                save->ds.selector, save->ds.attrib,
3162                save->ds.limit, save->ds.base);
3163         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3164                "fs:",
3165                save01->fs.selector, save01->fs.attrib,
3166                save01->fs.limit, save01->fs.base);
3167         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3168                "gs:",
3169                save01->gs.selector, save01->gs.attrib,
3170                save01->gs.limit, save01->gs.base);
3171         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3172                "gdtr:",
3173                save->gdtr.selector, save->gdtr.attrib,
3174                save->gdtr.limit, save->gdtr.base);
3175         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3176                "ldtr:",
3177                save01->ldtr.selector, save01->ldtr.attrib,
3178                save01->ldtr.limit, save01->ldtr.base);
3179         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3180                "idtr:",
3181                save->idtr.selector, save->idtr.attrib,
3182                save->idtr.limit, save->idtr.base);
3183         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3184                "tr:",
3185                save01->tr.selector, save01->tr.attrib,
3186                save01->tr.limit, save01->tr.base);
3187         pr_err("cpl:            %d                efer:         %016llx\n",
3188                 save->cpl, save->efer);
3189         pr_err("%-15s %016llx %-13s %016llx\n",
3190                "cr0:", save->cr0, "cr2:", save->cr2);
3191         pr_err("%-15s %016llx %-13s %016llx\n",
3192                "cr3:", save->cr3, "cr4:", save->cr4);
3193         pr_err("%-15s %016llx %-13s %016llx\n",
3194                "dr6:", save->dr6, "dr7:", save->dr7);
3195         pr_err("%-15s %016llx %-13s %016llx\n",
3196                "rip:", save->rip, "rflags:", save->rflags);
3197         pr_err("%-15s %016llx %-13s %016llx\n",
3198                "rsp:", save->rsp, "rax:", save->rax);
3199         pr_err("%-15s %016llx %-13s %016llx\n",
3200                "star:", save01->star, "lstar:", save01->lstar);
3201         pr_err("%-15s %016llx %-13s %016llx\n",
3202                "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3203         pr_err("%-15s %016llx %-13s %016llx\n",
3204                "kernel_gs_base:", save01->kernel_gs_base,
3205                "sysenter_cs:", save01->sysenter_cs);
3206         pr_err("%-15s %016llx %-13s %016llx\n",
3207                "sysenter_esp:", save01->sysenter_esp,
3208                "sysenter_eip:", save01->sysenter_eip);
3209         pr_err("%-15s %016llx %-13s %016llx\n",
3210                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3211         pr_err("%-15s %016llx %-13s %016llx\n",
3212                "br_from:", save->br_from, "br_to:", save->br_to);
3213         pr_err("%-15s %016llx %-13s %016llx\n",
3214                "excp_from:", save->last_excp_from,
3215                "excp_to:", save->last_excp_to);
3216 }
3217
3218 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3219 {
3220         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3221             svm_exit_handlers[exit_code])
3222                 return 0;
3223
3224         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3225         dump_vmcb(vcpu);
3226         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3227         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3228         vcpu->run->internal.ndata = 2;
3229         vcpu->run->internal.data[0] = exit_code;
3230         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3231
3232         return -EINVAL;
3233 }
3234
3235 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3236 {
3237         if (svm_handle_invalid_exit(vcpu, exit_code))
3238                 return 0;
3239
3240 #ifdef CONFIG_RETPOLINE
3241         if (exit_code == SVM_EXIT_MSR)
3242                 return msr_interception(vcpu);
3243         else if (exit_code == SVM_EXIT_VINTR)
3244                 return interrupt_window_interception(vcpu);
3245         else if (exit_code == SVM_EXIT_INTR)
3246                 return intr_interception(vcpu);
3247         else if (exit_code == SVM_EXIT_HLT)
3248                 return kvm_emulate_halt(vcpu);
3249         else if (exit_code == SVM_EXIT_NPF)
3250                 return npf_interception(vcpu);
3251 #endif
3252         return svm_exit_handlers[exit_code](vcpu);
3253 }
3254
3255 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3256                               u32 *intr_info, u32 *error_code)
3257 {
3258         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3259
3260         *info1 = control->exit_info_1;
3261         *info2 = control->exit_info_2;
3262         *intr_info = control->exit_int_info;
3263         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3264             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3265                 *error_code = control->exit_int_info_err;
3266         else
3267                 *error_code = 0;
3268 }
3269
3270 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3271 {
3272         struct vcpu_svm *svm = to_svm(vcpu);
3273         struct kvm_run *kvm_run = vcpu->run;
3274         u32 exit_code = svm->vmcb->control.exit_code;
3275
3276         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3277
3278         /* SEV-ES guests must use the CR write traps to track CR registers. */
3279         if (!sev_es_guest(vcpu->kvm)) {
3280                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3281                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3282                 if (npt_enabled)
3283                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3284         }
3285
3286         if (is_guest_mode(vcpu)) {
3287                 int vmexit;
3288
3289                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3290
3291                 vmexit = nested_svm_exit_special(svm);
3292
3293                 if (vmexit == NESTED_EXIT_CONTINUE)
3294                         vmexit = nested_svm_exit_handled(svm);
3295
3296                 if (vmexit == NESTED_EXIT_DONE)
3297                         return 1;
3298         }
3299
3300         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3301                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3302                 kvm_run->fail_entry.hardware_entry_failure_reason
3303                         = svm->vmcb->control.exit_code;
3304                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3305                 dump_vmcb(vcpu);
3306                 return 0;
3307         }
3308
3309         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3310             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3311             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3312             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3313                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3314                        "exit_code 0x%x\n",
3315                        __func__, svm->vmcb->control.exit_int_info,
3316                        exit_code);
3317
3318         if (exit_fastpath != EXIT_FASTPATH_NONE)
3319                 return 1;
3320
3321         return svm_invoke_exit_handler(vcpu, exit_code);
3322 }
3323
3324 static void reload_tss(struct kvm_vcpu *vcpu)
3325 {
3326         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3327
3328         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3329         load_TR_desc();
3330 }
3331
3332 static void pre_svm_run(struct kvm_vcpu *vcpu)
3333 {
3334         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3335         struct vcpu_svm *svm = to_svm(vcpu);
3336
3337         /*
3338          * If the previous vmrun of the vmcb occurred on a different physical
3339          * cpu, then mark the vmcb dirty and assign a new asid.  Hardware's
3340          * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3341          */
3342         if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3343                 svm->current_vmcb->asid_generation = 0;
3344                 vmcb_mark_all_dirty(svm->vmcb);
3345                 svm->current_vmcb->cpu = vcpu->cpu;
3346         }
3347
3348         if (sev_guest(vcpu->kvm))
3349                 return pre_sev_run(svm, vcpu->cpu);
3350
3351         /* FIXME: handle wraparound of asid_generation */
3352         if (svm->current_vmcb->asid_generation != sd->asid_generation)
3353                 new_asid(svm, sd);
3354 }
3355
3356 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3357 {
3358         struct vcpu_svm *svm = to_svm(vcpu);
3359
3360         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3361         vcpu->arch.hflags |= HF_NMI_MASK;
3362         if (!sev_es_guest(vcpu->kvm))
3363                 svm_set_intercept(svm, INTERCEPT_IRET);
3364         ++vcpu->stat.nmi_injections;
3365 }
3366
3367 static void svm_set_irq(struct kvm_vcpu *vcpu)
3368 {
3369         struct vcpu_svm *svm = to_svm(vcpu);
3370
3371         BUG_ON(!(gif_set(svm)));
3372
3373         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3374         ++vcpu->stat.irq_injections;
3375
3376         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3377                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3378 }
3379
3380 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3381 {
3382         struct vcpu_svm *svm = to_svm(vcpu);
3383
3384         /*
3385          * SEV-ES guests must always keep the CR intercepts cleared. CR
3386          * tracking is done using the CR write traps.
3387          */
3388         if (sev_es_guest(vcpu->kvm))
3389                 return;
3390
3391         if (nested_svm_virtualize_tpr(vcpu))
3392                 return;
3393
3394         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3395
3396         if (irr == -1)
3397                 return;
3398
3399         if (tpr >= irr)
3400                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3401 }
3402
3403 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3404 {
3405         struct vcpu_svm *svm = to_svm(vcpu);
3406         struct vmcb *vmcb = svm->vmcb;
3407         bool ret;
3408
3409         if (!gif_set(svm))
3410                 return true;
3411
3412         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3413                 return false;
3414
3415         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3416               (vcpu->arch.hflags & HF_NMI_MASK);
3417
3418         return ret;
3419 }
3420
3421 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3422 {
3423         struct vcpu_svm *svm = to_svm(vcpu);
3424         if (svm->nested.nested_run_pending)
3425                 return -EBUSY;
3426
3427         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3428         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3429                 return -EBUSY;
3430
3431         return !svm_nmi_blocked(vcpu);
3432 }
3433
3434 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3435 {
3436         return !!(vcpu->arch.hflags & HF_NMI_MASK);
3437 }
3438
3439 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3440 {
3441         struct vcpu_svm *svm = to_svm(vcpu);
3442
3443         if (masked) {
3444                 vcpu->arch.hflags |= HF_NMI_MASK;
3445                 if (!sev_es_guest(vcpu->kvm))
3446                         svm_set_intercept(svm, INTERCEPT_IRET);
3447         } else {
3448                 vcpu->arch.hflags &= ~HF_NMI_MASK;
3449                 if (!sev_es_guest(vcpu->kvm))
3450                         svm_clr_intercept(svm, INTERCEPT_IRET);
3451         }
3452 }
3453
3454 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3455 {
3456         struct vcpu_svm *svm = to_svm(vcpu);
3457         struct vmcb *vmcb = svm->vmcb;
3458
3459         if (!gif_set(svm))
3460                 return true;
3461
3462         if (sev_es_guest(vcpu->kvm)) {
3463                 /*
3464                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3465                  * bit to determine the state of the IF flag.
3466                  */
3467                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3468                         return true;
3469         } else if (is_guest_mode(vcpu)) {
3470                 /* As long as interrupts are being delivered...  */
3471                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3472                     ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3473                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3474                         return true;
3475
3476                 /* ... vmexits aren't blocked by the interrupt shadow  */
3477                 if (nested_exit_on_intr(svm))
3478                         return false;
3479         } else {
3480                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3481                         return true;
3482         }
3483
3484         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3485 }
3486
3487 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3488 {
3489         struct vcpu_svm *svm = to_svm(vcpu);
3490         if (svm->nested.nested_run_pending)
3491                 return -EBUSY;
3492
3493         /*
3494          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3495          * e.g. if the IRQ arrived asynchronously after checking nested events.
3496          */
3497         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3498                 return -EBUSY;
3499
3500         return !svm_interrupt_blocked(vcpu);
3501 }
3502
3503 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3504 {
3505         struct vcpu_svm *svm = to_svm(vcpu);
3506
3507         /*
3508          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3509          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3510          * get that intercept, this function will be called again though and
3511          * we'll get the vintr intercept. However, if the vGIF feature is
3512          * enabled, the STGI interception will not occur. Enable the irq
3513          * window under the assumption that the hardware will set the GIF.
3514          */
3515         if (vgif_enabled(svm) || gif_set(svm)) {
3516                 /*
3517                  * IRQ window is not needed when AVIC is enabled,
3518                  * unless we have pending ExtINT since it cannot be injected
3519                  * via AVIC. In such case, we need to temporarily disable AVIC,
3520                  * and fallback to injecting IRQ via V_IRQ.
3521                  */
3522                 svm_toggle_avic_for_irq_window(vcpu, false);
3523                 svm_set_vintr(svm);
3524         }
3525 }
3526
3527 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3528 {
3529         struct vcpu_svm *svm = to_svm(vcpu);
3530
3531         if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3532                 return; /* IRET will cause a vm exit */
3533
3534         if (!gif_set(svm)) {
3535                 if (vgif_enabled(svm))
3536                         svm_set_intercept(svm, INTERCEPT_STGI);
3537                 return; /* STGI will cause a vm exit */
3538         }
3539
3540         /*
3541          * Something prevents NMI from been injected. Single step over possible
3542          * problem (IRET or exception injection or interrupt shadow)
3543          */
3544         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3545         svm->nmi_singlestep = true;
3546         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3547 }
3548
3549 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3550 {
3551         return 0;
3552 }
3553
3554 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3555 {
3556         return 0;
3557 }
3558
3559 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3560 {
3561         struct vcpu_svm *svm = to_svm(vcpu);
3562
3563         /*
3564          * Flush only the current ASID even if the TLB flush was invoked via
3565          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3566          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3567          * unconditionally does a TLB flush on both nested VM-Enter and nested
3568          * VM-Exit (via kvm_mmu_reset_context()).
3569          */
3570         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3571                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3572         else
3573                 svm->current_vmcb->asid_generation--;
3574 }
3575
3576 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3577 {
3578         struct vcpu_svm *svm = to_svm(vcpu);
3579
3580         invlpga(gva, svm->vmcb->control.asid);
3581 }
3582
3583 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3584 {
3585         struct vcpu_svm *svm = to_svm(vcpu);
3586
3587         if (nested_svm_virtualize_tpr(vcpu))
3588                 return;
3589
3590         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3591                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3592                 kvm_set_cr8(vcpu, cr8);
3593         }
3594 }
3595
3596 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3597 {
3598         struct vcpu_svm *svm = to_svm(vcpu);
3599         u64 cr8;
3600
3601         if (nested_svm_virtualize_tpr(vcpu) ||
3602             kvm_vcpu_apicv_active(vcpu))
3603                 return;
3604
3605         cr8 = kvm_get_cr8(vcpu);
3606         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3607         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3608 }
3609
3610 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3611 {
3612         struct vcpu_svm *svm = to_svm(vcpu);
3613         u8 vector;
3614         int type;
3615         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3616         unsigned int3_injected = svm->int3_injected;
3617
3618         svm->int3_injected = 0;
3619
3620         /*
3621          * If we've made progress since setting HF_IRET_MASK, we've
3622          * executed an IRET and can allow NMI injection.
3623          */
3624         if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3625             (sev_es_guest(vcpu->kvm) ||
3626              kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3627                 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3628                 kvm_make_request(KVM_REQ_EVENT, vcpu);
3629         }
3630
3631         vcpu->arch.nmi_injected = false;
3632         kvm_clear_exception_queue(vcpu);
3633         kvm_clear_interrupt_queue(vcpu);
3634
3635         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3636                 return;
3637
3638         kvm_make_request(KVM_REQ_EVENT, vcpu);
3639
3640         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3641         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3642
3643         switch (type) {
3644         case SVM_EXITINTINFO_TYPE_NMI:
3645                 vcpu->arch.nmi_injected = true;
3646                 break;
3647         case SVM_EXITINTINFO_TYPE_EXEPT:
3648                 /*
3649                  * Never re-inject a #VC exception.
3650                  */
3651                 if (vector == X86_TRAP_VC)
3652                         break;
3653
3654                 /*
3655                  * In case of software exceptions, do not reinject the vector,
3656                  * but re-execute the instruction instead. Rewind RIP first
3657                  * if we emulated INT3 before.
3658                  */
3659                 if (kvm_exception_is_soft(vector)) {
3660                         if (vector == BP_VECTOR && int3_injected &&
3661                             kvm_is_linear_rip(vcpu, svm->int3_rip))
3662                                 kvm_rip_write(vcpu,
3663                                               kvm_rip_read(vcpu) - int3_injected);
3664                         break;
3665                 }
3666                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3667                         u32 err = svm->vmcb->control.exit_int_info_err;
3668                         kvm_requeue_exception_e(vcpu, vector, err);
3669
3670                 } else
3671                         kvm_requeue_exception(vcpu, vector);
3672                 break;
3673         case SVM_EXITINTINFO_TYPE_INTR:
3674                 kvm_queue_interrupt(vcpu, vector, false);
3675                 break;
3676         default:
3677                 break;
3678         }
3679 }
3680
3681 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3682 {
3683         struct vcpu_svm *svm = to_svm(vcpu);
3684         struct vmcb_control_area *control = &svm->vmcb->control;
3685
3686         control->exit_int_info = control->event_inj;
3687         control->exit_int_info_err = control->event_inj_err;
3688         control->event_inj = 0;
3689         svm_complete_interrupts(vcpu);
3690 }
3691
3692 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3693 {
3694         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3695             to_svm(vcpu)->vmcb->control.exit_info_1)
3696                 return handle_fastpath_set_msr_irqoff(vcpu);
3697
3698         return EXIT_FASTPATH_NONE;
3699 }
3700
3701 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3702 {
3703         struct vcpu_svm *svm = to_svm(vcpu);
3704         unsigned long vmcb_pa = svm->current_vmcb->pa;
3705
3706         kvm_guest_enter_irqoff();
3707
3708         if (sev_es_guest(vcpu->kvm)) {
3709                 __svm_sev_es_vcpu_run(vmcb_pa);
3710         } else {
3711                 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3712
3713                 /*
3714                  * Use a single vmcb (vmcb01 because it's always valid) for
3715                  * context switching guest state via VMLOAD/VMSAVE, that way
3716                  * the state doesn't need to be copied between vmcb01 and
3717                  * vmcb02 when switching vmcbs for nested virtualization.
3718                  */
3719                 vmload(svm->vmcb01.pa);
3720                 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3721                 vmsave(svm->vmcb01.pa);
3722
3723                 vmload(__sme_page_pa(sd->save_area));
3724         }
3725
3726         kvm_guest_exit_irqoff();
3727 }
3728
3729 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3730 {
3731         struct vcpu_svm *svm = to_svm(vcpu);
3732
3733         trace_kvm_entry(vcpu);
3734
3735         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3736         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3737         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3738
3739         /*
3740          * Disable singlestep if we're injecting an interrupt/exception.
3741          * We don't want our modified rflags to be pushed on the stack where
3742          * we might not be able to easily reset them if we disabled NMI
3743          * singlestep later.
3744          */
3745         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3746                 /*
3747                  * Event injection happens before external interrupts cause a
3748                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3749                  * is enough to force an immediate vmexit.
3750                  */
3751                 disable_nmi_singlestep(svm);
3752                 smp_send_reschedule(vcpu->cpu);
3753         }
3754
3755         pre_svm_run(vcpu);
3756
3757         sync_lapic_to_cr8(vcpu);
3758
3759         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3760                 svm->vmcb->control.asid = svm->asid;
3761                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3762         }
3763         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3764
3765         /*
3766          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3767          * of a #DB.
3768          */
3769         if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3770                 svm_set_dr6(svm, vcpu->arch.dr6);
3771         else
3772                 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3773
3774         clgi();
3775         kvm_load_guest_xsave_state(vcpu);
3776
3777         kvm_wait_lapic_expire(vcpu);
3778
3779         /*
3780          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3781          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3782          * is no need to worry about the conditional branch over the wrmsr
3783          * being speculatively taken.
3784          */
3785         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3786                 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3787
3788         svm_vcpu_enter_exit(vcpu);
3789
3790         /*
3791          * We do not use IBRS in the kernel. If this vCPU has used the
3792          * SPEC_CTRL MSR it may have left it on; save the value and
3793          * turn it off. This is much more efficient than blindly adding
3794          * it to the atomic save/restore list. Especially as the former
3795          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3796          *
3797          * For non-nested case:
3798          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3799          * save it.
3800          *
3801          * For nested case:
3802          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3803          * save it.
3804          */
3805         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
3806             unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3807                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3808
3809         if (!sev_es_guest(vcpu->kvm))
3810                 reload_tss(vcpu);
3811
3812         if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
3813                 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3814
3815         if (!sev_es_guest(vcpu->kvm)) {
3816                 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3817                 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3818                 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3819                 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3820         }
3821
3822         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3823                 kvm_before_interrupt(vcpu);
3824
3825         kvm_load_host_xsave_state(vcpu);
3826         stgi();
3827
3828         /* Any pending NMI will happen here */
3829
3830         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3831                 kvm_after_interrupt(vcpu);
3832
3833         sync_cr8_to_lapic(vcpu);
3834
3835         svm->next_rip = 0;
3836         if (is_guest_mode(vcpu)) {
3837                 nested_sync_control_from_vmcb02(svm);
3838                 svm->nested.nested_run_pending = 0;
3839         }
3840
3841         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3842         vmcb_mark_all_clean(svm->vmcb);
3843
3844         /* if exit due to PF check for async PF */
3845         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3846                 vcpu->arch.apf.host_apf_flags =
3847                         kvm_read_and_reset_apf_flags();
3848
3849         if (npt_enabled) {
3850                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3851                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3852         }
3853
3854         /*
3855          * We need to handle MC intercepts here before the vcpu has a chance to
3856          * change the physical cpu
3857          */
3858         if (unlikely(svm->vmcb->control.exit_code ==
3859                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3860                 svm_handle_mce(vcpu);
3861
3862         svm_complete_interrupts(vcpu);
3863
3864         if (is_guest_mode(vcpu))
3865                 return EXIT_FASTPATH_NONE;
3866
3867         return svm_exit_handlers_fastpath(vcpu);
3868 }
3869
3870 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
3871                              int root_level)
3872 {
3873         struct vcpu_svm *svm = to_svm(vcpu);
3874         unsigned long cr3;
3875
3876         if (npt_enabled) {
3877                 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
3878                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3879
3880                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3881                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3882                         return;
3883                 cr3 = vcpu->arch.cr3;
3884         } else if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) {
3885                 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
3886         } else {
3887                 /* PCID in the guest should be impossible with a 32-bit MMU. */
3888                 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
3889                 cr3 = root_hpa;
3890         }
3891
3892         svm->vmcb->save.cr3 = cr3;
3893         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3894 }
3895
3896 static int is_disabled(void)
3897 {
3898         u64 vm_cr;
3899
3900         rdmsrl(MSR_VM_CR, vm_cr);
3901         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3902                 return 1;
3903
3904         return 0;
3905 }
3906
3907 static void
3908 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3909 {
3910         /*
3911          * Patch in the VMMCALL instruction:
3912          */
3913         hypercall[0] = 0x0f;
3914         hypercall[1] = 0x01;
3915         hypercall[2] = 0xd9;
3916 }
3917
3918 static int __init svm_check_processor_compat(void)
3919 {
3920         return 0;
3921 }
3922
3923 static bool svm_cpu_has_accelerated_tpr(void)
3924 {
3925         return false;
3926 }
3927
3928 /*
3929  * The kvm parameter can be NULL (module initialization, or invocation before
3930  * VM creation). Be sure to check the kvm parameter before using it.
3931  */
3932 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3933 {
3934         switch (index) {
3935         case MSR_IA32_MCG_EXT_CTL:
3936         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3937                 return false;
3938         case MSR_IA32_SMBASE:
3939                 /* SEV-ES guests do not support SMM, so report false */
3940                 if (kvm && sev_es_guest(kvm))
3941                         return false;
3942                 break;
3943         default:
3944                 break;
3945         }
3946
3947         return true;
3948 }
3949
3950 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3951 {
3952         return 0;
3953 }
3954
3955 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3956 {
3957         struct vcpu_svm *svm = to_svm(vcpu);
3958         struct kvm_cpuid_entry2 *best;
3959
3960         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3961                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3962                                     boot_cpu_has(X86_FEATURE_XSAVES);
3963
3964         /* Update nrips enabled cache */
3965         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3966                              guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
3967
3968         svm_recalc_instruction_intercepts(vcpu, svm);
3969
3970         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
3971         if (sev_guest(vcpu->kvm)) {
3972                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3973                 if (best)
3974                         vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
3975         }
3976
3977         if (kvm_vcpu_apicv_active(vcpu)) {
3978                 /*
3979                  * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3980                  * is exposed to the guest, disable AVIC.
3981                  */
3982                 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3983                         kvm_request_apicv_update(vcpu->kvm, false,
3984                                                  APICV_INHIBIT_REASON_X2APIC);
3985
3986                 /*
3987                  * Currently, AVIC does not work with nested virtualization.
3988                  * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3989                  */
3990                 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3991                         kvm_request_apicv_update(vcpu->kvm, false,
3992                                                  APICV_INHIBIT_REASON_NESTED);
3993         }
3994
3995         if (guest_cpuid_is_intel(vcpu)) {
3996                 /*
3997                  * We must intercept SYSENTER_EIP and SYSENTER_ESP
3998                  * accesses because the processor only stores 32 bits.
3999                  * For the same reason we cannot use virtual VMLOAD/VMSAVE.
4000                  */
4001                 svm_set_intercept(svm, INTERCEPT_VMLOAD);
4002                 svm_set_intercept(svm, INTERCEPT_VMSAVE);
4003                 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4004
4005                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
4006                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
4007         } else {
4008                 /*
4009                  * If hardware supports Virtual VMLOAD VMSAVE then enable it
4010                  * in VMCB and clear intercepts to avoid #VMEXIT.
4011                  */
4012                 if (vls) {
4013                         svm_clr_intercept(svm, INTERCEPT_VMLOAD);
4014                         svm_clr_intercept(svm, INTERCEPT_VMSAVE);
4015                         svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
4016                 }
4017                 /* No need to intercept these MSRs */
4018                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
4019                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
4020         }
4021 }
4022
4023 static bool svm_has_wbinvd_exit(void)
4024 {
4025         return true;
4026 }
4027
4028 #define PRE_EX(exit)  { .exit_code = (exit), \
4029                         .stage = X86_ICPT_PRE_EXCEPT, }
4030 #define POST_EX(exit) { .exit_code = (exit), \
4031                         .stage = X86_ICPT_POST_EXCEPT, }
4032 #define POST_MEM(exit) { .exit_code = (exit), \
4033                         .stage = X86_ICPT_POST_MEMACCESS, }
4034
4035 static const struct __x86_intercept {
4036         u32 exit_code;
4037         enum x86_intercept_stage stage;
4038 } x86_intercept_map[] = {
4039         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
4040         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
4041         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
4042         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
4043         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
4044         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
4045         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
4046         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
4047         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
4048         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
4049         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
4050         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
4051         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
4052         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
4053         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
4054         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
4055         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
4056         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4057         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4058         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4059         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4060         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4061         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4062         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4063         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4064         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4065         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4066         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4067         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4068         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4069         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4070         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4071         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4072         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4073         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4074         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4075         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4076         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4077         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4078         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4079         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4080         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4081         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4082         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4083         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4084         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4085         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4086 };
4087
4088 #undef PRE_EX
4089 #undef POST_EX
4090 #undef POST_MEM
4091
4092 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4093                                struct x86_instruction_info *info,
4094                                enum x86_intercept_stage stage,
4095                                struct x86_exception *exception)
4096 {
4097         struct vcpu_svm *svm = to_svm(vcpu);
4098         int vmexit, ret = X86EMUL_CONTINUE;
4099         struct __x86_intercept icpt_info;
4100         struct vmcb *vmcb = svm->vmcb;
4101
4102         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4103                 goto out;
4104
4105         icpt_info = x86_intercept_map[info->intercept];
4106
4107         if (stage != icpt_info.stage)
4108                 goto out;
4109
4110         switch (icpt_info.exit_code) {
4111         case SVM_EXIT_READ_CR0:
4112                 if (info->intercept == x86_intercept_cr_read)
4113                         icpt_info.exit_code += info->modrm_reg;
4114                 break;
4115         case SVM_EXIT_WRITE_CR0: {
4116                 unsigned long cr0, val;
4117
4118                 if (info->intercept == x86_intercept_cr_write)
4119                         icpt_info.exit_code += info->modrm_reg;
4120
4121                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4122                     info->intercept == x86_intercept_clts)
4123                         break;
4124
4125                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4126                                         INTERCEPT_SELECTIVE_CR0)))
4127                         break;
4128
4129                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4130                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4131
4132                 if (info->intercept == x86_intercept_lmsw) {
4133                         cr0 &= 0xfUL;
4134                         val &= 0xfUL;
4135                         /* lmsw can't clear PE - catch this here */
4136                         if (cr0 & X86_CR0_PE)
4137                                 val |= X86_CR0_PE;
4138                 }
4139
4140                 if (cr0 ^ val)
4141                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4142
4143                 break;
4144         }
4145         case SVM_EXIT_READ_DR0:
4146         case SVM_EXIT_WRITE_DR0:
4147                 icpt_info.exit_code += info->modrm_reg;
4148                 break;
4149         case SVM_EXIT_MSR:
4150                 if (info->intercept == x86_intercept_wrmsr)
4151                         vmcb->control.exit_info_1 = 1;
4152                 else
4153                         vmcb->control.exit_info_1 = 0;
4154                 break;
4155         case SVM_EXIT_PAUSE:
4156                 /*
4157                  * We get this for NOP only, but pause
4158                  * is rep not, check this here
4159                  */
4160                 if (info->rep_prefix != REPE_PREFIX)
4161                         goto out;
4162                 break;
4163         case SVM_EXIT_IOIO: {
4164                 u64 exit_info;
4165                 u32 bytes;
4166
4167                 if (info->intercept == x86_intercept_in ||
4168                     info->intercept == x86_intercept_ins) {
4169                         exit_info = ((info->src_val & 0xffff) << 16) |
4170                                 SVM_IOIO_TYPE_MASK;
4171                         bytes = info->dst_bytes;
4172                 } else {
4173                         exit_info = (info->dst_val & 0xffff) << 16;
4174                         bytes = info->src_bytes;
4175                 }
4176
4177                 if (info->intercept == x86_intercept_outs ||
4178                     info->intercept == x86_intercept_ins)
4179                         exit_info |= SVM_IOIO_STR_MASK;
4180
4181                 if (info->rep_prefix)
4182                         exit_info |= SVM_IOIO_REP_MASK;
4183
4184                 bytes = min(bytes, 4u);
4185
4186                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4187
4188                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4189
4190                 vmcb->control.exit_info_1 = exit_info;
4191                 vmcb->control.exit_info_2 = info->next_rip;
4192
4193                 break;
4194         }
4195         default:
4196                 break;
4197         }
4198
4199         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4200         if (static_cpu_has(X86_FEATURE_NRIPS))
4201                 vmcb->control.next_rip  = info->next_rip;
4202         vmcb->control.exit_code = icpt_info.exit_code;
4203         vmexit = nested_svm_exit_handled(svm);
4204
4205         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4206                                            : X86EMUL_CONTINUE;
4207
4208 out:
4209         return ret;
4210 }
4211
4212 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4213 {
4214 }
4215
4216 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4217 {
4218         if (!kvm_pause_in_guest(vcpu->kvm))
4219                 shrink_ple_window(vcpu);
4220 }
4221
4222 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4223 {
4224         /* [63:9] are reserved. */
4225         vcpu->arch.mcg_cap &= 0x1ff;
4226 }
4227
4228 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4229 {
4230         struct vcpu_svm *svm = to_svm(vcpu);
4231
4232         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4233         if (!gif_set(svm))
4234                 return true;
4235
4236         return is_smm(vcpu);
4237 }
4238
4239 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4240 {
4241         struct vcpu_svm *svm = to_svm(vcpu);
4242         if (svm->nested.nested_run_pending)
4243                 return -EBUSY;
4244
4245         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4246         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4247                 return -EBUSY;
4248
4249         return !svm_smi_blocked(vcpu);
4250 }
4251
4252 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4253 {
4254         struct vcpu_svm *svm = to_svm(vcpu);
4255         int ret;
4256
4257         if (is_guest_mode(vcpu)) {
4258                 /* FED8h - SVM Guest */
4259                 put_smstate(u64, smstate, 0x7ed8, 1);
4260                 /* FEE0h - SVM Guest VMCB Physical Address */
4261                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4262
4263                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4264                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4265                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4266
4267                 ret = nested_svm_vmexit(svm);
4268                 if (ret)
4269                         return ret;
4270         }
4271         return 0;
4272 }
4273
4274 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4275 {
4276         struct vcpu_svm *svm = to_svm(vcpu);
4277         struct kvm_host_map map;
4278         int ret = 0;
4279
4280         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4281                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4282                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4283                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4284
4285                 if (guest) {
4286                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4287                                 return 1;
4288
4289                         if (!(saved_efer & EFER_SVME))
4290                                 return 1;
4291
4292                         if (kvm_vcpu_map(vcpu,
4293                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4294                                 return 1;
4295
4296                         if (svm_allocate_nested(svm))
4297                                 return 1;
4298
4299                         ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, map.hva);
4300                         kvm_vcpu_unmap(vcpu, &map, true);
4301                 }
4302         }
4303
4304         return ret;
4305 }
4306
4307 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4308 {
4309         struct vcpu_svm *svm = to_svm(vcpu);
4310
4311         if (!gif_set(svm)) {
4312                 if (vgif_enabled(svm))
4313                         svm_set_intercept(svm, INTERCEPT_STGI);
4314                 /* STGI will cause a vm exit */
4315         } else {
4316                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4317         }
4318 }
4319
4320 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4321 {
4322         bool smep, smap, is_user;
4323         unsigned long cr4;
4324
4325         /*
4326          * When the guest is an SEV-ES guest, emulation is not possible.
4327          */
4328         if (sev_es_guest(vcpu->kvm))
4329                 return false;
4330
4331         /*
4332          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4333          *
4334          * Errata:
4335          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4336          * possible that CPU microcode implementing DecodeAssist will fail
4337          * to read bytes of instruction which caused #NPF. In this case,
4338          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4339          * return 0 instead of the correct guest instruction bytes.
4340          *
4341          * This happens because CPU microcode reading instruction bytes
4342          * uses a special opcode which attempts to read data using CPL=0
4343          * privileges. The microcode reads CS:RIP and if it hits a SMAP
4344          * fault, it gives up and returns no instruction bytes.
4345          *
4346          * Detection:
4347          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4348          * returned 0 in GuestIntrBytes field of the VMCB.
4349          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4350          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4351          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4352          * a SMEP fault instead of #NPF).
4353          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4354          * As most guests enable SMAP if they have also enabled SMEP, use above
4355          * logic in order to attempt minimize false-positive of detecting errata
4356          * while still preserving all cases semantic correctness.
4357          *
4358          * Workaround:
4359          * To determine what instruction the guest was executing, the hypervisor
4360          * will have to decode the instruction at the instruction pointer.
4361          *
4362          * In non SEV guest, hypervisor will be able to read the guest
4363          * memory to decode the instruction pointer when insn_len is zero
4364          * so we return true to indicate that decoding is possible.
4365          *
4366          * But in the SEV guest, the guest memory is encrypted with the
4367          * guest specific key and hypervisor will not be able to decode the
4368          * instruction pointer so we will not able to workaround it. Lets
4369          * print the error and request to kill the guest.
4370          */
4371         if (likely(!insn || insn_len))
4372                 return true;
4373
4374         /*
4375          * If RIP is invalid, go ahead with emulation which will cause an
4376          * internal error exit.
4377          */
4378         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4379                 return true;
4380
4381         cr4 = kvm_read_cr4(vcpu);
4382         smep = cr4 & X86_CR4_SMEP;
4383         smap = cr4 & X86_CR4_SMAP;
4384         is_user = svm_get_cpl(vcpu) == 3;
4385         if (smap && (!smep || is_user)) {
4386                 if (!sev_guest(vcpu->kvm))
4387                         return true;
4388
4389                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4390                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4391         }
4392
4393         return false;
4394 }
4395
4396 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4397 {
4398         struct vcpu_svm *svm = to_svm(vcpu);
4399
4400         /*
4401          * TODO: Last condition latch INIT signals on vCPU when
4402          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4403          * To properly emulate the INIT intercept,
4404          * svm_check_nested_events() should call nested_svm_vmexit()
4405          * if an INIT signal is pending.
4406          */
4407         return !gif_set(svm) ||
4408                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4409 }
4410
4411 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4412 {
4413         if (!sev_es_guest(vcpu->kvm))
4414                 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4415
4416         sev_vcpu_deliver_sipi_vector(vcpu, vector);
4417 }
4418
4419 static void svm_vm_destroy(struct kvm *kvm)
4420 {
4421         avic_vm_destroy(kvm);
4422         sev_vm_destroy(kvm);
4423 }
4424
4425 static int svm_vm_init(struct kvm *kvm)
4426 {
4427         if (!pause_filter_count || !pause_filter_thresh)
4428                 kvm->arch.pause_in_guest = true;
4429
4430         if (avic) {
4431                 int ret = avic_vm_init(kvm);
4432                 if (ret)
4433                         return ret;
4434         }
4435
4436         kvm_apicv_init(kvm, avic);
4437         return 0;
4438 }
4439
4440 static struct kvm_x86_ops svm_x86_ops __initdata = {
4441         .hardware_unsetup = svm_hardware_teardown,
4442         .hardware_enable = svm_hardware_enable,
4443         .hardware_disable = svm_hardware_disable,
4444         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4445         .has_emulated_msr = svm_has_emulated_msr,
4446
4447         .vcpu_create = svm_create_vcpu,
4448         .vcpu_free = svm_free_vcpu,
4449         .vcpu_reset = svm_vcpu_reset,
4450
4451         .vm_size = sizeof(struct kvm_svm),
4452         .vm_init = svm_vm_init,
4453         .vm_destroy = svm_vm_destroy,
4454
4455         .prepare_guest_switch = svm_prepare_guest_switch,
4456         .vcpu_load = svm_vcpu_load,
4457         .vcpu_put = svm_vcpu_put,
4458         .vcpu_blocking = svm_vcpu_blocking,
4459         .vcpu_unblocking = svm_vcpu_unblocking,
4460
4461         .update_exception_bitmap = svm_update_exception_bitmap,
4462         .get_msr_feature = svm_get_msr_feature,
4463         .get_msr = svm_get_msr,
4464         .set_msr = svm_set_msr,
4465         .get_segment_base = svm_get_segment_base,
4466         .get_segment = svm_get_segment,
4467         .set_segment = svm_set_segment,
4468         .get_cpl = svm_get_cpl,
4469         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4470         .set_cr0 = svm_set_cr0,
4471         .is_valid_cr4 = svm_is_valid_cr4,
4472         .set_cr4 = svm_set_cr4,
4473         .set_efer = svm_set_efer,
4474         .get_idt = svm_get_idt,
4475         .set_idt = svm_set_idt,
4476         .get_gdt = svm_get_gdt,
4477         .set_gdt = svm_set_gdt,
4478         .set_dr7 = svm_set_dr7,
4479         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4480         .cache_reg = svm_cache_reg,
4481         .get_rflags = svm_get_rflags,
4482         .set_rflags = svm_set_rflags,
4483
4484         .tlb_flush_all = svm_flush_tlb,
4485         .tlb_flush_current = svm_flush_tlb,
4486         .tlb_flush_gva = svm_flush_tlb_gva,
4487         .tlb_flush_guest = svm_flush_tlb,
4488
4489         .run = svm_vcpu_run,
4490         .handle_exit = handle_exit,
4491         .skip_emulated_instruction = skip_emulated_instruction,
4492         .update_emulated_instruction = NULL,
4493         .set_interrupt_shadow = svm_set_interrupt_shadow,
4494         .get_interrupt_shadow = svm_get_interrupt_shadow,
4495         .patch_hypercall = svm_patch_hypercall,
4496         .set_irq = svm_set_irq,
4497         .set_nmi = svm_inject_nmi,
4498         .queue_exception = svm_queue_exception,
4499         .cancel_injection = svm_cancel_injection,
4500         .interrupt_allowed = svm_interrupt_allowed,
4501         .nmi_allowed = svm_nmi_allowed,
4502         .get_nmi_mask = svm_get_nmi_mask,
4503         .set_nmi_mask = svm_set_nmi_mask,
4504         .enable_nmi_window = svm_enable_nmi_window,
4505         .enable_irq_window = svm_enable_irq_window,
4506         .update_cr8_intercept = svm_update_cr8_intercept,
4507         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4508         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4509         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4510         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4511         .load_eoi_exitmap = svm_load_eoi_exitmap,
4512         .hwapic_irr_update = svm_hwapic_irr_update,
4513         .hwapic_isr_update = svm_hwapic_isr_update,
4514         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4515         .apicv_post_state_restore = avic_post_state_restore,
4516
4517         .set_tss_addr = svm_set_tss_addr,
4518         .set_identity_map_addr = svm_set_identity_map_addr,
4519         .get_mt_mask = svm_get_mt_mask,
4520
4521         .get_exit_info = svm_get_exit_info,
4522
4523         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4524
4525         .has_wbinvd_exit = svm_has_wbinvd_exit,
4526
4527         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4528
4529         .load_mmu_pgd = svm_load_mmu_pgd,
4530
4531         .check_intercept = svm_check_intercept,
4532         .handle_exit_irqoff = svm_handle_exit_irqoff,
4533
4534         .request_immediate_exit = __kvm_request_immediate_exit,
4535
4536         .sched_in = svm_sched_in,
4537
4538         .pmu_ops = &amd_pmu_ops,
4539         .nested_ops = &svm_nested_ops,
4540
4541         .deliver_posted_interrupt = svm_deliver_avic_intr,
4542         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4543         .update_pi_irte = svm_update_pi_irte,
4544         .setup_mce = svm_setup_mce,
4545
4546         .smi_allowed = svm_smi_allowed,
4547         .pre_enter_smm = svm_pre_enter_smm,
4548         .pre_leave_smm = svm_pre_leave_smm,
4549         .enable_smi_window = svm_enable_smi_window,
4550
4551         .mem_enc_op = svm_mem_enc_op,
4552         .mem_enc_reg_region = svm_register_enc_region,
4553         .mem_enc_unreg_region = svm_unregister_enc_region,
4554
4555         .vm_copy_enc_context_from = svm_vm_copy_asid_from,
4556
4557         .can_emulate_instruction = svm_can_emulate_instruction,
4558
4559         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4560
4561         .msr_filter_changed = svm_msr_filter_changed,
4562         .complete_emulated_msr = svm_complete_emulated_msr,
4563
4564         .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4565 };
4566
4567 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4568         .cpu_has_kvm_support = has_svm,
4569         .disabled_by_bios = is_disabled,
4570         .hardware_setup = svm_hardware_setup,
4571         .check_processor_compatibility = svm_check_processor_compat,
4572
4573         .runtime_ops = &svm_x86_ops,
4574 };
4575
4576 static int __init svm_init(void)
4577 {
4578         __unused_size_checks();
4579
4580         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4581                         __alignof__(struct vcpu_svm), THIS_MODULE);
4582 }
4583
4584 static void __exit svm_exit(void)
4585 {
4586         kvm_exit();
4587 }
4588
4589 module_init(svm_init)
4590 module_exit(svm_exit)