1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/frame.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
30 #include <asm/perf_event.h>
31 #include <asm/tlbflush.h>
33 #include <asm/debugreg.h>
34 #include <asm/kvm_para.h>
35 #include <asm/irq_remapping.h>
37 #include <asm/spec-ctrl.h>
38 #include <asm/cpu_device_id.h>
40 #include <asm/virtext.h>
45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
47 MODULE_AUTHOR("Qumranet");
48 MODULE_LICENSE("GPL");
51 static const struct x86_cpu_id svm_cpu_id[] = {
52 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
58 #define IOPM_ALLOC_ORDER 2
59 #define MSRPM_ALLOC_ORDER 1
61 #define SEG_TYPE_LDT 2
62 #define SEG_TYPE_BUSY_TSS16 3
64 #define SVM_FEATURE_LBRV (1 << 1)
65 #define SVM_FEATURE_SVML (1 << 2)
66 #define SVM_FEATURE_TSC_RATE (1 << 4)
67 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
68 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
69 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
70 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
74 #define TSC_RATIO_RSVD 0xffffff0000000000ULL
75 #define TSC_RATIO_MIN 0x0000000000000001ULL
76 #define TSC_RATIO_MAX 0x000000ffffffffffULL
78 static bool erratum_383_found __read_mostly;
80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
83 * Set osvw_len to higher value when updated Revision Guides
84 * are published and we know what the new status bits are
86 static uint64_t osvw_len = 4, osvw_status;
88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
89 #define TSC_RATIO_DEFAULT 0x0100000000ULL
91 static const struct svm_direct_access_msrs {
92 u32 index; /* Index of the MSR */
93 bool always; /* True if intercept is always on */
94 } direct_access_msrs[] = {
95 { .index = MSR_STAR, .always = true },
96 { .index = MSR_IA32_SYSENTER_CS, .always = true },
98 { .index = MSR_GS_BASE, .always = true },
99 { .index = MSR_FS_BASE, .always = true },
100 { .index = MSR_KERNEL_GS_BASE, .always = true },
101 { .index = MSR_LSTAR, .always = true },
102 { .index = MSR_CSTAR, .always = true },
103 { .index = MSR_SYSCALL_MASK, .always = true },
105 { .index = MSR_IA32_SPEC_CTRL, .always = false },
106 { .index = MSR_IA32_PRED_CMD, .always = false },
107 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
108 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
109 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
110 { .index = MSR_IA32_LASTINTTOIP, .always = false },
111 { .index = MSR_INVALID, .always = false },
114 /* enable NPT for AMD64 and X86 with PAE */
115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
116 bool npt_enabled = true;
122 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
123 * pause_filter_count: On processors that support Pause filtering(indicated
124 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
125 * count value. On VMRUN this value is loaded into an internal counter.
126 * Each time a pause instruction is executed, this counter is decremented
127 * until it reaches zero at which time a #VMEXIT is generated if pause
128 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
129 * Intercept Filtering for more details.
130 * This also indicate if ple logic enabled.
132 * pause_filter_thresh: In addition, some processor families support advanced
133 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
134 * the amount of time a guest is allowed to execute in a pause loop.
135 * In this mode, a 16-bit pause filter threshold field is added in the
136 * VMCB. The threshold value is a cycle count that is used to reset the
137 * pause counter. As with simple pause filtering, VMRUN loads the pause
138 * count value from VMCB into an internal counter. Then, on each pause
139 * instruction the hardware checks the elapsed number of cycles since
140 * the most recent pause instruction against the pause filter threshold.
141 * If the elapsed cycle count is greater than the pause filter threshold,
142 * then the internal pause count is reloaded from the VMCB and execution
143 * continues. If the elapsed cycle count is less than the pause filter
144 * threshold, then the internal pause count is decremented. If the count
145 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
146 * triggered. If advanced pause filtering is supported and pause filter
147 * threshold field is set to zero, the filter will operate in the simpler,
151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
152 module_param(pause_filter_thresh, ushort, 0444);
154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
155 module_param(pause_filter_count, ushort, 0444);
157 /* Default doubles per-vcpu window every exit. */
158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
159 module_param(pause_filter_count_grow, ushort, 0444);
161 /* Default resets per-vcpu window every exit to pause_filter_count. */
162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
163 module_param(pause_filter_count_shrink, ushort, 0444);
165 /* Default is to compute the maximum so we can never overflow. */
166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
167 module_param(pause_filter_count_max, ushort, 0444);
169 /* allow nested paging (virtualized MMU) for all guests */
170 static int npt = true;
171 module_param(npt, int, S_IRUGO);
173 /* allow nested virtualization in KVM/SVM */
174 static int nested = true;
175 module_param(nested, int, S_IRUGO);
177 /* enable/disable Next RIP Save */
178 static int nrips = true;
179 module_param(nrips, int, 0444);
181 /* enable/disable Virtual VMLOAD VMSAVE */
182 static int vls = true;
183 module_param(vls, int, 0444);
185 /* enable/disable Virtual GIF */
186 static int vgif = true;
187 module_param(vgif, int, 0444);
189 /* enable/disable SEV support */
190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
191 module_param(sev, int, 0444);
193 static bool __read_mostly dump_invalid_vmcb = 0;
194 module_param(dump_invalid_vmcb, bool, 0644);
196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
198 static void svm_complete_interrupts(struct vcpu_svm *svm);
200 static unsigned long iopm_base;
202 struct kvm_ldttss_desc {
205 unsigned base1:8, type:5, dpl:2, p:1;
206 unsigned limit1:4, zero0:3, g:1, base2:8;
209 } __attribute__((packed));
211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
216 #define MSRS_RANGE_SIZE 2048
217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
219 u32 svm_msrpm_offset(u32 msr)
224 for (i = 0; i < NUM_MSR_MAPS; i++) {
225 if (msr < msrpm_ranges[i] ||
226 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
229 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
230 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
232 /* Now we have the u8 offset - but need the u32 offset */
236 /* MSR not in any range */
240 #define MAX_INST_SIZE 15
242 static inline void clgi(void)
244 asm volatile (__ex("clgi"));
247 static inline void stgi(void)
249 asm volatile (__ex("stgi"));
252 static inline void invlpga(unsigned long addr, u32 asid)
254 asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
257 static int get_npt_level(struct kvm_vcpu *vcpu)
260 return PT64_ROOT_4LEVEL;
262 return PT32E_ROOT_LEVEL;
266 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
268 struct vcpu_svm *svm = to_svm(vcpu);
269 vcpu->arch.efer = efer;
272 /* Shadow paging assumes NX to be available. */
275 if (!(efer & EFER_LMA))
279 if (!(efer & EFER_SVME)) {
280 svm_leave_nested(svm);
281 svm_set_gif(svm, true);
284 svm->vmcb->save.efer = efer | EFER_SVME;
285 mark_dirty(svm->vmcb, VMCB_CR);
288 static int is_external_interrupt(u32 info)
290 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
291 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
294 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
296 struct vcpu_svm *svm = to_svm(vcpu);
299 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
300 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
304 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
306 struct vcpu_svm *svm = to_svm(vcpu);
309 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
311 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
315 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
317 struct vcpu_svm *svm = to_svm(vcpu);
319 if (nrips && svm->vmcb->control.next_rip != 0) {
320 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
321 svm->next_rip = svm->vmcb->control.next_rip;
324 if (!svm->next_rip) {
325 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
328 kvm_rip_write(vcpu, svm->next_rip);
330 svm_set_interrupt_shadow(vcpu, 0);
335 static void svm_queue_exception(struct kvm_vcpu *vcpu)
337 struct vcpu_svm *svm = to_svm(vcpu);
338 unsigned nr = vcpu->arch.exception.nr;
339 bool has_error_code = vcpu->arch.exception.has_error_code;
340 u32 error_code = vcpu->arch.exception.error_code;
342 kvm_deliver_exception_payload(&svm->vcpu);
344 if (nr == BP_VECTOR && !nrips) {
345 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
348 * For guest debugging where we have to reinject #BP if some
349 * INT3 is guest-owned:
350 * Emulate nRIP by moving RIP forward. Will fail if injection
351 * raises a fault that is not intercepted. Still better than
352 * failing in all cases.
354 (void)skip_emulated_instruction(&svm->vcpu);
355 rip = kvm_rip_read(&svm->vcpu);
356 svm->int3_rip = rip + svm->vmcb->save.cs.base;
357 svm->int3_injected = rip - old_rip;
360 svm->vmcb->control.event_inj = nr
362 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
363 | SVM_EVTINJ_TYPE_EXEPT;
364 svm->vmcb->control.event_inj_err = error_code;
367 static void svm_init_erratum_383(void)
373 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
376 /* Use _safe variants to not break nested virtualization */
377 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
383 low = lower_32_bits(val);
384 high = upper_32_bits(val);
386 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
388 erratum_383_found = true;
391 static void svm_init_osvw(struct kvm_vcpu *vcpu)
394 * Guests should see errata 400 and 415 as fixed (assuming that
395 * HLT and IO instructions are intercepted).
397 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
398 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
401 * By increasing VCPU's osvw.length to 3 we are telling the guest that
402 * all osvw.status bits inside that length, including bit 0 (which is
403 * reserved for erratum 298), are valid. However, if host processor's
404 * osvw_len is 0 then osvw_status[0] carries no information. We need to
405 * be conservative here and therefore we tell the guest that erratum 298
406 * is present (because we really don't know).
408 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
409 vcpu->arch.osvw.status |= 1;
412 static int has_svm(void)
416 if (!cpu_has_svm(&msg)) {
417 printk(KERN_INFO "has_svm: %s\n", msg);
424 static void svm_hardware_disable(void)
426 /* Make sure we clean up behind us */
427 if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
428 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
432 amd_pmu_disable_virt();
435 static int svm_hardware_enable(void)
438 struct svm_cpu_data *sd;
440 struct desc_struct *gdt;
441 int me = raw_smp_processor_id();
443 rdmsrl(MSR_EFER, efer);
444 if (efer & EFER_SVME)
448 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
451 sd = per_cpu(svm_data, me);
453 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
457 sd->asid_generation = 1;
458 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
459 sd->next_asid = sd->max_asid + 1;
460 sd->min_asid = max_sev_asid + 1;
462 gdt = get_current_gdt_rw();
463 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
465 wrmsrl(MSR_EFER, efer | EFER_SVME);
467 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
469 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
470 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
471 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
478 * Note that it is possible to have a system with mixed processor
479 * revisions and therefore different OSVW bits. If bits are not the same
480 * on different processors then choose the worst case (i.e. if erratum
481 * is present on one processor and not on another then assume that the
482 * erratum is present everywhere).
484 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
485 uint64_t len, status = 0;
488 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
490 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
494 osvw_status = osvw_len = 0;
498 osvw_status |= status;
499 osvw_status &= (1ULL << osvw_len) - 1;
502 osvw_status = osvw_len = 0;
504 svm_init_erratum_383();
506 amd_pmu_enable_virt();
511 static void svm_cpu_uninit(int cpu)
513 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
518 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
519 kfree(sd->sev_vmcbs);
520 __free_page(sd->save_area);
524 static int svm_cpu_init(int cpu)
526 struct svm_cpu_data *sd;
528 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
532 sd->save_area = alloc_page(GFP_KERNEL);
536 if (svm_sev_enabled()) {
537 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
544 per_cpu(svm_data, cpu) = sd;
549 __free_page(sd->save_area);
556 static bool valid_msr_intercept(u32 index)
560 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
561 if (direct_access_msrs[i].index == index)
567 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
574 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
577 offset = svm_msrpm_offset(msr);
578 bit_write = 2 * (msr & 0x0f) + 1;
581 BUG_ON(offset == MSR_INVALID);
583 return !!test_bit(bit_write, &tmp);
586 static void set_msr_interception(u32 *msrpm, unsigned msr,
589 u8 bit_read, bit_write;
594 * If this warning triggers extend the direct_access_msrs list at the
595 * beginning of the file
597 WARN_ON(!valid_msr_intercept(msr));
599 offset = svm_msrpm_offset(msr);
600 bit_read = 2 * (msr & 0x0f);
601 bit_write = 2 * (msr & 0x0f) + 1;
604 BUG_ON(offset == MSR_INVALID);
606 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
607 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
612 static void svm_vcpu_init_msrpm(u32 *msrpm)
616 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
618 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
619 if (!direct_access_msrs[i].always)
622 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
626 static void add_msr_offset(u32 offset)
630 for (i = 0; i < MSRPM_OFFSETS; ++i) {
632 /* Offset already in list? */
633 if (msrpm_offsets[i] == offset)
636 /* Slot used by another offset? */
637 if (msrpm_offsets[i] != MSR_INVALID)
640 /* Add offset to list */
641 msrpm_offsets[i] = offset;
647 * If this BUG triggers the msrpm_offsets table has an overflow. Just
648 * increase MSRPM_OFFSETS in this case.
653 static void init_msrpm_offsets(void)
657 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
659 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
662 offset = svm_msrpm_offset(direct_access_msrs[i].index);
663 BUG_ON(offset == MSR_INVALID);
665 add_msr_offset(offset);
669 static void svm_enable_lbrv(struct vcpu_svm *svm)
671 u32 *msrpm = svm->msrpm;
673 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
674 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
675 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
676 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
677 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
680 static void svm_disable_lbrv(struct vcpu_svm *svm)
682 u32 *msrpm = svm->msrpm;
684 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
685 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
686 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
687 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
688 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
691 void disable_nmi_singlestep(struct vcpu_svm *svm)
693 svm->nmi_singlestep = false;
695 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
696 /* Clear our flags if they were not set by the guest */
697 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
698 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
699 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
700 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
704 static void grow_ple_window(struct kvm_vcpu *vcpu)
706 struct vcpu_svm *svm = to_svm(vcpu);
707 struct vmcb_control_area *control = &svm->vmcb->control;
708 int old = control->pause_filter_count;
710 control->pause_filter_count = __grow_ple_window(old,
712 pause_filter_count_grow,
713 pause_filter_count_max);
715 if (control->pause_filter_count != old) {
716 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
717 trace_kvm_ple_window_update(vcpu->vcpu_id,
718 control->pause_filter_count, old);
722 static void shrink_ple_window(struct kvm_vcpu *vcpu)
724 struct vcpu_svm *svm = to_svm(vcpu);
725 struct vmcb_control_area *control = &svm->vmcb->control;
726 int old = control->pause_filter_count;
728 control->pause_filter_count =
729 __shrink_ple_window(old,
731 pause_filter_count_shrink,
733 if (control->pause_filter_count != old) {
734 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
735 trace_kvm_ple_window_update(vcpu->vcpu_id,
736 control->pause_filter_count, old);
741 * The default MMIO mask is a single bit (excluding the present bit),
742 * which could conflict with the memory encryption bit. Check for
743 * memory encryption support and override the default MMIO mask if
744 * memory encryption is enabled.
746 static __init void svm_adjust_mmio_mask(void)
748 unsigned int enc_bit, mask_bit;
751 /* If there is no memory encryption support, use existing mask */
752 if (cpuid_eax(0x80000000) < 0x8000001f)
755 /* If memory encryption is not enabled, use existing mask */
756 rdmsrl(MSR_K8_SYSCFG, msr);
757 if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
760 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
761 mask_bit = boot_cpu_data.x86_phys_bits;
763 /* Increment the mask bit if it is the same as the encryption bit */
764 if (enc_bit == mask_bit)
768 * If the mask bit location is below 52, then some bits above the
769 * physical addressing limit will always be reserved, so use the
770 * rsvd_bits() function to generate the mask. This mask, along with
771 * the present bit, will be used to generate a page fault with
774 * If the mask bit location is 52 (or above), then clear the mask.
776 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
778 kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
781 static void svm_hardware_teardown(void)
785 if (svm_sev_enabled())
786 sev_hardware_teardown();
788 for_each_possible_cpu(cpu)
791 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
795 static __init void svm_set_cpu_caps(void)
801 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
803 kvm_cpu_cap_set(X86_FEATURE_SVM);
806 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
809 kvm_cpu_cap_set(X86_FEATURE_NPT);
812 /* CPUID 0x80000008 */
813 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
814 boot_cpu_has(X86_FEATURE_AMD_SSBD))
815 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
818 static __init int svm_hardware_setup(void)
821 struct page *iopm_pages;
825 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
830 iopm_va = page_address(iopm_pages);
831 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
832 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
834 init_msrpm_offsets();
836 supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
838 if (boot_cpu_has(X86_FEATURE_NX))
839 kvm_enable_efer_bits(EFER_NX);
841 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
842 kvm_enable_efer_bits(EFER_FFXSR);
844 if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
845 kvm_has_tsc_control = true;
846 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
847 kvm_tsc_scaling_ratio_frac_bits = 32;
850 /* Check for pause filtering support */
851 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
852 pause_filter_count = 0;
853 pause_filter_thresh = 0;
854 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
855 pause_filter_thresh = 0;
859 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
860 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
864 if (boot_cpu_has(X86_FEATURE_SEV) &&
865 IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
866 r = sev_hardware_setup();
874 svm_adjust_mmio_mask();
876 for_each_possible_cpu(cpu) {
877 r = svm_cpu_init(cpu);
882 if (!boot_cpu_has(X86_FEATURE_NPT))
885 if (npt_enabled && !npt)
888 kvm_configure_mmu(npt_enabled, PG_LEVEL_1G);
889 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
892 if (!boot_cpu_has(X86_FEATURE_NRIPS))
898 !boot_cpu_has(X86_FEATURE_AVIC) ||
899 !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
902 pr_info("AVIC enabled\n");
904 amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
910 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
911 !IS_ENABLED(CONFIG_X86_64)) {
914 pr_info("Virtual VMLOAD VMSAVE supported\n");
919 if (!boot_cpu_has(X86_FEATURE_VGIF))
922 pr_info("Virtual GIF supported\n");
930 svm_hardware_teardown();
934 static void init_seg(struct vmcb_seg *seg)
937 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
938 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
943 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
946 seg->attrib = SVM_SELECTOR_P_MASK | type;
951 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
953 struct vcpu_svm *svm = to_svm(vcpu);
954 u64 g_tsc_offset = 0;
956 if (is_guest_mode(vcpu)) {
957 /* Write L1's TSC offset. */
958 g_tsc_offset = svm->vmcb->control.tsc_offset -
959 svm->nested.hsave->control.tsc_offset;
960 svm->nested.hsave->control.tsc_offset = offset;
963 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
964 svm->vmcb->control.tsc_offset - g_tsc_offset,
967 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
969 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
970 return svm->vmcb->control.tsc_offset;
973 static void init_vmcb(struct vcpu_svm *svm)
975 struct vmcb_control_area *control = &svm->vmcb->control;
976 struct vmcb_save_area *save = &svm->vmcb->save;
978 svm->vcpu.arch.hflags = 0;
980 set_cr_intercept(svm, INTERCEPT_CR0_READ);
981 set_cr_intercept(svm, INTERCEPT_CR3_READ);
982 set_cr_intercept(svm, INTERCEPT_CR4_READ);
983 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
984 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
985 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
986 if (!kvm_vcpu_apicv_active(&svm->vcpu))
987 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
989 set_dr_intercepts(svm);
991 set_exception_intercept(svm, PF_VECTOR);
992 set_exception_intercept(svm, UD_VECTOR);
993 set_exception_intercept(svm, MC_VECTOR);
994 set_exception_intercept(svm, AC_VECTOR);
995 set_exception_intercept(svm, DB_VECTOR);
997 * Guest access to VMware backdoor ports could legitimately
998 * trigger #GP because of TSS I/O permission bitmap.
999 * We intercept those #GP and allow access to them anyway
1002 if (enable_vmware_backdoor)
1003 set_exception_intercept(svm, GP_VECTOR);
1005 set_intercept(svm, INTERCEPT_INTR);
1006 set_intercept(svm, INTERCEPT_NMI);
1007 set_intercept(svm, INTERCEPT_SMI);
1008 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1009 set_intercept(svm, INTERCEPT_RDPMC);
1010 set_intercept(svm, INTERCEPT_CPUID);
1011 set_intercept(svm, INTERCEPT_INVD);
1012 set_intercept(svm, INTERCEPT_INVLPG);
1013 set_intercept(svm, INTERCEPT_INVLPGA);
1014 set_intercept(svm, INTERCEPT_IOIO_PROT);
1015 set_intercept(svm, INTERCEPT_MSR_PROT);
1016 set_intercept(svm, INTERCEPT_TASK_SWITCH);
1017 set_intercept(svm, INTERCEPT_SHUTDOWN);
1018 set_intercept(svm, INTERCEPT_VMRUN);
1019 set_intercept(svm, INTERCEPT_VMMCALL);
1020 set_intercept(svm, INTERCEPT_VMLOAD);
1021 set_intercept(svm, INTERCEPT_VMSAVE);
1022 set_intercept(svm, INTERCEPT_STGI);
1023 set_intercept(svm, INTERCEPT_CLGI);
1024 set_intercept(svm, INTERCEPT_SKINIT);
1025 set_intercept(svm, INTERCEPT_WBINVD);
1026 set_intercept(svm, INTERCEPT_XSETBV);
1027 set_intercept(svm, INTERCEPT_RDPRU);
1028 set_intercept(svm, INTERCEPT_RSM);
1030 if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1031 set_intercept(svm, INTERCEPT_MONITOR);
1032 set_intercept(svm, INTERCEPT_MWAIT);
1035 if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1036 set_intercept(svm, INTERCEPT_HLT);
1038 control->iopm_base_pa = __sme_set(iopm_base);
1039 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1040 control->int_ctl = V_INTR_MASKING_MASK;
1042 init_seg(&save->es);
1043 init_seg(&save->ss);
1044 init_seg(&save->ds);
1045 init_seg(&save->fs);
1046 init_seg(&save->gs);
1048 save->cs.selector = 0xf000;
1049 save->cs.base = 0xffff0000;
1050 /* Executable/Readable Code Segment */
1051 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1052 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1053 save->cs.limit = 0xffff;
1055 save->gdtr.limit = 0xffff;
1056 save->idtr.limit = 0xffff;
1058 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1059 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1061 svm_set_efer(&svm->vcpu, 0);
1062 save->dr6 = 0xffff0ff0;
1063 kvm_set_rflags(&svm->vcpu, 2);
1064 save->rip = 0x0000fff0;
1065 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1068 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1069 * It also updates the guest-visible cr0 value.
1071 svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1072 kvm_mmu_reset_context(&svm->vcpu);
1074 save->cr4 = X86_CR4_PAE;
1078 /* Setup VMCB for Nested Paging */
1079 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1080 clr_intercept(svm, INTERCEPT_INVLPG);
1081 clr_exception_intercept(svm, PF_VECTOR);
1082 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1083 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1084 save->g_pat = svm->vcpu.arch.pat;
1088 svm->asid_generation = 0;
1090 svm->nested.vmcb = 0;
1091 svm->vcpu.arch.hflags = 0;
1093 if (pause_filter_count) {
1094 control->pause_filter_count = pause_filter_count;
1095 if (pause_filter_thresh)
1096 control->pause_filter_thresh = pause_filter_thresh;
1097 set_intercept(svm, INTERCEPT_PAUSE);
1099 clr_intercept(svm, INTERCEPT_PAUSE);
1102 if (kvm_vcpu_apicv_active(&svm->vcpu))
1103 avic_init_vmcb(svm);
1106 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1107 * in VMCB and clear intercepts to avoid #VMEXIT.
1110 clr_intercept(svm, INTERCEPT_VMLOAD);
1111 clr_intercept(svm, INTERCEPT_VMSAVE);
1112 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1116 clr_intercept(svm, INTERCEPT_STGI);
1117 clr_intercept(svm, INTERCEPT_CLGI);
1118 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1121 if (sev_guest(svm->vcpu.kvm)) {
1122 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1123 clr_exception_intercept(svm, UD_VECTOR);
1126 mark_all_dirty(svm->vmcb);
1132 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1134 struct vcpu_svm *svm = to_svm(vcpu);
1139 svm->virt_spec_ctrl = 0;
1142 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1143 MSR_IA32_APICBASE_ENABLE;
1144 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1145 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1149 kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1150 kvm_rdx_write(vcpu, eax);
1152 if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1153 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1156 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1158 struct vcpu_svm *svm;
1160 struct page *msrpm_pages;
1161 struct page *hsave_page;
1162 struct page *nested_msrpm_pages;
1165 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1169 page = alloc_page(GFP_KERNEL_ACCOUNT);
1173 msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1177 nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1178 if (!nested_msrpm_pages)
1181 hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
1185 err = avic_init_vcpu(svm);
1189 /* We initialize this flag to true to make sure that the is_running
1190 * bit would be set the first time the vcpu is loaded.
1192 if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1193 svm->avic_is_running = true;
1195 svm->nested.hsave = page_address(hsave_page);
1196 clear_page(svm->nested.hsave);
1198 svm->msrpm = page_address(msrpm_pages);
1199 svm_vcpu_init_msrpm(svm->msrpm);
1201 svm->nested.msrpm = page_address(nested_msrpm_pages);
1202 svm_vcpu_init_msrpm(svm->nested.msrpm);
1204 svm->vmcb = page_address(page);
1205 clear_page(svm->vmcb);
1206 svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1207 svm->asid_generation = 0;
1210 svm_init_osvw(vcpu);
1211 vcpu->arch.microcode_version = 0x01000065;
1216 __free_page(hsave_page);
1218 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1220 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1227 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1231 for_each_online_cpu(i)
1232 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1235 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1237 struct vcpu_svm *svm = to_svm(vcpu);
1240 * The vmcb page can be recycled, causing a false negative in
1241 * svm_vcpu_load(). So, ensure that no logical CPU has this
1242 * vmcb page recorded as its current vmcb.
1244 svm_clear_current_vmcb(svm->vmcb);
1246 __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1247 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1248 __free_page(virt_to_page(svm->nested.hsave));
1249 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1252 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1254 struct vcpu_svm *svm = to_svm(vcpu);
1255 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1258 if (unlikely(cpu != vcpu->cpu)) {
1259 svm->asid_generation = 0;
1260 mark_all_dirty(svm->vmcb);
1263 #ifdef CONFIG_X86_64
1264 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1266 savesegment(fs, svm->host.fs);
1267 savesegment(gs, svm->host.gs);
1268 svm->host.ldt = kvm_read_ldt();
1270 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1271 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1273 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1274 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1275 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1276 __this_cpu_write(current_tsc_ratio, tsc_ratio);
1277 wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1280 /* This assumes that the kernel never uses MSR_TSC_AUX */
1281 if (static_cpu_has(X86_FEATURE_RDTSCP))
1282 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1284 if (sd->current_vmcb != svm->vmcb) {
1285 sd->current_vmcb = svm->vmcb;
1286 indirect_branch_prediction_barrier();
1288 avic_vcpu_load(vcpu, cpu);
1291 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1293 struct vcpu_svm *svm = to_svm(vcpu);
1296 avic_vcpu_put(vcpu);
1298 ++vcpu->stat.host_state_reload;
1299 kvm_load_ldt(svm->host.ldt);
1300 #ifdef CONFIG_X86_64
1301 loadsegment(fs, svm->host.fs);
1302 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1303 load_gs_index(svm->host.gs);
1305 #ifdef CONFIG_X86_32_LAZY_GS
1306 loadsegment(gs, svm->host.gs);
1309 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1310 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1313 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1315 struct vcpu_svm *svm = to_svm(vcpu);
1316 unsigned long rflags = svm->vmcb->save.rflags;
1318 if (svm->nmi_singlestep) {
1319 /* Hide our flags if they were not set by the guest */
1320 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1321 rflags &= ~X86_EFLAGS_TF;
1322 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1323 rflags &= ~X86_EFLAGS_RF;
1328 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1330 if (to_svm(vcpu)->nmi_singlestep)
1331 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1334 * Any change of EFLAGS.VM is accompanied by a reload of SS
1335 * (caused by either a task switch or an inter-privilege IRET),
1336 * so we do not need to update the CPL here.
1338 to_svm(vcpu)->vmcb->save.rflags = rflags;
1341 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1344 case VCPU_EXREG_PDPTR:
1345 BUG_ON(!npt_enabled);
1346 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1353 static void svm_set_vintr(struct vcpu_svm *svm)
1355 struct vmcb_control_area *control;
1357 /* The following fields are ignored when AVIC is enabled */
1358 WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1359 set_intercept(svm, INTERCEPT_VINTR);
1362 * This is just a dummy VINTR to actually cause a vmexit to happen.
1363 * Actual injection of virtual interrupts happens through EVENTINJ.
1365 control = &svm->vmcb->control;
1366 control->int_vector = 0x0;
1367 control->int_ctl &= ~V_INTR_PRIO_MASK;
1368 control->int_ctl |= V_IRQ_MASK |
1369 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1370 mark_dirty(svm->vmcb, VMCB_INTR);
1373 static void svm_clear_vintr(struct vcpu_svm *svm)
1375 const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1376 clr_intercept(svm, INTERCEPT_VINTR);
1378 /* Drop int_ctl fields related to VINTR injection. */
1379 svm->vmcb->control.int_ctl &= mask;
1380 if (is_guest_mode(&svm->vcpu)) {
1381 svm->nested.hsave->control.int_ctl &= mask;
1383 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1384 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1385 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1388 mark_dirty(svm->vmcb, VMCB_INTR);
1391 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1393 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1396 case VCPU_SREG_CS: return &save->cs;
1397 case VCPU_SREG_DS: return &save->ds;
1398 case VCPU_SREG_ES: return &save->es;
1399 case VCPU_SREG_FS: return &save->fs;
1400 case VCPU_SREG_GS: return &save->gs;
1401 case VCPU_SREG_SS: return &save->ss;
1402 case VCPU_SREG_TR: return &save->tr;
1403 case VCPU_SREG_LDTR: return &save->ldtr;
1409 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1411 struct vmcb_seg *s = svm_seg(vcpu, seg);
1416 static void svm_get_segment(struct kvm_vcpu *vcpu,
1417 struct kvm_segment *var, int seg)
1419 struct vmcb_seg *s = svm_seg(vcpu, seg);
1421 var->base = s->base;
1422 var->limit = s->limit;
1423 var->selector = s->selector;
1424 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1425 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1426 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1427 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1428 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1429 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1430 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1433 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1434 * However, the SVM spec states that the G bit is not observed by the
1435 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1436 * So let's synthesize a legal G bit for all segments, this helps
1437 * running KVM nested. It also helps cross-vendor migration, because
1438 * Intel's vmentry has a check on the 'G' bit.
1440 var->g = s->limit > 0xfffff;
1443 * AMD's VMCB does not have an explicit unusable field, so emulate it
1444 * for cross vendor migration purposes by "not present"
1446 var->unusable = !var->present;
1451 * Work around a bug where the busy flag in the tr selector
1461 * The accessed bit must always be set in the segment
1462 * descriptor cache, although it can be cleared in the
1463 * descriptor, the cached bit always remains at 1. Since
1464 * Intel has a check on this, set it here to support
1465 * cross-vendor migration.
1472 * On AMD CPUs sometimes the DB bit in the segment
1473 * descriptor is left as 1, although the whole segment has
1474 * been made unusable. Clear it here to pass an Intel VMX
1475 * entry check when cross vendor migrating.
1479 /* This is symmetric with svm_set_segment() */
1480 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1485 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1487 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1492 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1494 struct vcpu_svm *svm = to_svm(vcpu);
1496 dt->size = svm->vmcb->save.idtr.limit;
1497 dt->address = svm->vmcb->save.idtr.base;
1500 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1502 struct vcpu_svm *svm = to_svm(vcpu);
1504 svm->vmcb->save.idtr.limit = dt->size;
1505 svm->vmcb->save.idtr.base = dt->address ;
1506 mark_dirty(svm->vmcb, VMCB_DT);
1509 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1511 struct vcpu_svm *svm = to_svm(vcpu);
1513 dt->size = svm->vmcb->save.gdtr.limit;
1514 dt->address = svm->vmcb->save.gdtr.base;
1517 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1519 struct vcpu_svm *svm = to_svm(vcpu);
1521 svm->vmcb->save.gdtr.limit = dt->size;
1522 svm->vmcb->save.gdtr.base = dt->address ;
1523 mark_dirty(svm->vmcb, VMCB_DT);
1526 static void update_cr0_intercept(struct vcpu_svm *svm)
1528 ulong gcr0 = svm->vcpu.arch.cr0;
1529 u64 *hcr0 = &svm->vmcb->save.cr0;
1531 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1532 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1534 mark_dirty(svm->vmcb, VMCB_CR);
1536 if (gcr0 == *hcr0) {
1537 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1538 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1540 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1541 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1545 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1547 struct vcpu_svm *svm = to_svm(vcpu);
1549 #ifdef CONFIG_X86_64
1550 if (vcpu->arch.efer & EFER_LME) {
1551 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1552 vcpu->arch.efer |= EFER_LMA;
1553 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1556 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1557 vcpu->arch.efer &= ~EFER_LMA;
1558 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1562 vcpu->arch.cr0 = cr0;
1565 cr0 |= X86_CR0_PG | X86_CR0_WP;
1568 * re-enable caching here because the QEMU bios
1569 * does not do it - this results in some delay at
1572 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1573 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1574 svm->vmcb->save.cr0 = cr0;
1575 mark_dirty(svm->vmcb, VMCB_CR);
1576 update_cr0_intercept(svm);
1579 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1581 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1582 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1584 if (cr4 & X86_CR4_VMXE)
1587 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1588 svm_flush_tlb(vcpu);
1590 vcpu->arch.cr4 = cr4;
1593 cr4 |= host_cr4_mce;
1594 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1595 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1599 static void svm_set_segment(struct kvm_vcpu *vcpu,
1600 struct kvm_segment *var, int seg)
1602 struct vcpu_svm *svm = to_svm(vcpu);
1603 struct vmcb_seg *s = svm_seg(vcpu, seg);
1605 s->base = var->base;
1606 s->limit = var->limit;
1607 s->selector = var->selector;
1608 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1609 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1610 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1611 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1612 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1613 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1614 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1615 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1618 * This is always accurate, except if SYSRET returned to a segment
1619 * with SS.DPL != 3. Intel does not have this quirk, and always
1620 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1621 * would entail passing the CPL to userspace and back.
1623 if (seg == VCPU_SREG_SS)
1624 /* This is symmetric with svm_get_segment() */
1625 svm->vmcb->save.cpl = (var->dpl & 3);
1627 mark_dirty(svm->vmcb, VMCB_SEG);
1630 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1632 struct vcpu_svm *svm = to_svm(vcpu);
1634 clr_exception_intercept(svm, BP_VECTOR);
1636 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1637 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1638 set_exception_intercept(svm, BP_VECTOR);
1640 vcpu->guest_debug = 0;
1643 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1645 if (sd->next_asid > sd->max_asid) {
1646 ++sd->asid_generation;
1647 sd->next_asid = sd->min_asid;
1648 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1651 svm->asid_generation = sd->asid_generation;
1652 svm->vmcb->control.asid = sd->next_asid++;
1654 mark_dirty(svm->vmcb, VMCB_ASID);
1657 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1659 struct vmcb *vmcb = svm->vmcb;
1661 if (unlikely(value != vmcb->save.dr6)) {
1662 vmcb->save.dr6 = value;
1663 mark_dirty(vmcb, VMCB_DR);
1667 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1669 struct vcpu_svm *svm = to_svm(vcpu);
1671 get_debugreg(vcpu->arch.db[0], 0);
1672 get_debugreg(vcpu->arch.db[1], 1);
1673 get_debugreg(vcpu->arch.db[2], 2);
1674 get_debugreg(vcpu->arch.db[3], 3);
1676 * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1677 * because db_interception might need it. We can do it before vmentry.
1679 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1680 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1681 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1682 set_dr_intercepts(svm);
1685 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1687 struct vcpu_svm *svm = to_svm(vcpu);
1689 svm->vmcb->save.dr7 = value;
1690 mark_dirty(svm->vmcb, VMCB_DR);
1693 static int pf_interception(struct vcpu_svm *svm)
1695 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1696 u64 error_code = svm->vmcb->control.exit_info_1;
1698 return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1699 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1700 svm->vmcb->control.insn_bytes : NULL,
1701 svm->vmcb->control.insn_len);
1704 static int npf_interception(struct vcpu_svm *svm)
1706 u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1707 u64 error_code = svm->vmcb->control.exit_info_1;
1709 trace_kvm_page_fault(fault_address, error_code);
1710 return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1711 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1712 svm->vmcb->control.insn_bytes : NULL,
1713 svm->vmcb->control.insn_len);
1716 static int db_interception(struct vcpu_svm *svm)
1718 struct kvm_run *kvm_run = svm->vcpu.run;
1719 struct kvm_vcpu *vcpu = &svm->vcpu;
1721 if (!(svm->vcpu.guest_debug &
1722 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1723 !svm->nmi_singlestep) {
1724 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1725 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1729 if (svm->nmi_singlestep) {
1730 disable_nmi_singlestep(svm);
1731 /* Make sure we check for pending NMIs upon entry */
1732 kvm_make_request(KVM_REQ_EVENT, vcpu);
1735 if (svm->vcpu.guest_debug &
1736 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1737 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1738 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1739 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1740 kvm_run->debug.arch.pc =
1741 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1742 kvm_run->debug.arch.exception = DB_VECTOR;
1749 static int bp_interception(struct vcpu_svm *svm)
1751 struct kvm_run *kvm_run = svm->vcpu.run;
1753 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1754 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1755 kvm_run->debug.arch.exception = BP_VECTOR;
1759 static int ud_interception(struct vcpu_svm *svm)
1761 return handle_ud(&svm->vcpu);
1764 static int ac_interception(struct vcpu_svm *svm)
1766 kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1770 static int gp_interception(struct vcpu_svm *svm)
1772 struct kvm_vcpu *vcpu = &svm->vcpu;
1773 u32 error_code = svm->vmcb->control.exit_info_1;
1775 WARN_ON_ONCE(!enable_vmware_backdoor);
1778 * VMware backdoor emulation on #GP interception only handles IN{S},
1779 * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1782 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1785 return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1788 static bool is_erratum_383(void)
1793 if (!erratum_383_found)
1796 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1800 /* Bit 62 may or may not be set for this mce */
1801 value &= ~(1ULL << 62);
1803 if (value != 0xb600000000010015ULL)
1806 /* Clear MCi_STATUS registers */
1807 for (i = 0; i < 6; ++i)
1808 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1810 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1814 value &= ~(1ULL << 2);
1815 low = lower_32_bits(value);
1816 high = upper_32_bits(value);
1818 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1821 /* Flush tlb to evict multi-match entries */
1828 * Trigger machine check on the host. We assume all the MSRs are already set up
1829 * by the CPU and that we still run on the same CPU as the MCE occurred on.
1830 * We pass a fake environment to the machine check handler because we want
1831 * the guest to be always treated like user space, no matter what context
1832 * it used internally.
1834 static void kvm_machine_check(void)
1836 #if defined(CONFIG_X86_MCE)
1837 struct pt_regs regs = {
1838 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1839 .flags = X86_EFLAGS_IF,
1842 do_machine_check(®s, 0);
1846 static void svm_handle_mce(struct vcpu_svm *svm)
1848 if (is_erratum_383()) {
1850 * Erratum 383 triggered. Guest state is corrupt so kill the
1853 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1855 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1861 * On an #MC intercept the MCE handler is not called automatically in
1862 * the host. So do it by hand here.
1864 kvm_machine_check();
1867 static int mc_interception(struct vcpu_svm *svm)
1872 static int shutdown_interception(struct vcpu_svm *svm)
1874 struct kvm_run *kvm_run = svm->vcpu.run;
1877 * VMCB is undefined after a SHUTDOWN intercept
1878 * so reinitialize it.
1880 clear_page(svm->vmcb);
1883 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1887 static int io_interception(struct vcpu_svm *svm)
1889 struct kvm_vcpu *vcpu = &svm->vcpu;
1890 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1891 int size, in, string;
1894 ++svm->vcpu.stat.io_exits;
1895 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1896 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1898 return kvm_emulate_instruction(vcpu, 0);
1900 port = io_info >> 16;
1901 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1902 svm->next_rip = svm->vmcb->control.exit_info_2;
1904 return kvm_fast_pio(&svm->vcpu, size, port, in);
1907 static int nmi_interception(struct vcpu_svm *svm)
1912 static int intr_interception(struct vcpu_svm *svm)
1914 ++svm->vcpu.stat.irq_exits;
1918 static int nop_on_interception(struct vcpu_svm *svm)
1923 static int halt_interception(struct vcpu_svm *svm)
1925 return kvm_emulate_halt(&svm->vcpu);
1928 static int vmmcall_interception(struct vcpu_svm *svm)
1930 return kvm_emulate_hypercall(&svm->vcpu);
1933 static int vmload_interception(struct vcpu_svm *svm)
1935 struct vmcb *nested_vmcb;
1936 struct kvm_host_map map;
1939 if (nested_svm_check_permissions(svm))
1942 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1945 kvm_inject_gp(&svm->vcpu, 0);
1949 nested_vmcb = map.hva;
1951 ret = kvm_skip_emulated_instruction(&svm->vcpu);
1953 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1954 kvm_vcpu_unmap(&svm->vcpu, &map, true);
1959 static int vmsave_interception(struct vcpu_svm *svm)
1961 struct vmcb *nested_vmcb;
1962 struct kvm_host_map map;
1965 if (nested_svm_check_permissions(svm))
1968 ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1971 kvm_inject_gp(&svm->vcpu, 0);
1975 nested_vmcb = map.hva;
1977 ret = kvm_skip_emulated_instruction(&svm->vcpu);
1979 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1980 kvm_vcpu_unmap(&svm->vcpu, &map, true);
1985 static int vmrun_interception(struct vcpu_svm *svm)
1987 if (nested_svm_check_permissions(svm))
1990 return nested_svm_vmrun(svm);
1993 void svm_set_gif(struct vcpu_svm *svm, bool value)
1997 * If VGIF is enabled, the STGI intercept is only added to
1998 * detect the opening of the SMI/NMI window; remove it now.
1999 * Likewise, clear the VINTR intercept, we will set it
2000 * again while processing KVM_REQ_EVENT if needed.
2002 if (vgif_enabled(svm))
2003 clr_intercept(svm, INTERCEPT_STGI);
2004 if (is_intercept(svm, INTERCEPT_VINTR))
2005 svm_clear_vintr(svm);
2008 if (svm->vcpu.arch.smi_pending ||
2009 svm->vcpu.arch.nmi_pending ||
2010 kvm_cpu_has_injectable_intr(&svm->vcpu))
2011 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2016 * After a CLGI no interrupts should come. But if vGIF is
2017 * in use, we still rely on the VINTR intercept (rather than
2018 * STGI) to detect an open interrupt window.
2020 if (!vgif_enabled(svm))
2021 svm_clear_vintr(svm);
2025 static int stgi_interception(struct vcpu_svm *svm)
2029 if (nested_svm_check_permissions(svm))
2032 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2033 svm_set_gif(svm, true);
2037 static int clgi_interception(struct vcpu_svm *svm)
2041 if (nested_svm_check_permissions(svm))
2044 ret = kvm_skip_emulated_instruction(&svm->vcpu);
2045 svm_set_gif(svm, false);
2049 static int invlpga_interception(struct vcpu_svm *svm)
2051 struct kvm_vcpu *vcpu = &svm->vcpu;
2053 trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2054 kvm_rax_read(&svm->vcpu));
2056 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2057 kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2059 return kvm_skip_emulated_instruction(&svm->vcpu);
2062 static int skinit_interception(struct vcpu_svm *svm)
2064 trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2066 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2070 static int wbinvd_interception(struct vcpu_svm *svm)
2072 return kvm_emulate_wbinvd(&svm->vcpu);
2075 static int xsetbv_interception(struct vcpu_svm *svm)
2077 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2078 u32 index = kvm_rcx_read(&svm->vcpu);
2080 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2081 return kvm_skip_emulated_instruction(&svm->vcpu);
2087 static int rdpru_interception(struct vcpu_svm *svm)
2089 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2093 static int task_switch_interception(struct vcpu_svm *svm)
2097 int int_type = svm->vmcb->control.exit_int_info &
2098 SVM_EXITINTINFO_TYPE_MASK;
2099 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2101 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2103 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2104 bool has_error_code = false;
2107 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2109 if (svm->vmcb->control.exit_info_2 &
2110 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2111 reason = TASK_SWITCH_IRET;
2112 else if (svm->vmcb->control.exit_info_2 &
2113 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2114 reason = TASK_SWITCH_JMP;
2116 reason = TASK_SWITCH_GATE;
2118 reason = TASK_SWITCH_CALL;
2120 if (reason == TASK_SWITCH_GATE) {
2122 case SVM_EXITINTINFO_TYPE_NMI:
2123 svm->vcpu.arch.nmi_injected = false;
2125 case SVM_EXITINTINFO_TYPE_EXEPT:
2126 if (svm->vmcb->control.exit_info_2 &
2127 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2128 has_error_code = true;
2130 (u32)svm->vmcb->control.exit_info_2;
2132 kvm_clear_exception_queue(&svm->vcpu);
2134 case SVM_EXITINTINFO_TYPE_INTR:
2135 kvm_clear_interrupt_queue(&svm->vcpu);
2142 if (reason != TASK_SWITCH_GATE ||
2143 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2144 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2145 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2146 if (!skip_emulated_instruction(&svm->vcpu))
2150 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2153 return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2154 has_error_code, error_code);
2157 static int cpuid_interception(struct vcpu_svm *svm)
2159 return kvm_emulate_cpuid(&svm->vcpu);
2162 static int iret_interception(struct vcpu_svm *svm)
2164 ++svm->vcpu.stat.nmi_window_exits;
2165 clr_intercept(svm, INTERCEPT_IRET);
2166 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2167 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2168 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2172 static int invlpg_interception(struct vcpu_svm *svm)
2174 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2175 return kvm_emulate_instruction(&svm->vcpu, 0);
2177 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2178 return kvm_skip_emulated_instruction(&svm->vcpu);
2181 static int emulate_on_interception(struct vcpu_svm *svm)
2183 return kvm_emulate_instruction(&svm->vcpu, 0);
2186 static int rsm_interception(struct vcpu_svm *svm)
2188 return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2191 static int rdpmc_interception(struct vcpu_svm *svm)
2196 return emulate_on_interception(svm);
2198 err = kvm_rdpmc(&svm->vcpu);
2199 return kvm_complete_insn_gp(&svm->vcpu, err);
2202 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2205 unsigned long cr0 = svm->vcpu.arch.cr0;
2209 intercept = svm->nested.ctl.intercept;
2211 if (!is_guest_mode(&svm->vcpu) ||
2212 (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2215 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2216 val &= ~SVM_CR0_SELECTIVE_MASK;
2219 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2220 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2226 #define CR_VALID (1ULL << 63)
2228 static int cr_interception(struct vcpu_svm *svm)
2234 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2235 return emulate_on_interception(svm);
2237 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2238 return emulate_on_interception(svm);
2240 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2241 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2242 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2244 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2247 if (cr >= 16) { /* mov to cr */
2249 val = kvm_register_read(&svm->vcpu, reg);
2252 if (!check_selective_cr0_intercepted(svm, val))
2253 err = kvm_set_cr0(&svm->vcpu, val);
2259 err = kvm_set_cr3(&svm->vcpu, val);
2262 err = kvm_set_cr4(&svm->vcpu, val);
2265 err = kvm_set_cr8(&svm->vcpu, val);
2268 WARN(1, "unhandled write to CR%d", cr);
2269 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2272 } else { /* mov from cr */
2275 val = kvm_read_cr0(&svm->vcpu);
2278 val = svm->vcpu.arch.cr2;
2281 val = kvm_read_cr3(&svm->vcpu);
2284 val = kvm_read_cr4(&svm->vcpu);
2287 val = kvm_get_cr8(&svm->vcpu);
2290 WARN(1, "unhandled read from CR%d", cr);
2291 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2294 kvm_register_write(&svm->vcpu, reg, val);
2296 return kvm_complete_insn_gp(&svm->vcpu, err);
2299 static int dr_interception(struct vcpu_svm *svm)
2304 if (svm->vcpu.guest_debug == 0) {
2306 * No more DR vmexits; force a reload of the debug registers
2307 * and reenter on this instruction. The next vmexit will
2308 * retrieve the full state of the debug registers.
2310 clr_dr_intercepts(svm);
2311 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2315 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2316 return emulate_on_interception(svm);
2318 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2319 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2321 if (dr >= 16) { /* mov to DRn */
2322 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2324 val = kvm_register_read(&svm->vcpu, reg);
2325 kvm_set_dr(&svm->vcpu, dr - 16, val);
2327 if (!kvm_require_dr(&svm->vcpu, dr))
2329 kvm_get_dr(&svm->vcpu, dr, &val);
2330 kvm_register_write(&svm->vcpu, reg, val);
2333 return kvm_skip_emulated_instruction(&svm->vcpu);
2336 static int cr8_write_interception(struct vcpu_svm *svm)
2338 struct kvm_run *kvm_run = svm->vcpu.run;
2341 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2342 /* instruction emulation calls kvm_set_cr8() */
2343 r = cr_interception(svm);
2344 if (lapic_in_kernel(&svm->vcpu))
2346 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2348 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2352 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2356 switch (msr->index) {
2357 case MSR_F10H_DECFG:
2358 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2359 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2368 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2370 struct vcpu_svm *svm = to_svm(vcpu);
2372 switch (msr_info->index) {
2374 msr_info->data = svm->vmcb->save.star;
2376 #ifdef CONFIG_X86_64
2378 msr_info->data = svm->vmcb->save.lstar;
2381 msr_info->data = svm->vmcb->save.cstar;
2383 case MSR_KERNEL_GS_BASE:
2384 msr_info->data = svm->vmcb->save.kernel_gs_base;
2386 case MSR_SYSCALL_MASK:
2387 msr_info->data = svm->vmcb->save.sfmask;
2390 case MSR_IA32_SYSENTER_CS:
2391 msr_info->data = svm->vmcb->save.sysenter_cs;
2393 case MSR_IA32_SYSENTER_EIP:
2394 msr_info->data = svm->sysenter_eip;
2396 case MSR_IA32_SYSENTER_ESP:
2397 msr_info->data = svm->sysenter_esp;
2400 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2402 msr_info->data = svm->tsc_aux;
2405 * Nobody will change the following 5 values in the VMCB so we can
2406 * safely return them on rdmsr. They will always be 0 until LBRV is
2409 case MSR_IA32_DEBUGCTLMSR:
2410 msr_info->data = svm->vmcb->save.dbgctl;
2412 case MSR_IA32_LASTBRANCHFROMIP:
2413 msr_info->data = svm->vmcb->save.br_from;
2415 case MSR_IA32_LASTBRANCHTOIP:
2416 msr_info->data = svm->vmcb->save.br_to;
2418 case MSR_IA32_LASTINTFROMIP:
2419 msr_info->data = svm->vmcb->save.last_excp_from;
2421 case MSR_IA32_LASTINTTOIP:
2422 msr_info->data = svm->vmcb->save.last_excp_to;
2424 case MSR_VM_HSAVE_PA:
2425 msr_info->data = svm->nested.hsave_msr;
2428 msr_info->data = svm->nested.vm_cr_msr;
2430 case MSR_IA32_SPEC_CTRL:
2431 if (!msr_info->host_initiated &&
2432 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2433 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2434 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2435 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2438 msr_info->data = svm->spec_ctrl;
2440 case MSR_AMD64_VIRT_SPEC_CTRL:
2441 if (!msr_info->host_initiated &&
2442 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2445 msr_info->data = svm->virt_spec_ctrl;
2447 case MSR_F15H_IC_CFG: {
2451 family = guest_cpuid_family(vcpu);
2452 model = guest_cpuid_model(vcpu);
2454 if (family < 0 || model < 0)
2455 return kvm_get_msr_common(vcpu, msr_info);
2459 if (family == 0x15 &&
2460 (model >= 0x2 && model < 0x20))
2461 msr_info->data = 0x1E;
2464 case MSR_F10H_DECFG:
2465 msr_info->data = svm->msr_decfg;
2468 return kvm_get_msr_common(vcpu, msr_info);
2473 static int rdmsr_interception(struct vcpu_svm *svm)
2475 return kvm_emulate_rdmsr(&svm->vcpu);
2478 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2480 struct vcpu_svm *svm = to_svm(vcpu);
2481 int svm_dis, chg_mask;
2483 if (data & ~SVM_VM_CR_VALID_MASK)
2486 chg_mask = SVM_VM_CR_VALID_MASK;
2488 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2489 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2491 svm->nested.vm_cr_msr &= ~chg_mask;
2492 svm->nested.vm_cr_msr |= (data & chg_mask);
2494 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2496 /* check for svm_disable while efer.svme is set */
2497 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2503 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2505 struct vcpu_svm *svm = to_svm(vcpu);
2507 u32 ecx = msr->index;
2508 u64 data = msr->data;
2510 case MSR_IA32_CR_PAT:
2511 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2513 vcpu->arch.pat = data;
2514 svm->vmcb->save.g_pat = data;
2515 mark_dirty(svm->vmcb, VMCB_NPT);
2517 case MSR_IA32_SPEC_CTRL:
2518 if (!msr->host_initiated &&
2519 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2520 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2521 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2522 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2525 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2528 svm->spec_ctrl = data;
2534 * When it's written (to non-zero) for the first time, pass
2538 * The handling of the MSR bitmap for L2 guests is done in
2539 * nested_svm_vmrun_msrpm.
2540 * We update the L1 MSR bit as well since it will end up
2541 * touching the MSR anyway now.
2543 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2545 case MSR_IA32_PRED_CMD:
2546 if (!msr->host_initiated &&
2547 !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2550 if (data & ~PRED_CMD_IBPB)
2552 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2557 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2558 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2560 case MSR_AMD64_VIRT_SPEC_CTRL:
2561 if (!msr->host_initiated &&
2562 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2565 if (data & ~SPEC_CTRL_SSBD)
2568 svm->virt_spec_ctrl = data;
2571 svm->vmcb->save.star = data;
2573 #ifdef CONFIG_X86_64
2575 svm->vmcb->save.lstar = data;
2578 svm->vmcb->save.cstar = data;
2580 case MSR_KERNEL_GS_BASE:
2581 svm->vmcb->save.kernel_gs_base = data;
2583 case MSR_SYSCALL_MASK:
2584 svm->vmcb->save.sfmask = data;
2587 case MSR_IA32_SYSENTER_CS:
2588 svm->vmcb->save.sysenter_cs = data;
2590 case MSR_IA32_SYSENTER_EIP:
2591 svm->sysenter_eip = data;
2592 svm->vmcb->save.sysenter_eip = data;
2594 case MSR_IA32_SYSENTER_ESP:
2595 svm->sysenter_esp = data;
2596 svm->vmcb->save.sysenter_esp = data;
2599 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2603 * This is rare, so we update the MSR here instead of using
2604 * direct_access_msrs. Doing that would require a rdmsr in
2607 svm->tsc_aux = data;
2608 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2610 case MSR_IA32_DEBUGCTLMSR:
2611 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2612 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2616 if (data & DEBUGCTL_RESERVED_BITS)
2619 svm->vmcb->save.dbgctl = data;
2620 mark_dirty(svm->vmcb, VMCB_LBR);
2621 if (data & (1ULL<<0))
2622 svm_enable_lbrv(svm);
2624 svm_disable_lbrv(svm);
2626 case MSR_VM_HSAVE_PA:
2627 svm->nested.hsave_msr = data;
2630 return svm_set_vm_cr(vcpu, data);
2632 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2634 case MSR_F10H_DECFG: {
2635 struct kvm_msr_entry msr_entry;
2637 msr_entry.index = msr->index;
2638 if (svm_get_msr_feature(&msr_entry))
2641 /* Check the supported bits */
2642 if (data & ~msr_entry.data)
2645 /* Don't allow the guest to change a bit, #GP */
2646 if (!msr->host_initiated && (data ^ msr_entry.data))
2649 svm->msr_decfg = data;
2652 case MSR_IA32_APICBASE:
2653 if (kvm_vcpu_apicv_active(vcpu))
2654 avic_update_vapic_bar(to_svm(vcpu), data);
2657 return kvm_set_msr_common(vcpu, msr);
2662 static int wrmsr_interception(struct vcpu_svm *svm)
2664 return kvm_emulate_wrmsr(&svm->vcpu);
2667 static int msr_interception(struct vcpu_svm *svm)
2669 if (svm->vmcb->control.exit_info_1)
2670 return wrmsr_interception(svm);
2672 return rdmsr_interception(svm);
2675 static int interrupt_window_interception(struct vcpu_svm *svm)
2677 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2678 svm_clear_vintr(svm);
2681 * For AVIC, the only reason to end up here is ExtINTs.
2682 * In this case AVIC was temporarily disabled for
2683 * requesting the IRQ window and we have to re-enable it.
2685 svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2687 ++svm->vcpu.stat.irq_window_exits;
2691 static int pause_interception(struct vcpu_svm *svm)
2693 struct kvm_vcpu *vcpu = &svm->vcpu;
2694 bool in_kernel = (svm_get_cpl(vcpu) == 0);
2696 if (pause_filter_thresh)
2697 grow_ple_window(vcpu);
2699 kvm_vcpu_on_spin(vcpu, in_kernel);
2703 static int nop_interception(struct vcpu_svm *svm)
2705 return kvm_skip_emulated_instruction(&(svm->vcpu));
2708 static int monitor_interception(struct vcpu_svm *svm)
2710 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2711 return nop_interception(svm);
2714 static int mwait_interception(struct vcpu_svm *svm)
2716 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2717 return nop_interception(svm);
2720 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2721 [SVM_EXIT_READ_CR0] = cr_interception,
2722 [SVM_EXIT_READ_CR3] = cr_interception,
2723 [SVM_EXIT_READ_CR4] = cr_interception,
2724 [SVM_EXIT_READ_CR8] = cr_interception,
2725 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
2726 [SVM_EXIT_WRITE_CR0] = cr_interception,
2727 [SVM_EXIT_WRITE_CR3] = cr_interception,
2728 [SVM_EXIT_WRITE_CR4] = cr_interception,
2729 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
2730 [SVM_EXIT_READ_DR0] = dr_interception,
2731 [SVM_EXIT_READ_DR1] = dr_interception,
2732 [SVM_EXIT_READ_DR2] = dr_interception,
2733 [SVM_EXIT_READ_DR3] = dr_interception,
2734 [SVM_EXIT_READ_DR4] = dr_interception,
2735 [SVM_EXIT_READ_DR5] = dr_interception,
2736 [SVM_EXIT_READ_DR6] = dr_interception,
2737 [SVM_EXIT_READ_DR7] = dr_interception,
2738 [SVM_EXIT_WRITE_DR0] = dr_interception,
2739 [SVM_EXIT_WRITE_DR1] = dr_interception,
2740 [SVM_EXIT_WRITE_DR2] = dr_interception,
2741 [SVM_EXIT_WRITE_DR3] = dr_interception,
2742 [SVM_EXIT_WRITE_DR4] = dr_interception,
2743 [SVM_EXIT_WRITE_DR5] = dr_interception,
2744 [SVM_EXIT_WRITE_DR6] = dr_interception,
2745 [SVM_EXIT_WRITE_DR7] = dr_interception,
2746 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
2747 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
2748 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
2749 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
2750 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
2751 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
2752 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
2753 [SVM_EXIT_INTR] = intr_interception,
2754 [SVM_EXIT_NMI] = nmi_interception,
2755 [SVM_EXIT_SMI] = nop_on_interception,
2756 [SVM_EXIT_INIT] = nop_on_interception,
2757 [SVM_EXIT_VINTR] = interrupt_window_interception,
2758 [SVM_EXIT_RDPMC] = rdpmc_interception,
2759 [SVM_EXIT_CPUID] = cpuid_interception,
2760 [SVM_EXIT_IRET] = iret_interception,
2761 [SVM_EXIT_INVD] = emulate_on_interception,
2762 [SVM_EXIT_PAUSE] = pause_interception,
2763 [SVM_EXIT_HLT] = halt_interception,
2764 [SVM_EXIT_INVLPG] = invlpg_interception,
2765 [SVM_EXIT_INVLPGA] = invlpga_interception,
2766 [SVM_EXIT_IOIO] = io_interception,
2767 [SVM_EXIT_MSR] = msr_interception,
2768 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
2769 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
2770 [SVM_EXIT_VMRUN] = vmrun_interception,
2771 [SVM_EXIT_VMMCALL] = vmmcall_interception,
2772 [SVM_EXIT_VMLOAD] = vmload_interception,
2773 [SVM_EXIT_VMSAVE] = vmsave_interception,
2774 [SVM_EXIT_STGI] = stgi_interception,
2775 [SVM_EXIT_CLGI] = clgi_interception,
2776 [SVM_EXIT_SKINIT] = skinit_interception,
2777 [SVM_EXIT_WBINVD] = wbinvd_interception,
2778 [SVM_EXIT_MONITOR] = monitor_interception,
2779 [SVM_EXIT_MWAIT] = mwait_interception,
2780 [SVM_EXIT_XSETBV] = xsetbv_interception,
2781 [SVM_EXIT_RDPRU] = rdpru_interception,
2782 [SVM_EXIT_NPF] = npf_interception,
2783 [SVM_EXIT_RSM] = rsm_interception,
2784 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
2785 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
2788 static void dump_vmcb(struct kvm_vcpu *vcpu)
2790 struct vcpu_svm *svm = to_svm(vcpu);
2791 struct vmcb_control_area *control = &svm->vmcb->control;
2792 struct vmcb_save_area *save = &svm->vmcb->save;
2794 if (!dump_invalid_vmcb) {
2795 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2799 pr_err("VMCB Control Area:\n");
2800 pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2801 pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2802 pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2803 pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2804 pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2805 pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2806 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2807 pr_err("%-20s%d\n", "pause filter threshold:",
2808 control->pause_filter_thresh);
2809 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2810 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2811 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2812 pr_err("%-20s%d\n", "asid:", control->asid);
2813 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2814 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2815 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2816 pr_err("%-20s%08x\n", "int_state:", control->int_state);
2817 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2818 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2819 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2820 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2821 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2822 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2823 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2824 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2825 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2826 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2827 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2828 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2829 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2830 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2831 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2832 pr_err("VMCB State Save Area:\n");
2833 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2835 save->es.selector, save->es.attrib,
2836 save->es.limit, save->es.base);
2837 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2839 save->cs.selector, save->cs.attrib,
2840 save->cs.limit, save->cs.base);
2841 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2843 save->ss.selector, save->ss.attrib,
2844 save->ss.limit, save->ss.base);
2845 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2847 save->ds.selector, save->ds.attrib,
2848 save->ds.limit, save->ds.base);
2849 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2851 save->fs.selector, save->fs.attrib,
2852 save->fs.limit, save->fs.base);
2853 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2855 save->gs.selector, save->gs.attrib,
2856 save->gs.limit, save->gs.base);
2857 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2859 save->gdtr.selector, save->gdtr.attrib,
2860 save->gdtr.limit, save->gdtr.base);
2861 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2863 save->ldtr.selector, save->ldtr.attrib,
2864 save->ldtr.limit, save->ldtr.base);
2865 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2867 save->idtr.selector, save->idtr.attrib,
2868 save->idtr.limit, save->idtr.base);
2869 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2871 save->tr.selector, save->tr.attrib,
2872 save->tr.limit, save->tr.base);
2873 pr_err("cpl: %d efer: %016llx\n",
2874 save->cpl, save->efer);
2875 pr_err("%-15s %016llx %-13s %016llx\n",
2876 "cr0:", save->cr0, "cr2:", save->cr2);
2877 pr_err("%-15s %016llx %-13s %016llx\n",
2878 "cr3:", save->cr3, "cr4:", save->cr4);
2879 pr_err("%-15s %016llx %-13s %016llx\n",
2880 "dr6:", save->dr6, "dr7:", save->dr7);
2881 pr_err("%-15s %016llx %-13s %016llx\n",
2882 "rip:", save->rip, "rflags:", save->rflags);
2883 pr_err("%-15s %016llx %-13s %016llx\n",
2884 "rsp:", save->rsp, "rax:", save->rax);
2885 pr_err("%-15s %016llx %-13s %016llx\n",
2886 "star:", save->star, "lstar:", save->lstar);
2887 pr_err("%-15s %016llx %-13s %016llx\n",
2888 "cstar:", save->cstar, "sfmask:", save->sfmask);
2889 pr_err("%-15s %016llx %-13s %016llx\n",
2890 "kernel_gs_base:", save->kernel_gs_base,
2891 "sysenter_cs:", save->sysenter_cs);
2892 pr_err("%-15s %016llx %-13s %016llx\n",
2893 "sysenter_esp:", save->sysenter_esp,
2894 "sysenter_eip:", save->sysenter_eip);
2895 pr_err("%-15s %016llx %-13s %016llx\n",
2896 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2897 pr_err("%-15s %016llx %-13s %016llx\n",
2898 "br_from:", save->br_from, "br_to:", save->br_to);
2899 pr_err("%-15s %016llx %-13s %016llx\n",
2900 "excp_from:", save->last_excp_from,
2901 "excp_to:", save->last_excp_to);
2904 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2906 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2908 *info1 = control->exit_info_1;
2909 *info2 = control->exit_info_2;
2912 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
2914 struct vcpu_svm *svm = to_svm(vcpu);
2915 struct kvm_run *kvm_run = vcpu->run;
2916 u32 exit_code = svm->vmcb->control.exit_code;
2918 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2920 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2921 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2923 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2925 svm_complete_interrupts(svm);
2927 if (is_guest_mode(vcpu)) {
2930 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2931 svm->vmcb->control.exit_info_1,
2932 svm->vmcb->control.exit_info_2,
2933 svm->vmcb->control.exit_int_info,
2934 svm->vmcb->control.exit_int_info_err,
2937 vmexit = nested_svm_exit_special(svm);
2939 if (vmexit == NESTED_EXIT_CONTINUE)
2940 vmexit = nested_svm_exit_handled(svm);
2942 if (vmexit == NESTED_EXIT_DONE)
2946 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2947 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2948 kvm_run->fail_entry.hardware_entry_failure_reason
2949 = svm->vmcb->control.exit_code;
2954 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2955 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2956 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2957 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2958 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
2960 __func__, svm->vmcb->control.exit_int_info,
2963 if (exit_fastpath != EXIT_FASTPATH_NONE)
2966 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2967 || !svm_exit_handlers[exit_code]) {
2968 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2970 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2971 vcpu->run->internal.suberror =
2972 KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2973 vcpu->run->internal.ndata = 1;
2974 vcpu->run->internal.data[0] = exit_code;
2978 #ifdef CONFIG_RETPOLINE
2979 if (exit_code == SVM_EXIT_MSR)
2980 return msr_interception(svm);
2981 else if (exit_code == SVM_EXIT_VINTR)
2982 return interrupt_window_interception(svm);
2983 else if (exit_code == SVM_EXIT_INTR)
2984 return intr_interception(svm);
2985 else if (exit_code == SVM_EXIT_HLT)
2986 return halt_interception(svm);
2987 else if (exit_code == SVM_EXIT_NPF)
2988 return npf_interception(svm);
2990 return svm_exit_handlers[exit_code](svm);
2993 static void reload_tss(struct kvm_vcpu *vcpu)
2995 int cpu = raw_smp_processor_id();
2997 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2998 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3002 static void pre_svm_run(struct vcpu_svm *svm)
3004 int cpu = raw_smp_processor_id();
3006 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3008 if (sev_guest(svm->vcpu.kvm))
3009 return pre_sev_run(svm, cpu);
3011 /* FIXME: handle wraparound of asid_generation */
3012 if (svm->asid_generation != sd->asid_generation)
3016 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3018 struct vcpu_svm *svm = to_svm(vcpu);
3020 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3021 vcpu->arch.hflags |= HF_NMI_MASK;
3022 set_intercept(svm, INTERCEPT_IRET);
3023 ++vcpu->stat.nmi_injections;
3026 static void svm_set_irq(struct kvm_vcpu *vcpu)
3028 struct vcpu_svm *svm = to_svm(vcpu);
3030 BUG_ON(!(gif_set(svm)));
3032 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3033 ++vcpu->stat.irq_injections;
3035 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3036 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3039 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3041 struct vcpu_svm *svm = to_svm(vcpu);
3043 if (svm_nested_virtualize_tpr(vcpu))
3046 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3052 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3055 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3057 struct vcpu_svm *svm = to_svm(vcpu);
3058 struct vmcb *vmcb = svm->vmcb;
3064 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3067 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3068 (svm->vcpu.arch.hflags & HF_NMI_MASK);
3073 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3075 struct vcpu_svm *svm = to_svm(vcpu);
3076 if (svm->nested.nested_run_pending)
3079 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3080 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3083 return !svm_nmi_blocked(vcpu);
3086 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3088 struct vcpu_svm *svm = to_svm(vcpu);
3090 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3093 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3095 struct vcpu_svm *svm = to_svm(vcpu);
3098 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3099 set_intercept(svm, INTERCEPT_IRET);
3101 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3102 clr_intercept(svm, INTERCEPT_IRET);
3106 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3108 struct vcpu_svm *svm = to_svm(vcpu);
3109 struct vmcb *vmcb = svm->vmcb;
3114 if (is_guest_mode(vcpu)) {
3115 /* As long as interrupts are being delivered... */
3116 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3117 ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3118 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3121 /* ... vmexits aren't blocked by the interrupt shadow */
3122 if (nested_exit_on_intr(svm))
3125 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3129 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3132 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3134 struct vcpu_svm *svm = to_svm(vcpu);
3135 if (svm->nested.nested_run_pending)
3139 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3140 * e.g. if the IRQ arrived asynchronously after checking nested events.
3142 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3145 return !svm_interrupt_blocked(vcpu);
3148 static void enable_irq_window(struct kvm_vcpu *vcpu)
3150 struct vcpu_svm *svm = to_svm(vcpu);
3153 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3154 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3155 * get that intercept, this function will be called again though and
3156 * we'll get the vintr intercept. However, if the vGIF feature is
3157 * enabled, the STGI interception will not occur. Enable the irq
3158 * window under the assumption that the hardware will set the GIF.
3160 if (vgif_enabled(svm) || gif_set(svm)) {
3162 * IRQ window is not needed when AVIC is enabled,
3163 * unless we have pending ExtINT since it cannot be injected
3164 * via AVIC. In such case, we need to temporarily disable AVIC,
3165 * and fallback to injecting IRQ via V_IRQ.
3167 svm_toggle_avic_for_irq_window(vcpu, false);
3172 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3174 struct vcpu_svm *svm = to_svm(vcpu);
3176 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3178 return; /* IRET will cause a vm exit */
3180 if (!gif_set(svm)) {
3181 if (vgif_enabled(svm))
3182 set_intercept(svm, INTERCEPT_STGI);
3183 return; /* STGI will cause a vm exit */
3187 * Something prevents NMI from been injected. Single step over possible
3188 * problem (IRET or exception injection or interrupt shadow)
3190 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3191 svm->nmi_singlestep = true;
3192 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3195 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3200 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3205 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3207 struct vcpu_svm *svm = to_svm(vcpu);
3210 * Flush only the current ASID even if the TLB flush was invoked via
3211 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3212 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3213 * unconditionally does a TLB flush on both nested VM-Enter and nested
3214 * VM-Exit (via kvm_mmu_reset_context()).
3216 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3217 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3219 svm->asid_generation--;
3222 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3224 struct vcpu_svm *svm = to_svm(vcpu);
3226 invlpga(gva, svm->vmcb->control.asid);
3229 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3233 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3235 struct vcpu_svm *svm = to_svm(vcpu);
3237 if (svm_nested_virtualize_tpr(vcpu))
3240 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3241 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3242 kvm_set_cr8(vcpu, cr8);
3246 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3248 struct vcpu_svm *svm = to_svm(vcpu);
3251 if (svm_nested_virtualize_tpr(vcpu) ||
3252 kvm_vcpu_apicv_active(vcpu))
3255 cr8 = kvm_get_cr8(vcpu);
3256 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3257 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3260 static void svm_complete_interrupts(struct vcpu_svm *svm)
3264 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3265 unsigned int3_injected = svm->int3_injected;
3267 svm->int3_injected = 0;
3270 * If we've made progress since setting HF_IRET_MASK, we've
3271 * executed an IRET and can allow NMI injection.
3273 if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3274 && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3275 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3276 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3279 svm->vcpu.arch.nmi_injected = false;
3280 kvm_clear_exception_queue(&svm->vcpu);
3281 kvm_clear_interrupt_queue(&svm->vcpu);
3283 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3286 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3288 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3289 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3292 case SVM_EXITINTINFO_TYPE_NMI:
3293 svm->vcpu.arch.nmi_injected = true;
3295 case SVM_EXITINTINFO_TYPE_EXEPT:
3297 * In case of software exceptions, do not reinject the vector,
3298 * but re-execute the instruction instead. Rewind RIP first
3299 * if we emulated INT3 before.
3301 if (kvm_exception_is_soft(vector)) {
3302 if (vector == BP_VECTOR && int3_injected &&
3303 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3304 kvm_rip_write(&svm->vcpu,
3305 kvm_rip_read(&svm->vcpu) -
3309 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3310 u32 err = svm->vmcb->control.exit_int_info_err;
3311 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3314 kvm_requeue_exception(&svm->vcpu, vector);
3316 case SVM_EXITINTINFO_TYPE_INTR:
3317 kvm_queue_interrupt(&svm->vcpu, vector, false);
3324 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3326 struct vcpu_svm *svm = to_svm(vcpu);
3327 struct vmcb_control_area *control = &svm->vmcb->control;
3329 control->exit_int_info = control->event_inj;
3330 control->exit_int_info_err = control->event_inj_err;
3331 control->event_inj = 0;
3332 svm_complete_interrupts(svm);
3335 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3337 if (!is_guest_mode(vcpu) &&
3338 to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3339 to_svm(vcpu)->vmcb->control.exit_info_1)
3340 return handle_fastpath_set_msr_irqoff(vcpu);
3342 return EXIT_FASTPATH_NONE;
3345 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3347 static fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3349 fastpath_t exit_fastpath;
3350 struct vcpu_svm *svm = to_svm(vcpu);
3352 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3353 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3354 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3357 * Disable singlestep if we're injecting an interrupt/exception.
3358 * We don't want our modified rflags to be pushed on the stack where
3359 * we might not be able to easily reset them if we disabled NMI
3362 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3364 * Event injection happens before external interrupts cause a
3365 * vmexit and interrupts are disabled here, so smp_send_reschedule
3366 * is enough to force an immediate vmexit.
3368 disable_nmi_singlestep(svm);
3369 smp_send_reschedule(vcpu->cpu);
3374 sync_lapic_to_cr8(vcpu);
3376 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3379 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3382 if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3383 svm_set_dr6(svm, vcpu->arch.dr6);
3385 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3388 kvm_load_guest_xsave_state(vcpu);
3390 if (lapic_in_kernel(vcpu) &&
3391 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3392 kvm_wait_lapic_expire(vcpu);
3395 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3396 * it's non-zero. Since vmentry is serialising on affected CPUs, there
3397 * is no need to worry about the conditional branch over the wrmsr
3398 * being speculatively taken.
3400 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3402 __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3404 #ifdef CONFIG_X86_64
3405 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3407 loadsegment(fs, svm->host.fs);
3408 #ifndef CONFIG_X86_32_LAZY_GS
3409 loadsegment(gs, svm->host.gs);
3414 * We do not use IBRS in the kernel. If this vCPU has used the
3415 * SPEC_CTRL MSR it may have left it on; save the value and
3416 * turn it off. This is much more efficient than blindly adding
3417 * it to the atomic save/restore list. Especially as the former
3418 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3420 * For non-nested case:
3421 * If the L01 MSR bitmap does not intercept the MSR, then we need to
3425 * If the L02 MSR bitmap does not intercept the MSR, then we need to
3428 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3429 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3433 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3435 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3436 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3437 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3438 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3440 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3441 kvm_before_interrupt(&svm->vcpu);
3443 kvm_load_host_xsave_state(vcpu);
3446 /* Any pending NMI will happen here */
3447 exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3449 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3450 kvm_after_interrupt(&svm->vcpu);
3452 sync_cr8_to_lapic(vcpu);
3455 if (is_guest_mode(&svm->vcpu)) {
3456 sync_nested_vmcb_control(svm);
3457 svm->nested.nested_run_pending = 0;
3460 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3462 /* if exit due to PF check for async PF */
3463 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3464 svm->vcpu.arch.apf.host_apf_flags =
3465 kvm_read_and_reset_apf_flags();
3468 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3469 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3473 * We need to handle MC intercepts here before the vcpu has a chance to
3474 * change the physical cpu
3476 if (unlikely(svm->vmcb->control.exit_code ==
3477 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3478 svm_handle_mce(svm);
3480 mark_all_clean(svm->vmcb);
3481 return exit_fastpath;
3484 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
3486 struct vcpu_svm *svm = to_svm(vcpu);
3489 cr3 = __sme_set(root);
3491 svm->vmcb->control.nested_cr3 = cr3;
3492 mark_dirty(svm->vmcb, VMCB_NPT);
3494 /* Loading L2's CR3 is handled by enter_svm_guest_mode. */
3495 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3497 cr3 = vcpu->arch.cr3;
3500 svm->vmcb->save.cr3 = cr3;
3501 mark_dirty(svm->vmcb, VMCB_CR);
3504 static int is_disabled(void)
3508 rdmsrl(MSR_VM_CR, vm_cr);
3509 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3516 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3519 * Patch in the VMMCALL instruction:
3521 hypercall[0] = 0x0f;
3522 hypercall[1] = 0x01;
3523 hypercall[2] = 0xd9;
3526 static int __init svm_check_processor_compat(void)
3531 static bool svm_cpu_has_accelerated_tpr(void)
3536 static bool svm_has_emulated_msr(u32 index)
3539 case MSR_IA32_MCG_EXT_CTL:
3540 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3549 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3554 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3556 struct vcpu_svm *svm = to_svm(vcpu);
3558 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3559 boot_cpu_has(X86_FEATURE_XSAVE) &&
3560 boot_cpu_has(X86_FEATURE_XSAVES);
3562 /* Update nrips enabled cache */
3563 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3564 guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3566 if (!kvm_vcpu_apicv_active(vcpu))
3570 * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3571 * is exposed to the guest, disable AVIC.
3573 if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3574 kvm_request_apicv_update(vcpu->kvm, false,
3575 APICV_INHIBIT_REASON_X2APIC);
3578 * Currently, AVIC does not work with nested virtualization.
3579 * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3581 if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3582 kvm_request_apicv_update(vcpu->kvm, false,
3583 APICV_INHIBIT_REASON_NESTED);
3586 static bool svm_has_wbinvd_exit(void)
3591 #define PRE_EX(exit) { .exit_code = (exit), \
3592 .stage = X86_ICPT_PRE_EXCEPT, }
3593 #define POST_EX(exit) { .exit_code = (exit), \
3594 .stage = X86_ICPT_POST_EXCEPT, }
3595 #define POST_MEM(exit) { .exit_code = (exit), \
3596 .stage = X86_ICPT_POST_MEMACCESS, }
3598 static const struct __x86_intercept {
3600 enum x86_intercept_stage stage;
3601 } x86_intercept_map[] = {
3602 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
3603 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
3604 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
3605 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
3606 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
3607 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
3608 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
3609 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
3610 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
3611 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
3612 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
3613 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
3614 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
3615 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
3616 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
3617 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
3618 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
3619 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
3620 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
3621 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
3622 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
3623 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
3624 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
3625 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
3626 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
3627 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
3628 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
3629 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
3630 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
3631 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
3632 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
3633 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
3634 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
3635 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
3636 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
3637 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
3638 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
3639 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
3640 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
3641 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
3642 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
3643 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
3644 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
3645 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
3646 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
3647 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
3648 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
3655 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3656 struct x86_instruction_info *info,
3657 enum x86_intercept_stage stage,
3658 struct x86_exception *exception)
3660 struct vcpu_svm *svm = to_svm(vcpu);
3661 int vmexit, ret = X86EMUL_CONTINUE;
3662 struct __x86_intercept icpt_info;
3663 struct vmcb *vmcb = svm->vmcb;
3665 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3668 icpt_info = x86_intercept_map[info->intercept];
3670 if (stage != icpt_info.stage)
3673 switch (icpt_info.exit_code) {
3674 case SVM_EXIT_READ_CR0:
3675 if (info->intercept == x86_intercept_cr_read)
3676 icpt_info.exit_code += info->modrm_reg;
3678 case SVM_EXIT_WRITE_CR0: {
3679 unsigned long cr0, val;
3682 if (info->intercept == x86_intercept_cr_write)
3683 icpt_info.exit_code += info->modrm_reg;
3685 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3686 info->intercept == x86_intercept_clts)
3689 intercept = svm->nested.ctl.intercept;
3691 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3694 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3695 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
3697 if (info->intercept == x86_intercept_lmsw) {
3700 /* lmsw can't clear PE - catch this here */
3701 if (cr0 & X86_CR0_PE)
3706 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3710 case SVM_EXIT_READ_DR0:
3711 case SVM_EXIT_WRITE_DR0:
3712 icpt_info.exit_code += info->modrm_reg;
3715 if (info->intercept == x86_intercept_wrmsr)
3716 vmcb->control.exit_info_1 = 1;
3718 vmcb->control.exit_info_1 = 0;
3720 case SVM_EXIT_PAUSE:
3722 * We get this for NOP only, but pause
3723 * is rep not, check this here
3725 if (info->rep_prefix != REPE_PREFIX)
3728 case SVM_EXIT_IOIO: {
3732 if (info->intercept == x86_intercept_in ||
3733 info->intercept == x86_intercept_ins) {
3734 exit_info = ((info->src_val & 0xffff) << 16) |
3736 bytes = info->dst_bytes;
3738 exit_info = (info->dst_val & 0xffff) << 16;
3739 bytes = info->src_bytes;
3742 if (info->intercept == x86_intercept_outs ||
3743 info->intercept == x86_intercept_ins)
3744 exit_info |= SVM_IOIO_STR_MASK;
3746 if (info->rep_prefix)
3747 exit_info |= SVM_IOIO_REP_MASK;
3749 bytes = min(bytes, 4u);
3751 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3753 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3755 vmcb->control.exit_info_1 = exit_info;
3756 vmcb->control.exit_info_2 = info->next_rip;
3764 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3765 if (static_cpu_has(X86_FEATURE_NRIPS))
3766 vmcb->control.next_rip = info->next_rip;
3767 vmcb->control.exit_code = icpt_info.exit_code;
3768 vmexit = nested_svm_exit_handled(svm);
3770 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3777 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3781 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3783 if (pause_filter_thresh)
3784 shrink_ple_window(vcpu);
3787 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3789 /* [63:9] are reserved. */
3790 vcpu->arch.mcg_cap &= 0x1ff;
3793 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
3795 struct vcpu_svm *svm = to_svm(vcpu);
3797 /* Per APM Vol.2 15.22.2 "Response to SMI" */
3801 return is_smm(vcpu);
3804 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3806 struct vcpu_svm *svm = to_svm(vcpu);
3807 if (svm->nested.nested_run_pending)
3810 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
3811 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
3814 return !svm_smi_blocked(vcpu);
3817 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3819 struct vcpu_svm *svm = to_svm(vcpu);
3822 if (is_guest_mode(vcpu)) {
3823 /* FED8h - SVM Guest */
3824 put_smstate(u64, smstate, 0x7ed8, 1);
3825 /* FEE0h - SVM Guest VMCB Physical Address */
3826 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3828 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3829 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3830 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3832 ret = nested_svm_vmexit(svm);
3839 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
3841 struct vcpu_svm *svm = to_svm(vcpu);
3842 struct vmcb *nested_vmcb;
3843 struct kvm_host_map map;
3847 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3848 vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
3851 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
3853 nested_vmcb = map.hva;
3854 enter_svm_guest_mode(svm, vmcb, nested_vmcb);
3855 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3860 static void enable_smi_window(struct kvm_vcpu *vcpu)
3862 struct vcpu_svm *svm = to_svm(vcpu);
3864 if (!gif_set(svm)) {
3865 if (vgif_enabled(svm))
3866 set_intercept(svm, INTERCEPT_STGI);
3867 /* STGI will cause a vm exit */
3869 /* We must be in SMM; RSM will cause a vmexit anyway. */
3873 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3875 unsigned long cr4 = kvm_read_cr4(vcpu);
3876 bool smep = cr4 & X86_CR4_SMEP;
3877 bool smap = cr4 & X86_CR4_SMAP;
3878 bool is_user = svm_get_cpl(vcpu) == 3;
3881 * If RIP is invalid, go ahead with emulation which will cause an
3882 * internal error exit.
3884 if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3888 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3891 * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3892 * possible that CPU microcode implementing DecodeAssist will fail
3893 * to read bytes of instruction which caused #NPF. In this case,
3894 * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3895 * return 0 instead of the correct guest instruction bytes.
3897 * This happens because CPU microcode reading instruction bytes
3898 * uses a special opcode which attempts to read data using CPL=0
3899 * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3900 * fault, it gives up and returns no instruction bytes.
3903 * We reach here in case CPU supports DecodeAssist, raised #NPF and
3904 * returned 0 in GuestIntrBytes field of the VMCB.
3905 * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3906 * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3907 * in case vCPU CPL==3 (Because otherwise guest would have triggered
3908 * a SMEP fault instead of #NPF).
3909 * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3910 * As most guests enable SMAP if they have also enabled SMEP, use above
3911 * logic in order to attempt minimize false-positive of detecting errata
3912 * while still preserving all cases semantic correctness.
3915 * To determine what instruction the guest was executing, the hypervisor
3916 * will have to decode the instruction at the instruction pointer.
3918 * In non SEV guest, hypervisor will be able to read the guest
3919 * memory to decode the instruction pointer when insn_len is zero
3920 * so we return true to indicate that decoding is possible.
3922 * But in the SEV guest, the guest memory is encrypted with the
3923 * guest specific key and hypervisor will not be able to decode the
3924 * instruction pointer so we will not able to workaround it. Lets
3925 * print the error and request to kill the guest.
3927 if (smap && (!smep || is_user)) {
3928 if (!sev_guest(vcpu->kvm))
3931 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
3932 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3938 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3940 struct vcpu_svm *svm = to_svm(vcpu);
3943 * TODO: Last condition latch INIT signals on vCPU when
3944 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
3945 * To properly emulate the INIT intercept,
3946 * svm_check_nested_events() should call nested_svm_vmexit()
3947 * if an INIT signal is pending.
3949 return !gif_set(svm) ||
3950 (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3953 static void svm_vm_destroy(struct kvm *kvm)
3955 avic_vm_destroy(kvm);
3956 sev_vm_destroy(kvm);
3959 static int svm_vm_init(struct kvm *kvm)
3962 int ret = avic_vm_init(kvm);
3967 kvm_apicv_init(kvm, avic);
3971 static struct kvm_x86_ops svm_x86_ops __initdata = {
3972 .hardware_unsetup = svm_hardware_teardown,
3973 .hardware_enable = svm_hardware_enable,
3974 .hardware_disable = svm_hardware_disable,
3975 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3976 .has_emulated_msr = svm_has_emulated_msr,
3978 .vcpu_create = svm_create_vcpu,
3979 .vcpu_free = svm_free_vcpu,
3980 .vcpu_reset = svm_vcpu_reset,
3982 .vm_size = sizeof(struct kvm_svm),
3983 .vm_init = svm_vm_init,
3984 .vm_destroy = svm_vm_destroy,
3986 .prepare_guest_switch = svm_prepare_guest_switch,
3987 .vcpu_load = svm_vcpu_load,
3988 .vcpu_put = svm_vcpu_put,
3989 .vcpu_blocking = svm_vcpu_blocking,
3990 .vcpu_unblocking = svm_vcpu_unblocking,
3992 .update_bp_intercept = update_bp_intercept,
3993 .get_msr_feature = svm_get_msr_feature,
3994 .get_msr = svm_get_msr,
3995 .set_msr = svm_set_msr,
3996 .get_segment_base = svm_get_segment_base,
3997 .get_segment = svm_get_segment,
3998 .set_segment = svm_set_segment,
3999 .get_cpl = svm_get_cpl,
4000 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4001 .set_cr0 = svm_set_cr0,
4002 .set_cr4 = svm_set_cr4,
4003 .set_efer = svm_set_efer,
4004 .get_idt = svm_get_idt,
4005 .set_idt = svm_set_idt,
4006 .get_gdt = svm_get_gdt,
4007 .set_gdt = svm_set_gdt,
4008 .set_dr7 = svm_set_dr7,
4009 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4010 .cache_reg = svm_cache_reg,
4011 .get_rflags = svm_get_rflags,
4012 .set_rflags = svm_set_rflags,
4014 .tlb_flush_all = svm_flush_tlb,
4015 .tlb_flush_current = svm_flush_tlb,
4016 .tlb_flush_gva = svm_flush_tlb_gva,
4017 .tlb_flush_guest = svm_flush_tlb,
4019 .run = svm_vcpu_run,
4020 .handle_exit = handle_exit,
4021 .skip_emulated_instruction = skip_emulated_instruction,
4022 .update_emulated_instruction = NULL,
4023 .set_interrupt_shadow = svm_set_interrupt_shadow,
4024 .get_interrupt_shadow = svm_get_interrupt_shadow,
4025 .patch_hypercall = svm_patch_hypercall,
4026 .set_irq = svm_set_irq,
4027 .set_nmi = svm_inject_nmi,
4028 .queue_exception = svm_queue_exception,
4029 .cancel_injection = svm_cancel_injection,
4030 .interrupt_allowed = svm_interrupt_allowed,
4031 .nmi_allowed = svm_nmi_allowed,
4032 .get_nmi_mask = svm_get_nmi_mask,
4033 .set_nmi_mask = svm_set_nmi_mask,
4034 .enable_nmi_window = enable_nmi_window,
4035 .enable_irq_window = enable_irq_window,
4036 .update_cr8_intercept = update_cr8_intercept,
4037 .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4038 .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4039 .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4040 .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4041 .load_eoi_exitmap = svm_load_eoi_exitmap,
4042 .hwapic_irr_update = svm_hwapic_irr_update,
4043 .hwapic_isr_update = svm_hwapic_isr_update,
4044 .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4045 .apicv_post_state_restore = avic_post_state_restore,
4047 .set_tss_addr = svm_set_tss_addr,
4048 .set_identity_map_addr = svm_set_identity_map_addr,
4049 .get_tdp_level = get_npt_level,
4050 .get_mt_mask = svm_get_mt_mask,
4052 .get_exit_info = svm_get_exit_info,
4054 .cpuid_update = svm_cpuid_update,
4056 .has_wbinvd_exit = svm_has_wbinvd_exit,
4058 .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4060 .load_mmu_pgd = svm_load_mmu_pgd,
4062 .check_intercept = svm_check_intercept,
4063 .handle_exit_irqoff = svm_handle_exit_irqoff,
4065 .request_immediate_exit = __kvm_request_immediate_exit,
4067 .sched_in = svm_sched_in,
4069 .pmu_ops = &amd_pmu_ops,
4070 .nested_ops = &svm_nested_ops,
4072 .deliver_posted_interrupt = svm_deliver_avic_intr,
4073 .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4074 .update_pi_irte = svm_update_pi_irte,
4075 .setup_mce = svm_setup_mce,
4077 .smi_allowed = svm_smi_allowed,
4078 .pre_enter_smm = svm_pre_enter_smm,
4079 .pre_leave_smm = svm_pre_leave_smm,
4080 .enable_smi_window = enable_smi_window,
4082 .mem_enc_op = svm_mem_enc_op,
4083 .mem_enc_reg_region = svm_register_enc_region,
4084 .mem_enc_unreg_region = svm_unregister_enc_region,
4086 .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4088 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4091 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4092 .cpu_has_kvm_support = has_svm,
4093 .disabled_by_bios = is_disabled,
4094 .hardware_setup = svm_hardware_setup,
4095 .check_processor_compatibility = svm_check_processor_compat,
4097 .runtime_ops = &svm_x86_ops,
4100 static int __init svm_init(void)
4102 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4103 __alignof__(struct vcpu_svm), THIS_MODULE);
4106 static void __exit svm_exit(void)
4111 module_init(svm_init)
4112 module_exit(svm_exit)