arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/frame.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/mce.h>
  37 #include <asm/spec-ctrl.h>
  38 #include <asm/cpu_device_id.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is always on */
  94 } direct_access_msrs[] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_INVALID,                         .always = false },
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 bool npt_enabled = true;
 117 #else
 118 bool npt_enabled;
 119 #endif
 120
 121 /*
 122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 123  * pause_filter_count: On processors that support Pause filtering(indicated
 124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 125  *      count value. On VMRUN this value is loaded into an internal counter.
 126  *      Each time a pause instruction is executed, this counter is decremented
 127  *      until it reaches zero at which time a #VMEXIT is generated if pause
 128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 129  *      Intercept Filtering for more details.
 130  *      This also indicate if ple logic enabled.
 131  *
 132  * pause_filter_thresh: In addition, some processor families support advanced
 133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 134  *      the amount of time a guest is allowed to execute in a pause loop.
 135  *      In this mode, a 16-bit pause filter threshold field is added in the
 136  *      VMCB. The threshold value is a cycle count that is used to reset the
 137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 138  *      count value from VMCB into an internal counter. Then, on each pause
 139  *      instruction the hardware checks the elapsed number of cycles since
 140  *      the most recent pause instruction against the pause filter threshold.
 141  *      If the elapsed cycle count is greater than the pause filter threshold,
 142  *      then the internal pause count is reloaded from the VMCB and execution
 143  *      continues. If the elapsed cycle count is less than the pause filter
 144  *      threshold, then the internal pause count is decremented. If the count
 145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 146  *      triggered. If advanced pause filtering is supported and pause filter
 147  *      threshold field is set to zero, the filter will operate in the simpler,
 148  *      count only mode.
 149  */
 150
 151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 152 module_param(pause_filter_thresh, ushort, 0444);
 153
 154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 155 module_param(pause_filter_count, ushort, 0444);
 156
 157 /* Default doubles per-vcpu window every exit. */
 158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 159 module_param(pause_filter_count_grow, ushort, 0444);
 160
 161 /* Default resets per-vcpu window every exit to pause_filter_count. */
 162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 163 module_param(pause_filter_count_shrink, ushort, 0444);
 164
 165 /* Default is to compute the maximum so we can never overflow. */
 166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 167 module_param(pause_filter_count_max, ushort, 0444);
 168
 169 /* allow nested paging (virtualized MMU) for all guests */
 170 static int npt = true;
 171 module_param(npt, int, S_IRUGO);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 static bool __read_mostly dump_invalid_vmcb = 0;
 194 module_param(dump_invalid_vmcb, bool, 0644);
 195
 196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 197
 198 static void svm_complete_interrupts(struct vcpu_svm *svm);
 199
 200 static unsigned long iopm_base;
 201
 202 struct kvm_ldttss_desc {
 203         u16 limit0;
 204         u16 base0;
 205         unsigned base1:8, type:5, dpl:2, p:1;
 206         unsigned limit1:4, zero0:3, g:1, base2:8;
 207         u32 base3;
 208         u32 zero1;
 209 } __attribute__((packed));
 210
 211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 212
 213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 214
 215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 216 #define MSRS_RANGE_SIZE 2048
 217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 218
 219 u32 svm_msrpm_offset(u32 msr)
 220 {
 221         u32 offset;
 222         int i;
 223
 224         for (i = 0; i < NUM_MSR_MAPS; i++) {
 225                 if (msr < msrpm_ranges[i] ||
 226                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 227                         continue;
 228
 229                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 230                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 231
 232                 /* Now we have the u8 offset - but need the u32 offset */
 233                 return offset / 4;
 234         }
 235
 236         /* MSR not in any range */
 237         return MSR_INVALID;
 238 }
 239
 240 #define MAX_INST_SIZE 15
 241
 242 static inline void clgi(void)
 243 {
 244         asm volatile (__ex("clgi"));
 245 }
 246
 247 static inline void stgi(void)
 248 {
 249         asm volatile (__ex("stgi"));
 250 }
 251
 252 static inline void invlpga(unsigned long addr, u32 asid)
 253 {
 254         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 255 }
 256
 257 static int get_npt_level(struct kvm_vcpu *vcpu)
 258 {
 259 #ifdef CONFIG_X86_64
 260         return PT64_ROOT_4LEVEL;
 261 #else
 262         return PT32E_ROOT_LEVEL;
 263 #endif
 264 }
 265
 266 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 267 {
 268         vcpu->arch.efer = efer;
 269
 270         if (!npt_enabled) {
 271                 /* Shadow paging assumes NX to be available.  */
 272                 efer |= EFER_NX;
 273
 274                 if (!(efer & EFER_LMA))
 275                         efer &= ~EFER_LME;
 276         }
 277
 278         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 279         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 280 }
 281
 282 static int is_external_interrupt(u32 info)
 283 {
 284         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 285         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 286 }
 287
 288 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 289 {
 290         struct vcpu_svm *svm = to_svm(vcpu);
 291         u32 ret = 0;
 292
 293         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 294                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 295         return ret;
 296 }
 297
 298 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 299 {
 300         struct vcpu_svm *svm = to_svm(vcpu);
 301
 302         if (mask == 0)
 303                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 304         else
 305                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 306
 307 }
 308
 309 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 310 {
 311         struct vcpu_svm *svm = to_svm(vcpu);
 312
 313         if (nrips && svm->vmcb->control.next_rip != 0) {
 314                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 315                 svm->next_rip = svm->vmcb->control.next_rip;
 316         }
 317
 318         if (!svm->next_rip) {
 319                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 320                         return 0;
 321         } else {
 322                 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 323                         pr_err("%s: ip 0x%lx next 0x%llx\n",
 324                                __func__, kvm_rip_read(vcpu), svm->next_rip);
 325                 kvm_rip_write(vcpu, svm->next_rip);
 326         }
 327         svm_set_interrupt_shadow(vcpu, 0);
 328
 329         return 1;
 330 }
 331
 332 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 333 {
 334         struct vcpu_svm *svm = to_svm(vcpu);
 335         unsigned nr = vcpu->arch.exception.nr;
 336         bool has_error_code = vcpu->arch.exception.has_error_code;
 337         bool reinject = vcpu->arch.exception.injected;
 338         u32 error_code = vcpu->arch.exception.error_code;
 339
 340         /*
 341          * If we are within a nested VM we'd better #VMEXIT and let the guest
 342          * handle the exception
 343          */
 344         if (!reinject &&
 345             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 346                 return;
 347
 348         kvm_deliver_exception_payload(&svm->vcpu);
 349
 350         if (nr == BP_VECTOR && !nrips) {
 351                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 352
 353                 /*
 354                  * For guest debugging where we have to reinject #BP if some
 355                  * INT3 is guest-owned:
 356                  * Emulate nRIP by moving RIP forward. Will fail if injection
 357                  * raises a fault that is not intercepted. Still better than
 358                  * failing in all cases.
 359                  */
 360                 (void)skip_emulated_instruction(&svm->vcpu);
 361                 rip = kvm_rip_read(&svm->vcpu);
 362                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 363                 svm->int3_injected = rip - old_rip;
 364         }
 365
 366         svm->vmcb->control.event_inj = nr
 367                 | SVM_EVTINJ_VALID
 368                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 369                 | SVM_EVTINJ_TYPE_EXEPT;
 370         svm->vmcb->control.event_inj_err = error_code;
 371 }
 372
 373 static void svm_init_erratum_383(void)
 374 {
 375         u32 low, high;
 376         int err;
 377         u64 val;
 378
 379         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 380                 return;
 381
 382         /* Use _safe variants to not break nested virtualization */
 383         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 384         if (err)
 385                 return;
 386
 387         val |= (1ULL << 47);
 388
 389         low  = lower_32_bits(val);
 390         high = upper_32_bits(val);
 391
 392         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 393
 394         erratum_383_found = true;
 395 }
 396
 397 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 398 {
 399         /*
 400          * Guests should see errata 400 and 415 as fixed (assuming that
 401          * HLT and IO instructions are intercepted).
 402          */
 403         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 404         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 405
 406         /*
 407          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 408          * all osvw.status bits inside that length, including bit 0 (which is
 409          * reserved for erratum 298), are valid. However, if host processor's
 410          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 411          * be conservative here and therefore we tell the guest that erratum 298
 412          * is present (because we really don't know).
 413          */
 414         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 415                 vcpu->arch.osvw.status |= 1;
 416 }
 417
 418 static int has_svm(void)
 419 {
 420         const char *msg;
 421
 422         if (!cpu_has_svm(&msg)) {
 423                 printk(KERN_INFO "has_svm: %s\n", msg);
 424                 return 0;
 425         }
 426
 427         return 1;
 428 }
 429
 430 static void svm_hardware_disable(void)
 431 {
 432         /* Make sure we clean up behind us */
 433         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 434                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 435
 436         cpu_svm_disable();
 437
 438         amd_pmu_disable_virt();
 439 }
 440
 441 static int svm_hardware_enable(void)
 442 {
 443
 444         struct svm_cpu_data *sd;
 445         uint64_t efer;
 446         struct desc_struct *gdt;
 447         int me = raw_smp_processor_id();
 448
 449         rdmsrl(MSR_EFER, efer);
 450         if (efer & EFER_SVME)
 451                 return -EBUSY;
 452
 453         if (!has_svm()) {
 454                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 455                 return -EINVAL;
 456         }
 457         sd = per_cpu(svm_data, me);
 458         if (!sd) {
 459                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 460                 return -EINVAL;
 461         }
 462
 463         sd->asid_generation = 1;
 464         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 465         sd->next_asid = sd->max_asid + 1;
 466         sd->min_asid = max_sev_asid + 1;
 467
 468         gdt = get_current_gdt_rw();
 469         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 470
 471         wrmsrl(MSR_EFER, efer | EFER_SVME);
 472
 473         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 474
 475         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 476                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 477                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 478         }
 479
 480
 481         /*
 482          * Get OSVW bits.
 483          *
 484          * Note that it is possible to have a system with mixed processor
 485          * revisions and therefore different OSVW bits. If bits are not the same
 486          * on different processors then choose the worst case (i.e. if erratum
 487          * is present on one processor and not on another then assume that the
 488          * erratum is present everywhere).
 489          */
 490         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 491                 uint64_t len, status = 0;
 492                 int err;
 493
 494                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 495                 if (!err)
 496                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 497                                                       &err);
 498
 499                 if (err)
 500                         osvw_status = osvw_len = 0;
 501                 else {
 502                         if (len < osvw_len)
 503                                 osvw_len = len;
 504                         osvw_status |= status;
 505                         osvw_status &= (1ULL << osvw_len) - 1;
 506                 }
 507         } else
 508                 osvw_status = osvw_len = 0;
 509
 510         svm_init_erratum_383();
 511
 512         amd_pmu_enable_virt();
 513
 514         return 0;
 515 }
 516
 517 static void svm_cpu_uninit(int cpu)
 518 {
 519         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 520
 521         if (!sd)
 522                 return;
 523
 524         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 525         kfree(sd->sev_vmcbs);
 526         __free_page(sd->save_area);
 527         kfree(sd);
 528 }
 529
 530 static int svm_cpu_init(int cpu)
 531 {
 532         struct svm_cpu_data *sd;
 533
 534         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 535         if (!sd)
 536                 return -ENOMEM;
 537         sd->cpu = cpu;
 538         sd->save_area = alloc_page(GFP_KERNEL);
 539         if (!sd->save_area)
 540                 goto free_cpu_data;
 541
 542         if (svm_sev_enabled()) {
 543                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 544                                               sizeof(void *),
 545                                               GFP_KERNEL);
 546                 if (!sd->sev_vmcbs)
 547                         goto free_save_area;
 548         }
 549
 550         per_cpu(svm_data, cpu) = sd;
 551
 552         return 0;
 553
 554 free_save_area:
 555         __free_page(sd->save_area);
 556 free_cpu_data:
 557         kfree(sd);
 558         return -ENOMEM;
 559
 560 }
 561
 562 static bool valid_msr_intercept(u32 index)
 563 {
 564         int i;
 565
 566         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 567                 if (direct_access_msrs[i].index == index)
 568                         return true;
 569
 570         return false;
 571 }
 572
 573 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
 574 {
 575         u8 bit_write;
 576         unsigned long tmp;
 577         u32 offset;
 578         u32 *msrpm;
 579
 580         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 581                                       to_svm(vcpu)->msrpm;
 582
 583         offset    = svm_msrpm_offset(msr);
 584         bit_write = 2 * (msr & 0x0f) + 1;
 585         tmp       = msrpm[offset];
 586
 587         BUG_ON(offset == MSR_INVALID);
 588
 589         return !!test_bit(bit_write,  &tmp);
 590 }
 591
 592 static void set_msr_interception(u32 *msrpm, unsigned msr,
 593                                  int read, int write)
 594 {
 595         u8 bit_read, bit_write;
 596         unsigned long tmp;
 597         u32 offset;
 598
 599         /*
 600          * If this warning triggers extend the direct_access_msrs list at the
 601          * beginning of the file
 602          */
 603         WARN_ON(!valid_msr_intercept(msr));
 604
 605         offset    = svm_msrpm_offset(msr);
 606         bit_read  = 2 * (msr & 0x0f);
 607         bit_write = 2 * (msr & 0x0f) + 1;
 608         tmp       = msrpm[offset];
 609
 610         BUG_ON(offset == MSR_INVALID);
 611
 612         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 613         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 614
 615         msrpm[offset] = tmp;
 616 }
 617
 618 static void svm_vcpu_init_msrpm(u32 *msrpm)
 619 {
 620         int i;
 621
 622         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 623
 624         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 625                 if (!direct_access_msrs[i].always)
 626                         continue;
 627
 628                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 629         }
 630 }
 631
 632 static void add_msr_offset(u32 offset)
 633 {
 634         int i;
 635
 636         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 637
 638                 /* Offset already in list? */
 639                 if (msrpm_offsets[i] == offset)
 640                         return;
 641
 642                 /* Slot used by another offset? */
 643                 if (msrpm_offsets[i] != MSR_INVALID)
 644                         continue;
 645
 646                 /* Add offset to list */
 647                 msrpm_offsets[i] = offset;
 648
 649                 return;
 650         }
 651
 652         /*
 653          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 654          * increase MSRPM_OFFSETS in this case.
 655          */
 656         BUG();
 657 }
 658
 659 static void init_msrpm_offsets(void)
 660 {
 661         int i;
 662
 663         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 664
 665         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 666                 u32 offset;
 667
 668                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 669                 BUG_ON(offset == MSR_INVALID);
 670
 671                 add_msr_offset(offset);
 672         }
 673 }
 674
 675 static void svm_enable_lbrv(struct vcpu_svm *svm)
 676 {
 677         u32 *msrpm = svm->msrpm;
 678
 679         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 680         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 681         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 682         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 683         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 684 }
 685
 686 static void svm_disable_lbrv(struct vcpu_svm *svm)
 687 {
 688         u32 *msrpm = svm->msrpm;
 689
 690         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 691         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 692         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 693         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 694         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 695 }
 696
 697 void disable_nmi_singlestep(struct vcpu_svm *svm)
 698 {
 699         svm->nmi_singlestep = false;
 700
 701         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 702                 /* Clear our flags if they were not set by the guest */
 703                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 704                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 705                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 706                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 707         }
 708 }
 709
 710 static void grow_ple_window(struct kvm_vcpu *vcpu)
 711 {
 712         struct vcpu_svm *svm = to_svm(vcpu);
 713         struct vmcb_control_area *control = &svm->vmcb->control;
 714         int old = control->pause_filter_count;
 715
 716         control->pause_filter_count = __grow_ple_window(old,
 717                                                         pause_filter_count,
 718                                                         pause_filter_count_grow,
 719                                                         pause_filter_count_max);
 720
 721         if (control->pause_filter_count != old) {
 722                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 723                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 724                                             control->pause_filter_count, old);
 725         }
 726 }
 727
 728 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 729 {
 730         struct vcpu_svm *svm = to_svm(vcpu);
 731         struct vmcb_control_area *control = &svm->vmcb->control;
 732         int old = control->pause_filter_count;
 733
 734         control->pause_filter_count =
 735                                 __shrink_ple_window(old,
 736                                                     pause_filter_count,
 737                                                     pause_filter_count_shrink,
 738                                                     pause_filter_count);
 739         if (control->pause_filter_count != old) {
 740                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 741                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 742                                             control->pause_filter_count, old);
 743         }
 744 }
 745
 746 /*
 747  * The default MMIO mask is a single bit (excluding the present bit),
 748  * which could conflict with the memory encryption bit. Check for
 749  * memory encryption support and override the default MMIO mask if
 750  * memory encryption is enabled.
 751  */
 752 static __init void svm_adjust_mmio_mask(void)
 753 {
 754         unsigned int enc_bit, mask_bit;
 755         u64 msr, mask;
 756
 757         /* If there is no memory encryption support, use existing mask */
 758         if (cpuid_eax(0x80000000) < 0x8000001f)
 759                 return;
 760
 761         /* If memory encryption is not enabled, use existing mask */
 762         rdmsrl(MSR_K8_SYSCFG, msr);
 763         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 764                 return;
 765
 766         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 767         mask_bit = boot_cpu_data.x86_phys_bits;
 768
 769         /* Increment the mask bit if it is the same as the encryption bit */
 770         if (enc_bit == mask_bit)
 771                 mask_bit++;
 772
 773         /*
 774          * If the mask bit location is below 52, then some bits above the
 775          * physical addressing limit will always be reserved, so use the
 776          * rsvd_bits() function to generate the mask. This mask, along with
 777          * the present bit, will be used to generate a page fault with
 778          * PFER.RSV = 1.
 779          *
 780          * If the mask bit location is 52 (or above), then clear the mask.
 781          */
 782         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 783
 784         kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
 785 }
 786
 787 static void svm_hardware_teardown(void)
 788 {
 789         int cpu;
 790
 791         if (svm_sev_enabled())
 792                 sev_hardware_teardown();
 793
 794         for_each_possible_cpu(cpu)
 795                 svm_cpu_uninit(cpu);
 796
 797         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 798         iopm_base = 0;
 799 }
 800
 801 static __init void svm_set_cpu_caps(void)
 802 {
 803         kvm_set_cpu_caps();
 804
 805         supported_xss = 0;
 806
 807         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 808         if (nested) {
 809                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 810
 811                 if (nrips)
 812                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 813
 814                 if (npt_enabled)
 815                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 816         }
 817
 818         /* CPUID 0x80000008 */
 819         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 820             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 821                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 822 }
 823
 824 static __init int svm_hardware_setup(void)
 825 {
 826         int cpu;
 827         struct page *iopm_pages;
 828         void *iopm_va;
 829         int r;
 830
 831         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 832
 833         if (!iopm_pages)
 834                 return -ENOMEM;
 835
 836         iopm_va = page_address(iopm_pages);
 837         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 838         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 839
 840         init_msrpm_offsets();
 841
 842         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 843
 844         if (boot_cpu_has(X86_FEATURE_NX))
 845                 kvm_enable_efer_bits(EFER_NX);
 846
 847         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 848                 kvm_enable_efer_bits(EFER_FFXSR);
 849
 850         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 851                 kvm_has_tsc_control = true;
 852                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 853                 kvm_tsc_scaling_ratio_frac_bits = 32;
 854         }
 855
 856         /* Check for pause filtering support */
 857         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 858                 pause_filter_count = 0;
 859                 pause_filter_thresh = 0;
 860         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 861                 pause_filter_thresh = 0;
 862         }
 863
 864         if (nested) {
 865                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 866                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 867         }
 868
 869         if (sev) {
 870                 if (boot_cpu_has(X86_FEATURE_SEV) &&
 871                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
 872                         r = sev_hardware_setup();
 873                         if (r)
 874                                 sev = false;
 875                 } else {
 876                         sev = false;
 877                 }
 878         }
 879
 880         svm_adjust_mmio_mask();
 881
 882         for_each_possible_cpu(cpu) {
 883                 r = svm_cpu_init(cpu);
 884                 if (r)
 885                         goto err;
 886         }
 887
 888         if (!boot_cpu_has(X86_FEATURE_NPT))
 889                 npt_enabled = false;
 890
 891         if (npt_enabled && !npt)
 892                 npt_enabled = false;
 893
 894         kvm_configure_mmu(npt_enabled, PT_PDPE_LEVEL);
 895         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 896
 897         if (nrips) {
 898                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
 899                         nrips = false;
 900         }
 901
 902         if (avic) {
 903                 if (!npt_enabled ||
 904                     !boot_cpu_has(X86_FEATURE_AVIC) ||
 905                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
 906                         avic = false;
 907                 } else {
 908                         pr_info("AVIC enabled\n");
 909
 910                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
 911                 }
 912         }
 913
 914         if (vls) {
 915                 if (!npt_enabled ||
 916                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
 917                     !IS_ENABLED(CONFIG_X86_64)) {
 918                         vls = false;
 919                 } else {
 920                         pr_info("Virtual VMLOAD VMSAVE supported\n");
 921                 }
 922         }
 923
 924         if (vgif) {
 925                 if (!boot_cpu_has(X86_FEATURE_VGIF))
 926                         vgif = false;
 927                 else
 928                         pr_info("Virtual GIF supported\n");
 929         }
 930
 931         svm_set_cpu_caps();
 932
 933         return 0;
 934
 935 err:
 936         svm_hardware_teardown();
 937         return r;
 938 }
 939
 940 static void init_seg(struct vmcb_seg *seg)
 941 {
 942         seg->selector = 0;
 943         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 944                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 945         seg->limit = 0xffff;
 946         seg->base = 0;
 947 }
 948
 949 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 950 {
 951         seg->selector = 0;
 952         seg->attrib = SVM_SELECTOR_P_MASK | type;
 953         seg->limit = 0xffff;
 954         seg->base = 0;
 955 }
 956
 957 static u64 svm_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
 958 {
 959         struct vcpu_svm *svm = to_svm(vcpu);
 960
 961         if (is_guest_mode(vcpu))
 962                 return svm->nested.hsave->control.tsc_offset;
 963
 964         return vcpu->arch.tsc_offset;
 965 }
 966
 967 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 968 {
 969         struct vcpu_svm *svm = to_svm(vcpu);
 970         u64 g_tsc_offset = 0;
 971
 972         if (is_guest_mode(vcpu)) {
 973                 /* Write L1's TSC offset.  */
 974                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 975                                svm->nested.hsave->control.tsc_offset;
 976                 svm->nested.hsave->control.tsc_offset = offset;
 977         }
 978
 979         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
 980                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
 981                                    offset);
 982
 983         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 984
 985         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 986         return svm->vmcb->control.tsc_offset;
 987 }
 988
 989 static void init_vmcb(struct vcpu_svm *svm)
 990 {
 991         struct vmcb_control_area *control = &svm->vmcb->control;
 992         struct vmcb_save_area *save = &svm->vmcb->save;
 993
 994         svm->vcpu.arch.hflags = 0;
 995
 996         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 997         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 998         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 999         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1000         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1001         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
1002         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1003                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
1004
1005         set_dr_intercepts(svm);
1006
1007         set_exception_intercept(svm, PF_VECTOR);
1008         set_exception_intercept(svm, UD_VECTOR);
1009         set_exception_intercept(svm, MC_VECTOR);
1010         set_exception_intercept(svm, AC_VECTOR);
1011         set_exception_intercept(svm, DB_VECTOR);
1012         /*
1013          * Guest access to VMware backdoor ports could legitimately
1014          * trigger #GP because of TSS I/O permission bitmap.
1015          * We intercept those #GP and allow access to them anyway
1016          * as VMware does.
1017          */
1018         if (enable_vmware_backdoor)
1019                 set_exception_intercept(svm, GP_VECTOR);
1020
1021         set_intercept(svm, INTERCEPT_INTR);
1022         set_intercept(svm, INTERCEPT_NMI);
1023         set_intercept(svm, INTERCEPT_SMI);
1024         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1025         set_intercept(svm, INTERCEPT_RDPMC);
1026         set_intercept(svm, INTERCEPT_CPUID);
1027         set_intercept(svm, INTERCEPT_INVD);
1028         set_intercept(svm, INTERCEPT_INVLPG);
1029         set_intercept(svm, INTERCEPT_INVLPGA);
1030         set_intercept(svm, INTERCEPT_IOIO_PROT);
1031         set_intercept(svm, INTERCEPT_MSR_PROT);
1032         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1033         set_intercept(svm, INTERCEPT_SHUTDOWN);
1034         set_intercept(svm, INTERCEPT_VMRUN);
1035         set_intercept(svm, INTERCEPT_VMMCALL);
1036         set_intercept(svm, INTERCEPT_VMLOAD);
1037         set_intercept(svm, INTERCEPT_VMSAVE);
1038         set_intercept(svm, INTERCEPT_STGI);
1039         set_intercept(svm, INTERCEPT_CLGI);
1040         set_intercept(svm, INTERCEPT_SKINIT);
1041         set_intercept(svm, INTERCEPT_WBINVD);
1042         set_intercept(svm, INTERCEPT_XSETBV);
1043         set_intercept(svm, INTERCEPT_RDPRU);
1044         set_intercept(svm, INTERCEPT_RSM);
1045
1046         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1047                 set_intercept(svm, INTERCEPT_MONITOR);
1048                 set_intercept(svm, INTERCEPT_MWAIT);
1049         }
1050
1051         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1052                 set_intercept(svm, INTERCEPT_HLT);
1053
1054         control->iopm_base_pa = __sme_set(iopm_base);
1055         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1056         control->int_ctl = V_INTR_MASKING_MASK;
1057
1058         init_seg(&save->es);
1059         init_seg(&save->ss);
1060         init_seg(&save->ds);
1061         init_seg(&save->fs);
1062         init_seg(&save->gs);
1063
1064         save->cs.selector = 0xf000;
1065         save->cs.base = 0xffff0000;
1066         /* Executable/Readable Code Segment */
1067         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1068                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1069         save->cs.limit = 0xffff;
1070
1071         save->gdtr.limit = 0xffff;
1072         save->idtr.limit = 0xffff;
1073
1074         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1075         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1076
1077         svm_set_efer(&svm->vcpu, 0);
1078         save->dr6 = 0xffff0ff0;
1079         kvm_set_rflags(&svm->vcpu, 2);
1080         save->rip = 0x0000fff0;
1081         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1082
1083         /*
1084          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1085          * It also updates the guest-visible cr0 value.
1086          */
1087         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1088         kvm_mmu_reset_context(&svm->vcpu);
1089
1090         save->cr4 = X86_CR4_PAE;
1091         /* rdx = ?? */
1092
1093         if (npt_enabled) {
1094                 /* Setup VMCB for Nested Paging */
1095                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1096                 clr_intercept(svm, INTERCEPT_INVLPG);
1097                 clr_exception_intercept(svm, PF_VECTOR);
1098                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1099                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1100                 save->g_pat = svm->vcpu.arch.pat;
1101                 save->cr3 = 0;
1102                 save->cr4 = 0;
1103         }
1104         svm->asid_generation = 0;
1105
1106         svm->nested.vmcb = 0;
1107         svm->vcpu.arch.hflags = 0;
1108
1109         if (pause_filter_count) {
1110                 control->pause_filter_count = pause_filter_count;
1111                 if (pause_filter_thresh)
1112                         control->pause_filter_thresh = pause_filter_thresh;
1113                 set_intercept(svm, INTERCEPT_PAUSE);
1114         } else {
1115                 clr_intercept(svm, INTERCEPT_PAUSE);
1116         }
1117
1118         if (kvm_vcpu_apicv_active(&svm->vcpu))
1119                 avic_init_vmcb(svm);
1120
1121         /*
1122          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1123          * in VMCB and clear intercepts to avoid #VMEXIT.
1124          */
1125         if (vls) {
1126                 clr_intercept(svm, INTERCEPT_VMLOAD);
1127                 clr_intercept(svm, INTERCEPT_VMSAVE);
1128                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1129         }
1130
1131         if (vgif) {
1132                 clr_intercept(svm, INTERCEPT_STGI);
1133                 clr_intercept(svm, INTERCEPT_CLGI);
1134                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1135         }
1136
1137         if (sev_guest(svm->vcpu.kvm)) {
1138                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1139                 clr_exception_intercept(svm, UD_VECTOR);
1140         }
1141
1142         mark_all_dirty(svm->vmcb);
1143
1144         enable_gif(svm);
1145
1146 }
1147
1148 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1149 {
1150         struct vcpu_svm *svm = to_svm(vcpu);
1151         u32 dummy;
1152         u32 eax = 1;
1153
1154         svm->spec_ctrl = 0;
1155         svm->virt_spec_ctrl = 0;
1156
1157         if (!init_event) {
1158                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1159                                            MSR_IA32_APICBASE_ENABLE;
1160                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1161                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1162         }
1163         init_vmcb(svm);
1164
1165         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1166         kvm_rdx_write(vcpu, eax);
1167
1168         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1169                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1170 }
1171
1172 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1173 {
1174         struct vcpu_svm *svm;
1175         struct page *page;
1176         struct page *msrpm_pages;
1177         struct page *hsave_page;
1178         struct page *nested_msrpm_pages;
1179         int err;
1180
1181         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1182         svm = to_svm(vcpu);
1183
1184         err = -ENOMEM;
1185         page = alloc_page(GFP_KERNEL_ACCOUNT);
1186         if (!page)
1187                 goto out;
1188
1189         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1190         if (!msrpm_pages)
1191                 goto free_page1;
1192
1193         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1194         if (!nested_msrpm_pages)
1195                 goto free_page2;
1196
1197         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
1198         if (!hsave_page)
1199                 goto free_page3;
1200
1201         err = avic_init_vcpu(svm);
1202         if (err)
1203                 goto free_page4;
1204
1205         /* We initialize this flag to true to make sure that the is_running
1206          * bit would be set the first time the vcpu is loaded.
1207          */
1208         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1209                 svm->avic_is_running = true;
1210
1211         svm->nested.hsave = page_address(hsave_page);
1212
1213         svm->msrpm = page_address(msrpm_pages);
1214         svm_vcpu_init_msrpm(svm->msrpm);
1215
1216         svm->nested.msrpm = page_address(nested_msrpm_pages);
1217         svm_vcpu_init_msrpm(svm->nested.msrpm);
1218
1219         svm->vmcb = page_address(page);
1220         clear_page(svm->vmcb);
1221         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1222         svm->asid_generation = 0;
1223         init_vmcb(svm);
1224
1225         svm_init_osvw(vcpu);
1226         vcpu->arch.microcode_version = 0x01000065;
1227
1228         return 0;
1229
1230 free_page4:
1231         __free_page(hsave_page);
1232 free_page3:
1233         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1234 free_page2:
1235         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1236 free_page1:
1237         __free_page(page);
1238 out:
1239         return err;
1240 }
1241
1242 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1243 {
1244         int i;
1245
1246         for_each_online_cpu(i)
1247                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1248 }
1249
1250 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1251 {
1252         struct vcpu_svm *svm = to_svm(vcpu);
1253
1254         /*
1255          * The vmcb page can be recycled, causing a false negative in
1256          * svm_vcpu_load(). So, ensure that no logical CPU has this
1257          * vmcb page recorded as its current vmcb.
1258          */
1259         svm_clear_current_vmcb(svm->vmcb);
1260
1261         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1262         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1263         __free_page(virt_to_page(svm->nested.hsave));
1264         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1265 }
1266
1267 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1268 {
1269         struct vcpu_svm *svm = to_svm(vcpu);
1270         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1271         int i;
1272
1273         if (unlikely(cpu != vcpu->cpu)) {
1274                 svm->asid_generation = 0;
1275                 mark_all_dirty(svm->vmcb);
1276         }
1277
1278 #ifdef CONFIG_X86_64
1279         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1280 #endif
1281         savesegment(fs, svm->host.fs);
1282         savesegment(gs, svm->host.gs);
1283         svm->host.ldt = kvm_read_ldt();
1284
1285         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1286                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1287
1288         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1289                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1290                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1291                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1292                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1293                 }
1294         }
1295         /* This assumes that the kernel never uses MSR_TSC_AUX */
1296         if (static_cpu_has(X86_FEATURE_RDTSCP))
1297                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1298
1299         if (sd->current_vmcb != svm->vmcb) {
1300                 sd->current_vmcb = svm->vmcb;
1301                 indirect_branch_prediction_barrier();
1302         }
1303         avic_vcpu_load(vcpu, cpu);
1304 }
1305
1306 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1307 {
1308         struct vcpu_svm *svm = to_svm(vcpu);
1309         int i;
1310
1311         avic_vcpu_put(vcpu);
1312
1313         ++vcpu->stat.host_state_reload;
1314         kvm_load_ldt(svm->host.ldt);
1315 #ifdef CONFIG_X86_64
1316         loadsegment(fs, svm->host.fs);
1317         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1318         load_gs_index(svm->host.gs);
1319 #else
1320 #ifdef CONFIG_X86_32_LAZY_GS
1321         loadsegment(gs, svm->host.gs);
1322 #endif
1323 #endif
1324         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1325                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1326 }
1327
1328 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1329 {
1330         struct vcpu_svm *svm = to_svm(vcpu);
1331         unsigned long rflags = svm->vmcb->save.rflags;
1332
1333         if (svm->nmi_singlestep) {
1334                 /* Hide our flags if they were not set by the guest */
1335                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1336                         rflags &= ~X86_EFLAGS_TF;
1337                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1338                         rflags &= ~X86_EFLAGS_RF;
1339         }
1340         return rflags;
1341 }
1342
1343 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1344 {
1345         if (to_svm(vcpu)->nmi_singlestep)
1346                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1347
1348        /*
1349         * Any change of EFLAGS.VM is accompanied by a reload of SS
1350         * (caused by either a task switch or an inter-privilege IRET),
1351         * so we do not need to update the CPL here.
1352         */
1353         to_svm(vcpu)->vmcb->save.rflags = rflags;
1354 }
1355
1356 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1357 {
1358         switch (reg) {
1359         case VCPU_EXREG_PDPTR:
1360                 BUG_ON(!npt_enabled);
1361                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1362                 break;
1363         default:
1364                 WARN_ON_ONCE(1);
1365         }
1366 }
1367
1368 static inline void svm_enable_vintr(struct vcpu_svm *svm)
1369 {
1370         struct vmcb_control_area *control;
1371
1372         /* The following fields are ignored when AVIC is enabled */
1373         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1374
1375         /*
1376          * This is just a dummy VINTR to actually cause a vmexit to happen.
1377          * Actual injection of virtual interrupts happens through EVENTINJ.
1378          */
1379         control = &svm->vmcb->control;
1380         control->int_vector = 0x0;
1381         control->int_ctl &= ~V_INTR_PRIO_MASK;
1382         control->int_ctl |= V_IRQ_MASK |
1383                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1384         mark_dirty(svm->vmcb, VMCB_INTR);
1385 }
1386
1387 static void svm_set_vintr(struct vcpu_svm *svm)
1388 {
1389         set_intercept(svm, INTERCEPT_VINTR);
1390         if (is_intercept(svm, INTERCEPT_VINTR))
1391                 svm_enable_vintr(svm);
1392 }
1393
1394 static void svm_clear_vintr(struct vcpu_svm *svm)
1395 {
1396         clr_intercept(svm, INTERCEPT_VINTR);
1397
1398         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1399         mark_dirty(svm->vmcb, VMCB_INTR);
1400 }
1401
1402 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1403 {
1404         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1405
1406         switch (seg) {
1407         case VCPU_SREG_CS: return &save->cs;
1408         case VCPU_SREG_DS: return &save->ds;
1409         case VCPU_SREG_ES: return &save->es;
1410         case VCPU_SREG_FS: return &save->fs;
1411         case VCPU_SREG_GS: return &save->gs;
1412         case VCPU_SREG_SS: return &save->ss;
1413         case VCPU_SREG_TR: return &save->tr;
1414         case VCPU_SREG_LDTR: return &save->ldtr;
1415         }
1416         BUG();
1417         return NULL;
1418 }
1419
1420 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1421 {
1422         struct vmcb_seg *s = svm_seg(vcpu, seg);
1423
1424         return s->base;
1425 }
1426
1427 static void svm_get_segment(struct kvm_vcpu *vcpu,
1428                             struct kvm_segment *var, int seg)
1429 {
1430         struct vmcb_seg *s = svm_seg(vcpu, seg);
1431
1432         var->base = s->base;
1433         var->limit = s->limit;
1434         var->selector = s->selector;
1435         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1436         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1437         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1438         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1439         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1440         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1441         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1442
1443         /*
1444          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1445          * However, the SVM spec states that the G bit is not observed by the
1446          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1447          * So let's synthesize a legal G bit for all segments, this helps
1448          * running KVM nested. It also helps cross-vendor migration, because
1449          * Intel's vmentry has a check on the 'G' bit.
1450          */
1451         var->g = s->limit > 0xfffff;
1452
1453         /*
1454          * AMD's VMCB does not have an explicit unusable field, so emulate it
1455          * for cross vendor migration purposes by "not present"
1456          */
1457         var->unusable = !var->present;
1458
1459         switch (seg) {
1460         case VCPU_SREG_TR:
1461                 /*
1462                  * Work around a bug where the busy flag in the tr selector
1463                  * isn't exposed
1464                  */
1465                 var->type |= 0x2;
1466                 break;
1467         case VCPU_SREG_DS:
1468         case VCPU_SREG_ES:
1469         case VCPU_SREG_FS:
1470         case VCPU_SREG_GS:
1471                 /*
1472                  * The accessed bit must always be set in the segment
1473                  * descriptor cache, although it can be cleared in the
1474                  * descriptor, the cached bit always remains at 1. Since
1475                  * Intel has a check on this, set it here to support
1476                  * cross-vendor migration.
1477                  */
1478                 if (!var->unusable)
1479                         var->type |= 0x1;
1480                 break;
1481         case VCPU_SREG_SS:
1482                 /*
1483                  * On AMD CPUs sometimes the DB bit in the segment
1484                  * descriptor is left as 1, although the whole segment has
1485                  * been made unusable. Clear it here to pass an Intel VMX
1486                  * entry check when cross vendor migrating.
1487                  */
1488                 if (var->unusable)
1489                         var->db = 0;
1490                 /* This is symmetric with svm_set_segment() */
1491                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1492                 break;
1493         }
1494 }
1495
1496 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1497 {
1498         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1499
1500         return save->cpl;
1501 }
1502
1503 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1504 {
1505         struct vcpu_svm *svm = to_svm(vcpu);
1506
1507         dt->size = svm->vmcb->save.idtr.limit;
1508         dt->address = svm->vmcb->save.idtr.base;
1509 }
1510
1511 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1512 {
1513         struct vcpu_svm *svm = to_svm(vcpu);
1514
1515         svm->vmcb->save.idtr.limit = dt->size;
1516         svm->vmcb->save.idtr.base = dt->address ;
1517         mark_dirty(svm->vmcb, VMCB_DT);
1518 }
1519
1520 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1521 {
1522         struct vcpu_svm *svm = to_svm(vcpu);
1523
1524         dt->size = svm->vmcb->save.gdtr.limit;
1525         dt->address = svm->vmcb->save.gdtr.base;
1526 }
1527
1528 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1529 {
1530         struct vcpu_svm *svm = to_svm(vcpu);
1531
1532         svm->vmcb->save.gdtr.limit = dt->size;
1533         svm->vmcb->save.gdtr.base = dt->address ;
1534         mark_dirty(svm->vmcb, VMCB_DT);
1535 }
1536
1537 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1538 {
1539 }
1540
1541 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1542 {
1543 }
1544
1545 static void update_cr0_intercept(struct vcpu_svm *svm)
1546 {
1547         ulong gcr0 = svm->vcpu.arch.cr0;
1548         u64 *hcr0 = &svm->vmcb->save.cr0;
1549
1550         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1551                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1552
1553         mark_dirty(svm->vmcb, VMCB_CR);
1554
1555         if (gcr0 == *hcr0) {
1556                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1557                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1558         } else {
1559                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1560                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1561         }
1562 }
1563
1564 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1565 {
1566         struct vcpu_svm *svm = to_svm(vcpu);
1567
1568 #ifdef CONFIG_X86_64
1569         if (vcpu->arch.efer & EFER_LME) {
1570                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1571                         vcpu->arch.efer |= EFER_LMA;
1572                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1573                 }
1574
1575                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1576                         vcpu->arch.efer &= ~EFER_LMA;
1577                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1578                 }
1579         }
1580 #endif
1581         vcpu->arch.cr0 = cr0;
1582
1583         if (!npt_enabled)
1584                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1585
1586         /*
1587          * re-enable caching here because the QEMU bios
1588          * does not do it - this results in some delay at
1589          * reboot
1590          */
1591         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1592                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1593         svm->vmcb->save.cr0 = cr0;
1594         mark_dirty(svm->vmcb, VMCB_CR);
1595         update_cr0_intercept(svm);
1596 }
1597
1598 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1599 {
1600         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1601         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1602
1603         if (cr4 & X86_CR4_VMXE)
1604                 return 1;
1605
1606         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1607                 svm_flush_tlb(vcpu);
1608
1609         vcpu->arch.cr4 = cr4;
1610         if (!npt_enabled)
1611                 cr4 |= X86_CR4_PAE;
1612         cr4 |= host_cr4_mce;
1613         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1614         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1615         return 0;
1616 }
1617
1618 static void svm_set_segment(struct kvm_vcpu *vcpu,
1619                             struct kvm_segment *var, int seg)
1620 {
1621         struct vcpu_svm *svm = to_svm(vcpu);
1622         struct vmcb_seg *s = svm_seg(vcpu, seg);
1623
1624         s->base = var->base;
1625         s->limit = var->limit;
1626         s->selector = var->selector;
1627         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1628         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1629         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1630         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1631         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1632         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1633         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1634         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1635
1636         /*
1637          * This is always accurate, except if SYSRET returned to a segment
1638          * with SS.DPL != 3.  Intel does not have this quirk, and always
1639          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1640          * would entail passing the CPL to userspace and back.
1641          */
1642         if (seg == VCPU_SREG_SS)
1643                 /* This is symmetric with svm_get_segment() */
1644                 svm->vmcb->save.cpl = (var->dpl & 3);
1645
1646         mark_dirty(svm->vmcb, VMCB_SEG);
1647 }
1648
1649 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1650 {
1651         struct vcpu_svm *svm = to_svm(vcpu);
1652
1653         clr_exception_intercept(svm, BP_VECTOR);
1654
1655         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1656                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1657                         set_exception_intercept(svm, BP_VECTOR);
1658         } else
1659                 vcpu->guest_debug = 0;
1660 }
1661
1662 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1663 {
1664         if (sd->next_asid > sd->max_asid) {
1665                 ++sd->asid_generation;
1666                 sd->next_asid = sd->min_asid;
1667                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1668         }
1669
1670         svm->asid_generation = sd->asid_generation;
1671         svm->vmcb->control.asid = sd->next_asid++;
1672
1673         mark_dirty(svm->vmcb, VMCB_ASID);
1674 }
1675
1676 static u64 svm_get_dr6(struct kvm_vcpu *vcpu)
1677 {
1678         return to_svm(vcpu)->vmcb->save.dr6;
1679 }
1680
1681 static void svm_set_dr6(struct kvm_vcpu *vcpu, unsigned long value)
1682 {
1683         struct vcpu_svm *svm = to_svm(vcpu);
1684
1685         svm->vmcb->save.dr6 = value;
1686         mark_dirty(svm->vmcb, VMCB_DR);
1687 }
1688
1689 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1690 {
1691         struct vcpu_svm *svm = to_svm(vcpu);
1692
1693         get_debugreg(vcpu->arch.db[0], 0);
1694         get_debugreg(vcpu->arch.db[1], 1);
1695         get_debugreg(vcpu->arch.db[2], 2);
1696         get_debugreg(vcpu->arch.db[3], 3);
1697         vcpu->arch.dr6 = svm_get_dr6(vcpu);
1698         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1699
1700         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1701         set_dr_intercepts(svm);
1702 }
1703
1704 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1705 {
1706         struct vcpu_svm *svm = to_svm(vcpu);
1707
1708         svm->vmcb->save.dr7 = value;
1709         mark_dirty(svm->vmcb, VMCB_DR);
1710 }
1711
1712 static int pf_interception(struct vcpu_svm *svm)
1713 {
1714         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1715         u64 error_code = svm->vmcb->control.exit_info_1;
1716
1717         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1718                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1719                         svm->vmcb->control.insn_bytes : NULL,
1720                         svm->vmcb->control.insn_len);
1721 }
1722
1723 static int npf_interception(struct vcpu_svm *svm)
1724 {
1725         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1726         u64 error_code = svm->vmcb->control.exit_info_1;
1727
1728         trace_kvm_page_fault(fault_address, error_code);
1729         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1730                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1731                         svm->vmcb->control.insn_bytes : NULL,
1732                         svm->vmcb->control.insn_len);
1733 }
1734
1735 static int db_interception(struct vcpu_svm *svm)
1736 {
1737         struct kvm_run *kvm_run = svm->vcpu.run;
1738         struct kvm_vcpu *vcpu = &svm->vcpu;
1739
1740         if (!(svm->vcpu.guest_debug &
1741               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1742                 !svm->nmi_singlestep) {
1743                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1744                 return 1;
1745         }
1746
1747         if (svm->nmi_singlestep) {
1748                 disable_nmi_singlestep(svm);
1749                 /* Make sure we check for pending NMIs upon entry */
1750                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1751         }
1752
1753         if (svm->vcpu.guest_debug &
1754             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1755                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1756                 kvm_run->debug.arch.pc =
1757                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1758                 kvm_run->debug.arch.exception = DB_VECTOR;
1759                 return 0;
1760         }
1761
1762         return 1;
1763 }
1764
1765 static int bp_interception(struct vcpu_svm *svm)
1766 {
1767         struct kvm_run *kvm_run = svm->vcpu.run;
1768
1769         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1770         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1771         kvm_run->debug.arch.exception = BP_VECTOR;
1772         return 0;
1773 }
1774
1775 static int ud_interception(struct vcpu_svm *svm)
1776 {
1777         return handle_ud(&svm->vcpu);
1778 }
1779
1780 static int ac_interception(struct vcpu_svm *svm)
1781 {
1782         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1783         return 1;
1784 }
1785
1786 static int gp_interception(struct vcpu_svm *svm)
1787 {
1788         struct kvm_vcpu *vcpu = &svm->vcpu;
1789         u32 error_code = svm->vmcb->control.exit_info_1;
1790
1791         WARN_ON_ONCE(!enable_vmware_backdoor);
1792
1793         /*
1794          * VMware backdoor emulation on #GP interception only handles IN{S},
1795          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1796          */
1797         if (error_code) {
1798                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1799                 return 1;
1800         }
1801         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1802 }
1803
1804 static bool is_erratum_383(void)
1805 {
1806         int err, i;
1807         u64 value;
1808
1809         if (!erratum_383_found)
1810                 return false;
1811
1812         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1813         if (err)
1814                 return false;
1815
1816         /* Bit 62 may or may not be set for this mce */
1817         value &= ~(1ULL << 62);
1818
1819         if (value != 0xb600000000010015ULL)
1820                 return false;
1821
1822         /* Clear MCi_STATUS registers */
1823         for (i = 0; i < 6; ++i)
1824                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1825
1826         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1827         if (!err) {
1828                 u32 low, high;
1829
1830                 value &= ~(1ULL << 2);
1831                 low    = lower_32_bits(value);
1832                 high   = upper_32_bits(value);
1833
1834                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1835         }
1836
1837         /* Flush tlb to evict multi-match entries */
1838         __flush_tlb_all();
1839
1840         return true;
1841 }
1842
1843 /*
1844  * Trigger machine check on the host. We assume all the MSRs are already set up
1845  * by the CPU and that we still run on the same CPU as the MCE occurred on.
1846  * We pass a fake environment to the machine check handler because we want
1847  * the guest to be always treated like user space, no matter what context
1848  * it used internally.
1849  */
1850 static void kvm_machine_check(void)
1851 {
1852 #if defined(CONFIG_X86_MCE)
1853         struct pt_regs regs = {
1854                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1855                 .flags = X86_EFLAGS_IF,
1856         };
1857
1858         do_machine_check(&regs, 0);
1859 #endif
1860 }
1861
1862 static void svm_handle_mce(struct vcpu_svm *svm)
1863 {
1864         if (is_erratum_383()) {
1865                 /*
1866                  * Erratum 383 triggered. Guest state is corrupt so kill the
1867                  * guest.
1868                  */
1869                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1870
1871                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1872
1873                 return;
1874         }
1875
1876         /*
1877          * On an #MC intercept the MCE handler is not called automatically in
1878          * the host. So do it by hand here.
1879          */
1880         kvm_machine_check();
1881 }
1882
1883 static int mc_interception(struct vcpu_svm *svm)
1884 {
1885         return 1;
1886 }
1887
1888 static int shutdown_interception(struct vcpu_svm *svm)
1889 {
1890         struct kvm_run *kvm_run = svm->vcpu.run;
1891
1892         /*
1893          * VMCB is undefined after a SHUTDOWN intercept
1894          * so reinitialize it.
1895          */
1896         clear_page(svm->vmcb);
1897         init_vmcb(svm);
1898
1899         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1900         return 0;
1901 }
1902
1903 static int io_interception(struct vcpu_svm *svm)
1904 {
1905         struct kvm_vcpu *vcpu = &svm->vcpu;
1906         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1907         int size, in, string;
1908         unsigned port;
1909
1910         ++svm->vcpu.stat.io_exits;
1911         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1912         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1913         if (string)
1914                 return kvm_emulate_instruction(vcpu, 0);
1915
1916         port = io_info >> 16;
1917         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1918         svm->next_rip = svm->vmcb->control.exit_info_2;
1919
1920         return kvm_fast_pio(&svm->vcpu, size, port, in);
1921 }
1922
1923 static int nmi_interception(struct vcpu_svm *svm)
1924 {
1925         return 1;
1926 }
1927
1928 static int intr_interception(struct vcpu_svm *svm)
1929 {
1930         ++svm->vcpu.stat.irq_exits;
1931         return 1;
1932 }
1933
1934 static int nop_on_interception(struct vcpu_svm *svm)
1935 {
1936         return 1;
1937 }
1938
1939 static int halt_interception(struct vcpu_svm *svm)
1940 {
1941         return kvm_emulate_halt(&svm->vcpu);
1942 }
1943
1944 static int vmmcall_interception(struct vcpu_svm *svm)
1945 {
1946         return kvm_emulate_hypercall(&svm->vcpu);
1947 }
1948
1949 static int vmload_interception(struct vcpu_svm *svm)
1950 {
1951         struct vmcb *nested_vmcb;
1952         struct kvm_host_map map;
1953         int ret;
1954
1955         if (nested_svm_check_permissions(svm))
1956                 return 1;
1957
1958         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1959         if (ret) {
1960                 if (ret == -EINVAL)
1961                         kvm_inject_gp(&svm->vcpu, 0);
1962                 return 1;
1963         }
1964
1965         nested_vmcb = map.hva;
1966
1967         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1968
1969         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1970         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1971
1972         return ret;
1973 }
1974
1975 static int vmsave_interception(struct vcpu_svm *svm)
1976 {
1977         struct vmcb *nested_vmcb;
1978         struct kvm_host_map map;
1979         int ret;
1980
1981         if (nested_svm_check_permissions(svm))
1982                 return 1;
1983
1984         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1985         if (ret) {
1986                 if (ret == -EINVAL)
1987                         kvm_inject_gp(&svm->vcpu, 0);
1988                 return 1;
1989         }
1990
1991         nested_vmcb = map.hva;
1992
1993         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1994
1995         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1996         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1997
1998         return ret;
1999 }
2000
2001 static int vmrun_interception(struct vcpu_svm *svm)
2002 {
2003         if (nested_svm_check_permissions(svm))
2004                 return 1;
2005
2006         return nested_svm_vmrun(svm);
2007 }
2008
2009 static int stgi_interception(struct vcpu_svm *svm)
2010 {
2011         int ret;
2012
2013         if (nested_svm_check_permissions(svm))
2014                 return 1;
2015
2016         /*
2017          * If VGIF is enabled, the STGI intercept is only added to
2018          * detect the opening of the SMI/NMI window; remove it now.
2019          */
2020         if (vgif_enabled(svm))
2021                 clr_intercept(svm, INTERCEPT_STGI);
2022
2023         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2024         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2025
2026         enable_gif(svm);
2027
2028         return ret;
2029 }
2030
2031 static int clgi_interception(struct vcpu_svm *svm)
2032 {
2033         int ret;
2034
2035         if (nested_svm_check_permissions(svm))
2036                 return 1;
2037
2038         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2039
2040         disable_gif(svm);
2041
2042         /* After a CLGI no interrupts should come */
2043         if (!kvm_vcpu_apicv_active(&svm->vcpu))
2044                 svm_clear_vintr(svm);
2045
2046         return ret;
2047 }
2048
2049 static int invlpga_interception(struct vcpu_svm *svm)
2050 {
2051         struct kvm_vcpu *vcpu = &svm->vcpu;
2052
2053         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2054                           kvm_rax_read(&svm->vcpu));
2055
2056         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2057         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2058
2059         return kvm_skip_emulated_instruction(&svm->vcpu);
2060 }
2061
2062 static int skinit_interception(struct vcpu_svm *svm)
2063 {
2064         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2065
2066         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2067         return 1;
2068 }
2069
2070 static int wbinvd_interception(struct vcpu_svm *svm)
2071 {
2072         return kvm_emulate_wbinvd(&svm->vcpu);
2073 }
2074
2075 static int xsetbv_interception(struct vcpu_svm *svm)
2076 {
2077         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2078         u32 index = kvm_rcx_read(&svm->vcpu);
2079
2080         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2081                 return kvm_skip_emulated_instruction(&svm->vcpu);
2082         }
2083
2084         return 1;
2085 }
2086
2087 static int rdpru_interception(struct vcpu_svm *svm)
2088 {
2089         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2090         return 1;
2091 }
2092
2093 static int task_switch_interception(struct vcpu_svm *svm)
2094 {
2095         u16 tss_selector;
2096         int reason;
2097         int int_type = svm->vmcb->control.exit_int_info &
2098                 SVM_EXITINTINFO_TYPE_MASK;
2099         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2100         uint32_t type =
2101                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2102         uint32_t idt_v =
2103                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2104         bool has_error_code = false;
2105         u32 error_code = 0;
2106
2107         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2108
2109         if (svm->vmcb->control.exit_info_2 &
2110             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2111                 reason = TASK_SWITCH_IRET;
2112         else if (svm->vmcb->control.exit_info_2 &
2113                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2114                 reason = TASK_SWITCH_JMP;
2115         else if (idt_v)
2116                 reason = TASK_SWITCH_GATE;
2117         else
2118                 reason = TASK_SWITCH_CALL;
2119
2120         if (reason == TASK_SWITCH_GATE) {
2121                 switch (type) {
2122                 case SVM_EXITINTINFO_TYPE_NMI:
2123                         svm->vcpu.arch.nmi_injected = false;
2124                         break;
2125                 case SVM_EXITINTINFO_TYPE_EXEPT:
2126                         if (svm->vmcb->control.exit_info_2 &
2127                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2128                                 has_error_code = true;
2129                                 error_code =
2130                                         (u32)svm->vmcb->control.exit_info_2;
2131                         }
2132                         kvm_clear_exception_queue(&svm->vcpu);
2133                         break;
2134                 case SVM_EXITINTINFO_TYPE_INTR:
2135                         kvm_clear_interrupt_queue(&svm->vcpu);
2136                         break;
2137                 default:
2138                         break;
2139                 }
2140         }
2141
2142         if (reason != TASK_SWITCH_GATE ||
2143             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2144             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2145              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2146                 if (!skip_emulated_instruction(&svm->vcpu))
2147                         return 0;
2148         }
2149
2150         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2151                 int_vec = -1;
2152
2153         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2154                                has_error_code, error_code);
2155 }
2156
2157 static int cpuid_interception(struct vcpu_svm *svm)
2158 {
2159         return kvm_emulate_cpuid(&svm->vcpu);
2160 }
2161
2162 static int iret_interception(struct vcpu_svm *svm)
2163 {
2164         ++svm->vcpu.stat.nmi_window_exits;
2165         clr_intercept(svm, INTERCEPT_IRET);
2166         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2167         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2168         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2169         return 1;
2170 }
2171
2172 static int invlpg_interception(struct vcpu_svm *svm)
2173 {
2174         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2175                 return kvm_emulate_instruction(&svm->vcpu, 0);
2176
2177         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2178         return kvm_skip_emulated_instruction(&svm->vcpu);
2179 }
2180
2181 static int emulate_on_interception(struct vcpu_svm *svm)
2182 {
2183         return kvm_emulate_instruction(&svm->vcpu, 0);
2184 }
2185
2186 static int rsm_interception(struct vcpu_svm *svm)
2187 {
2188         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2189 }
2190
2191 static int rdpmc_interception(struct vcpu_svm *svm)
2192 {
2193         int err;
2194
2195         if (!nrips)
2196                 return emulate_on_interception(svm);
2197
2198         err = kvm_rdpmc(&svm->vcpu);
2199         return kvm_complete_insn_gp(&svm->vcpu, err);
2200 }
2201
2202 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2203                                             unsigned long val)
2204 {
2205         unsigned long cr0 = svm->vcpu.arch.cr0;
2206         bool ret = false;
2207         u64 intercept;
2208
2209         intercept = svm->nested.intercept;
2210
2211         if (!is_guest_mode(&svm->vcpu) ||
2212             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2213                 return false;
2214
2215         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2216         val &= ~SVM_CR0_SELECTIVE_MASK;
2217
2218         if (cr0 ^ val) {
2219                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2220                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2221         }
2222
2223         return ret;
2224 }
2225
2226 #define CR_VALID (1ULL << 63)
2227
2228 static int cr_interception(struct vcpu_svm *svm)
2229 {
2230         int reg, cr;
2231         unsigned long val;
2232         int err;
2233
2234         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2235                 return emulate_on_interception(svm);
2236
2237         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2238                 return emulate_on_interception(svm);
2239
2240         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2241         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2242                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2243         else
2244                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2245
2246         err = 0;
2247         if (cr >= 16) { /* mov to cr */
2248                 cr -= 16;
2249                 val = kvm_register_read(&svm->vcpu, reg);
2250                 switch (cr) {
2251                 case 0:
2252                         if (!check_selective_cr0_intercepted(svm, val))
2253                                 err = kvm_set_cr0(&svm->vcpu, val);
2254                         else
2255                                 return 1;
2256
2257                         break;
2258                 case 3:
2259                         err = kvm_set_cr3(&svm->vcpu, val);
2260                         break;
2261                 case 4:
2262                         err = kvm_set_cr4(&svm->vcpu, val);
2263                         break;
2264                 case 8:
2265                         err = kvm_set_cr8(&svm->vcpu, val);
2266                         break;
2267                 default:
2268                         WARN(1, "unhandled write to CR%d", cr);
2269                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2270                         return 1;
2271                 }
2272         } else { /* mov from cr */
2273                 switch (cr) {
2274                 case 0:
2275                         val = kvm_read_cr0(&svm->vcpu);
2276                         break;
2277                 case 2:
2278                         val = svm->vcpu.arch.cr2;
2279                         break;
2280                 case 3:
2281                         val = kvm_read_cr3(&svm->vcpu);
2282                         break;
2283                 case 4:
2284                         val = kvm_read_cr4(&svm->vcpu);
2285                         break;
2286                 case 8:
2287                         val = kvm_get_cr8(&svm->vcpu);
2288                         break;
2289                 default:
2290                         WARN(1, "unhandled read from CR%d", cr);
2291                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2292                         return 1;
2293                 }
2294                 kvm_register_write(&svm->vcpu, reg, val);
2295         }
2296         return kvm_complete_insn_gp(&svm->vcpu, err);
2297 }
2298
2299 static int dr_interception(struct vcpu_svm *svm)
2300 {
2301         int reg, dr;
2302         unsigned long val;
2303
2304         if (svm->vcpu.guest_debug == 0) {
2305                 /*
2306                  * No more DR vmexits; force a reload of the debug registers
2307                  * and reenter on this instruction.  The next vmexit will
2308                  * retrieve the full state of the debug registers.
2309                  */
2310                 clr_dr_intercepts(svm);
2311                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2312                 return 1;
2313         }
2314
2315         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2316                 return emulate_on_interception(svm);
2317
2318         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2319         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2320
2321         if (dr >= 16) { /* mov to DRn */
2322                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2323                         return 1;
2324                 val = kvm_register_read(&svm->vcpu, reg);
2325                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2326         } else {
2327                 if (!kvm_require_dr(&svm->vcpu, dr))
2328                         return 1;
2329                 kvm_get_dr(&svm->vcpu, dr, &val);
2330                 kvm_register_write(&svm->vcpu, reg, val);
2331         }
2332
2333         return kvm_skip_emulated_instruction(&svm->vcpu);
2334 }
2335
2336 static int cr8_write_interception(struct vcpu_svm *svm)
2337 {
2338         struct kvm_run *kvm_run = svm->vcpu.run;
2339         int r;
2340
2341         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2342         /* instruction emulation calls kvm_set_cr8() */
2343         r = cr_interception(svm);
2344         if (lapic_in_kernel(&svm->vcpu))
2345                 return r;
2346         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2347                 return r;
2348         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2349         return 0;
2350 }
2351
2352 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2353 {
2354         msr->data = 0;
2355
2356         switch (msr->index) {
2357         case MSR_F10H_DECFG:
2358                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2359                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2360                 break;
2361         default:
2362                 return 1;
2363         }
2364
2365         return 0;
2366 }
2367
2368 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2369 {
2370         struct vcpu_svm *svm = to_svm(vcpu);
2371
2372         switch (msr_info->index) {
2373         case MSR_STAR:
2374                 msr_info->data = svm->vmcb->save.star;
2375                 break;
2376 #ifdef CONFIG_X86_64
2377         case MSR_LSTAR:
2378                 msr_info->data = svm->vmcb->save.lstar;
2379                 break;
2380         case MSR_CSTAR:
2381                 msr_info->data = svm->vmcb->save.cstar;
2382                 break;
2383         case MSR_KERNEL_GS_BASE:
2384                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2385                 break;
2386         case MSR_SYSCALL_MASK:
2387                 msr_info->data = svm->vmcb->save.sfmask;
2388                 break;
2389 #endif
2390         case MSR_IA32_SYSENTER_CS:
2391                 msr_info->data = svm->vmcb->save.sysenter_cs;
2392                 break;
2393         case MSR_IA32_SYSENTER_EIP:
2394                 msr_info->data = svm->sysenter_eip;
2395                 break;
2396         case MSR_IA32_SYSENTER_ESP:
2397                 msr_info->data = svm->sysenter_esp;
2398                 break;
2399         case MSR_TSC_AUX:
2400                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2401                         return 1;
2402                 msr_info->data = svm->tsc_aux;
2403                 break;
2404         /*
2405          * Nobody will change the following 5 values in the VMCB so we can
2406          * safely return them on rdmsr. They will always be 0 until LBRV is
2407          * implemented.
2408          */
2409         case MSR_IA32_DEBUGCTLMSR:
2410                 msr_info->data = svm->vmcb->save.dbgctl;
2411                 break;
2412         case MSR_IA32_LASTBRANCHFROMIP:
2413                 msr_info->data = svm->vmcb->save.br_from;
2414                 break;
2415         case MSR_IA32_LASTBRANCHTOIP:
2416                 msr_info->data = svm->vmcb->save.br_to;
2417                 break;
2418         case MSR_IA32_LASTINTFROMIP:
2419                 msr_info->data = svm->vmcb->save.last_excp_from;
2420                 break;
2421         case MSR_IA32_LASTINTTOIP:
2422                 msr_info->data = svm->vmcb->save.last_excp_to;
2423                 break;
2424         case MSR_VM_HSAVE_PA:
2425                 msr_info->data = svm->nested.hsave_msr;
2426                 break;
2427         case MSR_VM_CR:
2428                 msr_info->data = svm->nested.vm_cr_msr;
2429                 break;
2430         case MSR_IA32_SPEC_CTRL:
2431                 if (!msr_info->host_initiated &&
2432                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2433                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2434                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2435                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2436                         return 1;
2437
2438                 msr_info->data = svm->spec_ctrl;
2439                 break;
2440         case MSR_AMD64_VIRT_SPEC_CTRL:
2441                 if (!msr_info->host_initiated &&
2442                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2443                         return 1;
2444
2445                 msr_info->data = svm->virt_spec_ctrl;
2446                 break;
2447         case MSR_F15H_IC_CFG: {
2448
2449                 int family, model;
2450
2451                 family = guest_cpuid_family(vcpu);
2452                 model  = guest_cpuid_model(vcpu);
2453
2454                 if (family < 0 || model < 0)
2455                         return kvm_get_msr_common(vcpu, msr_info);
2456
2457                 msr_info->data = 0;
2458
2459                 if (family == 0x15 &&
2460                     (model >= 0x2 && model < 0x20))
2461                         msr_info->data = 0x1E;
2462                 }
2463                 break;
2464         case MSR_F10H_DECFG:
2465                 msr_info->data = svm->msr_decfg;
2466                 break;
2467         default:
2468                 return kvm_get_msr_common(vcpu, msr_info);
2469         }
2470         return 0;
2471 }
2472
2473 static int rdmsr_interception(struct vcpu_svm *svm)
2474 {
2475         return kvm_emulate_rdmsr(&svm->vcpu);
2476 }
2477
2478 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2479 {
2480         struct vcpu_svm *svm = to_svm(vcpu);
2481         int svm_dis, chg_mask;
2482
2483         if (data & ~SVM_VM_CR_VALID_MASK)
2484                 return 1;
2485
2486         chg_mask = SVM_VM_CR_VALID_MASK;
2487
2488         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2489                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2490
2491         svm->nested.vm_cr_msr &= ~chg_mask;
2492         svm->nested.vm_cr_msr |= (data & chg_mask);
2493
2494         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2495
2496         /* check for svm_disable while efer.svme is set */
2497         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2498                 return 1;
2499
2500         return 0;
2501 }
2502
2503 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2504 {
2505         struct vcpu_svm *svm = to_svm(vcpu);
2506
2507         u32 ecx = msr->index;
2508         u64 data = msr->data;
2509         switch (ecx) {
2510         case MSR_IA32_CR_PAT:
2511                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2512                         return 1;
2513                 vcpu->arch.pat = data;
2514                 svm->vmcb->save.g_pat = data;
2515                 mark_dirty(svm->vmcb, VMCB_NPT);
2516                 break;
2517         case MSR_IA32_SPEC_CTRL:
2518                 if (!msr->host_initiated &&
2519                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2520                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2521                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2522                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2523                         return 1;
2524
2525                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2526                         return 1;
2527
2528                 svm->spec_ctrl = data;
2529                 if (!data)
2530                         break;
2531
2532                 /*
2533                  * For non-nested:
2534                  * When it's written (to non-zero) for the first time, pass
2535                  * it through.
2536                  *
2537                  * For nested:
2538                  * The handling of the MSR bitmap for L2 guests is done in
2539                  * nested_svm_vmrun_msrpm.
2540                  * We update the L1 MSR bit as well since it will end up
2541                  * touching the MSR anyway now.
2542                  */
2543                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2544                 break;
2545         case MSR_IA32_PRED_CMD:
2546                 if (!msr->host_initiated &&
2547                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2548                         return 1;
2549
2550                 if (data & ~PRED_CMD_IBPB)
2551                         return 1;
2552                 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2553                         return 1;
2554                 if (!data)
2555                         break;
2556
2557                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2558                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2559                 break;
2560         case MSR_AMD64_VIRT_SPEC_CTRL:
2561                 if (!msr->host_initiated &&
2562                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2563                         return 1;
2564
2565                 if (data & ~SPEC_CTRL_SSBD)
2566                         return 1;
2567
2568                 svm->virt_spec_ctrl = data;
2569                 break;
2570         case MSR_STAR:
2571                 svm->vmcb->save.star = data;
2572                 break;
2573 #ifdef CONFIG_X86_64
2574         case MSR_LSTAR:
2575                 svm->vmcb->save.lstar = data;
2576                 break;
2577         case MSR_CSTAR:
2578                 svm->vmcb->save.cstar = data;
2579                 break;
2580         case MSR_KERNEL_GS_BASE:
2581                 svm->vmcb->save.kernel_gs_base = data;
2582                 break;
2583         case MSR_SYSCALL_MASK:
2584                 svm->vmcb->save.sfmask = data;
2585                 break;
2586 #endif
2587         case MSR_IA32_SYSENTER_CS:
2588                 svm->vmcb->save.sysenter_cs = data;
2589                 break;
2590         case MSR_IA32_SYSENTER_EIP:
2591                 svm->sysenter_eip = data;
2592                 svm->vmcb->save.sysenter_eip = data;
2593                 break;
2594         case MSR_IA32_SYSENTER_ESP:
2595                 svm->sysenter_esp = data;
2596                 svm->vmcb->save.sysenter_esp = data;
2597                 break;
2598         case MSR_TSC_AUX:
2599                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2600                         return 1;
2601
2602                 /*
2603                  * This is rare, so we update the MSR here instead of using
2604                  * direct_access_msrs.  Doing that would require a rdmsr in
2605                  * svm_vcpu_put.
2606                  */
2607                 svm->tsc_aux = data;
2608                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2609                 break;
2610         case MSR_IA32_DEBUGCTLMSR:
2611                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2612                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2613                                     __func__, data);
2614                         break;
2615                 }
2616                 if (data & DEBUGCTL_RESERVED_BITS)
2617                         return 1;
2618
2619                 svm->vmcb->save.dbgctl = data;
2620                 mark_dirty(svm->vmcb, VMCB_LBR);
2621                 if (data & (1ULL<<0))
2622                         svm_enable_lbrv(svm);
2623                 else
2624                         svm_disable_lbrv(svm);
2625                 break;
2626         case MSR_VM_HSAVE_PA:
2627                 svm->nested.hsave_msr = data;
2628                 break;
2629         case MSR_VM_CR:
2630                 return svm_set_vm_cr(vcpu, data);
2631         case MSR_VM_IGNNE:
2632                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2633                 break;
2634         case MSR_F10H_DECFG: {
2635                 struct kvm_msr_entry msr_entry;
2636
2637                 msr_entry.index = msr->index;
2638                 if (svm_get_msr_feature(&msr_entry))
2639                         return 1;
2640
2641                 /* Check the supported bits */
2642                 if (data & ~msr_entry.data)
2643                         return 1;
2644
2645                 /* Don't allow the guest to change a bit, #GP */
2646                 if (!msr->host_initiated && (data ^ msr_entry.data))
2647                         return 1;
2648
2649                 svm->msr_decfg = data;
2650                 break;
2651         }
2652         case MSR_IA32_APICBASE:
2653                 if (kvm_vcpu_apicv_active(vcpu))
2654                         avic_update_vapic_bar(to_svm(vcpu), data);
2655                 /* Fall through */
2656         default:
2657                 return kvm_set_msr_common(vcpu, msr);
2658         }
2659         return 0;
2660 }
2661
2662 static int wrmsr_interception(struct vcpu_svm *svm)
2663 {
2664         return kvm_emulate_wrmsr(&svm->vcpu);
2665 }
2666
2667 static int msr_interception(struct vcpu_svm *svm)
2668 {
2669         if (svm->vmcb->control.exit_info_1)
2670                 return wrmsr_interception(svm);
2671         else
2672                 return rdmsr_interception(svm);
2673 }
2674
2675 static int interrupt_window_interception(struct vcpu_svm *svm)
2676 {
2677         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2678         svm_clear_vintr(svm);
2679
2680         /*
2681          * For AVIC, the only reason to end up here is ExtINTs.
2682          * In this case AVIC was temporarily disabled for
2683          * requesting the IRQ window and we have to re-enable it.
2684          */
2685         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2686
2687         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2688         mark_dirty(svm->vmcb, VMCB_INTR);
2689         ++svm->vcpu.stat.irq_window_exits;
2690         return 1;
2691 }
2692
2693 static int pause_interception(struct vcpu_svm *svm)
2694 {
2695         struct kvm_vcpu *vcpu = &svm->vcpu;
2696         bool in_kernel = (svm_get_cpl(vcpu) == 0);
2697
2698         if (pause_filter_thresh)
2699                 grow_ple_window(vcpu);
2700
2701         kvm_vcpu_on_spin(vcpu, in_kernel);
2702         return 1;
2703 }
2704
2705 static int nop_interception(struct vcpu_svm *svm)
2706 {
2707         return kvm_skip_emulated_instruction(&(svm->vcpu));
2708 }
2709
2710 static int monitor_interception(struct vcpu_svm *svm)
2711 {
2712         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2713         return nop_interception(svm);
2714 }
2715
2716 static int mwait_interception(struct vcpu_svm *svm)
2717 {
2718         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2719         return nop_interception(svm);
2720 }
2721
2722 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2723         [SVM_EXIT_READ_CR0]                     = cr_interception,
2724         [SVM_EXIT_READ_CR3]                     = cr_interception,
2725         [SVM_EXIT_READ_CR4]                     = cr_interception,
2726         [SVM_EXIT_READ_CR8]                     = cr_interception,
2727         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2728         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2729         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2730         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2731         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2732         [SVM_EXIT_READ_DR0]                     = dr_interception,
2733         [SVM_EXIT_READ_DR1]                     = dr_interception,
2734         [SVM_EXIT_READ_DR2]                     = dr_interception,
2735         [SVM_EXIT_READ_DR3]                     = dr_interception,
2736         [SVM_EXIT_READ_DR4]                     = dr_interception,
2737         [SVM_EXIT_READ_DR5]                     = dr_interception,
2738         [SVM_EXIT_READ_DR6]                     = dr_interception,
2739         [SVM_EXIT_READ_DR7]                     = dr_interception,
2740         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2741         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2742         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2743         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2744         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2745         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2746         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2747         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2748         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2749         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2750         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2751         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2752         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2753         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2754         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2755         [SVM_EXIT_INTR]                         = intr_interception,
2756         [SVM_EXIT_NMI]                          = nmi_interception,
2757         [SVM_EXIT_SMI]                          = nop_on_interception,
2758         [SVM_EXIT_INIT]                         = nop_on_interception,
2759         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2760         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
2761         [SVM_EXIT_CPUID]                        = cpuid_interception,
2762         [SVM_EXIT_IRET]                         = iret_interception,
2763         [SVM_EXIT_INVD]                         = emulate_on_interception,
2764         [SVM_EXIT_PAUSE]                        = pause_interception,
2765         [SVM_EXIT_HLT]                          = halt_interception,
2766         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2767         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2768         [SVM_EXIT_IOIO]                         = io_interception,
2769         [SVM_EXIT_MSR]                          = msr_interception,
2770         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2771         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2772         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2773         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2774         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2775         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2776         [SVM_EXIT_STGI]                         = stgi_interception,
2777         [SVM_EXIT_CLGI]                         = clgi_interception,
2778         [SVM_EXIT_SKINIT]                       = skinit_interception,
2779         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
2780         [SVM_EXIT_MONITOR]                      = monitor_interception,
2781         [SVM_EXIT_MWAIT]                        = mwait_interception,
2782         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2783         [SVM_EXIT_RDPRU]                        = rdpru_interception,
2784         [SVM_EXIT_NPF]                          = npf_interception,
2785         [SVM_EXIT_RSM]                          = rsm_interception,
2786         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
2787         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
2788 };
2789
2790 static void dump_vmcb(struct kvm_vcpu *vcpu)
2791 {
2792         struct vcpu_svm *svm = to_svm(vcpu);
2793         struct vmcb_control_area *control = &svm->vmcb->control;
2794         struct vmcb_save_area *save = &svm->vmcb->save;
2795
2796         if (!dump_invalid_vmcb) {
2797                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2798                 return;
2799         }
2800
2801         pr_err("VMCB Control Area:\n");
2802         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2803         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2804         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2805         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2806         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2807         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2808         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2809         pr_err("%-20s%d\n", "pause filter threshold:",
2810                control->pause_filter_thresh);
2811         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2812         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2813         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2814         pr_err("%-20s%d\n", "asid:", control->asid);
2815         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2816         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2817         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2818         pr_err("%-20s%08x\n", "int_state:", control->int_state);
2819         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2820         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2821         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2822         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2823         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2824         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2825         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2826         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2827         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2828         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2829         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2830         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2831         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2832         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2833         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2834         pr_err("VMCB State Save Area:\n");
2835         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2836                "es:",
2837                save->es.selector, save->es.attrib,
2838                save->es.limit, save->es.base);
2839         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2840                "cs:",
2841                save->cs.selector, save->cs.attrib,
2842                save->cs.limit, save->cs.base);
2843         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2844                "ss:",
2845                save->ss.selector, save->ss.attrib,
2846                save->ss.limit, save->ss.base);
2847         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2848                "ds:",
2849                save->ds.selector, save->ds.attrib,
2850                save->ds.limit, save->ds.base);
2851         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2852                "fs:",
2853                save->fs.selector, save->fs.attrib,
2854                save->fs.limit, save->fs.base);
2855         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2856                "gs:",
2857                save->gs.selector, save->gs.attrib,
2858                save->gs.limit, save->gs.base);
2859         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2860                "gdtr:",
2861                save->gdtr.selector, save->gdtr.attrib,
2862                save->gdtr.limit, save->gdtr.base);
2863         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2864                "ldtr:",
2865                save->ldtr.selector, save->ldtr.attrib,
2866                save->ldtr.limit, save->ldtr.base);
2867         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2868                "idtr:",
2869                save->idtr.selector, save->idtr.attrib,
2870                save->idtr.limit, save->idtr.base);
2871         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2872                "tr:",
2873                save->tr.selector, save->tr.attrib,
2874                save->tr.limit, save->tr.base);
2875         pr_err("cpl:            %d                efer:         %016llx\n",
2876                 save->cpl, save->efer);
2877         pr_err("%-15s %016llx %-13s %016llx\n",
2878                "cr0:", save->cr0, "cr2:", save->cr2);
2879         pr_err("%-15s %016llx %-13s %016llx\n",
2880                "cr3:", save->cr3, "cr4:", save->cr4);
2881         pr_err("%-15s %016llx %-13s %016llx\n",
2882                "dr6:", save->dr6, "dr7:", save->dr7);
2883         pr_err("%-15s %016llx %-13s %016llx\n",
2884                "rip:", save->rip, "rflags:", save->rflags);
2885         pr_err("%-15s %016llx %-13s %016llx\n",
2886                "rsp:", save->rsp, "rax:", save->rax);
2887         pr_err("%-15s %016llx %-13s %016llx\n",
2888                "star:", save->star, "lstar:", save->lstar);
2889         pr_err("%-15s %016llx %-13s %016llx\n",
2890                "cstar:", save->cstar, "sfmask:", save->sfmask);
2891         pr_err("%-15s %016llx %-13s %016llx\n",
2892                "kernel_gs_base:", save->kernel_gs_base,
2893                "sysenter_cs:", save->sysenter_cs);
2894         pr_err("%-15s %016llx %-13s %016llx\n",
2895                "sysenter_esp:", save->sysenter_esp,
2896                "sysenter_eip:", save->sysenter_eip);
2897         pr_err("%-15s %016llx %-13s %016llx\n",
2898                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2899         pr_err("%-15s %016llx %-13s %016llx\n",
2900                "br_from:", save->br_from, "br_to:", save->br_to);
2901         pr_err("%-15s %016llx %-13s %016llx\n",
2902                "excp_from:", save->last_excp_from,
2903                "excp_to:", save->last_excp_to);
2904 }
2905
2906 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2907 {
2908         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2909
2910         *info1 = control->exit_info_1;
2911         *info2 = control->exit_info_2;
2912 }
2913
2914 static int handle_exit(struct kvm_vcpu *vcpu,
2915         enum exit_fastpath_completion exit_fastpath)
2916 {
2917         struct vcpu_svm *svm = to_svm(vcpu);
2918         struct kvm_run *kvm_run = vcpu->run;
2919         u32 exit_code = svm->vmcb->control.exit_code;
2920
2921         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2922
2923         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2924                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2925         if (npt_enabled)
2926                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2927
2928         if (unlikely(svm->nested.exit_required)) {
2929                 nested_svm_vmexit(svm);
2930                 svm->nested.exit_required = false;
2931
2932                 return 1;
2933         }
2934
2935         if (is_guest_mode(vcpu)) {
2936                 int vmexit;
2937
2938                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2939                                         svm->vmcb->control.exit_info_1,
2940                                         svm->vmcb->control.exit_info_2,
2941                                         svm->vmcb->control.exit_int_info,
2942                                         svm->vmcb->control.exit_int_info_err,
2943                                         KVM_ISA_SVM);
2944
2945                 vmexit = nested_svm_exit_special(svm);
2946
2947                 if (vmexit == NESTED_EXIT_CONTINUE)
2948                         vmexit = nested_svm_exit_handled(svm);
2949
2950                 if (vmexit == NESTED_EXIT_DONE)
2951                         return 1;
2952         }
2953
2954         svm_complete_interrupts(svm);
2955
2956         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2957                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2958                 kvm_run->fail_entry.hardware_entry_failure_reason
2959                         = svm->vmcb->control.exit_code;
2960                 dump_vmcb(vcpu);
2961                 return 0;
2962         }
2963
2964         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2965             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2966             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2967             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2968                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
2969                        "exit_code 0x%x\n",
2970                        __func__, svm->vmcb->control.exit_int_info,
2971                        exit_code);
2972
2973         if (exit_fastpath == EXIT_FASTPATH_SKIP_EMUL_INS) {
2974                 kvm_skip_emulated_instruction(vcpu);
2975                 return 1;
2976         } else if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2977             || !svm_exit_handlers[exit_code]) {
2978                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2979                 dump_vmcb(vcpu);
2980                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2981                 vcpu->run->internal.suberror =
2982                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2983                 vcpu->run->internal.ndata = 1;
2984                 vcpu->run->internal.data[0] = exit_code;
2985                 return 0;
2986         }
2987
2988 #ifdef CONFIG_RETPOLINE
2989         if (exit_code == SVM_EXIT_MSR)
2990                 return msr_interception(svm);
2991         else if (exit_code == SVM_EXIT_VINTR)
2992                 return interrupt_window_interception(svm);
2993         else if (exit_code == SVM_EXIT_INTR)
2994                 return intr_interception(svm);
2995         else if (exit_code == SVM_EXIT_HLT)
2996                 return halt_interception(svm);
2997         else if (exit_code == SVM_EXIT_NPF)
2998                 return npf_interception(svm);
2999 #endif
3000         return svm_exit_handlers[exit_code](svm);
3001 }
3002
3003 static void reload_tss(struct kvm_vcpu *vcpu)
3004 {
3005         int cpu = raw_smp_processor_id();
3006
3007         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3008         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3009         load_TR_desc();
3010 }
3011
3012 static void pre_svm_run(struct vcpu_svm *svm)
3013 {
3014         int cpu = raw_smp_processor_id();
3015
3016         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3017
3018         if (sev_guest(svm->vcpu.kvm))
3019                 return pre_sev_run(svm, cpu);
3020
3021         /* FIXME: handle wraparound of asid_generation */
3022         if (svm->asid_generation != sd->asid_generation)
3023                 new_asid(svm, sd);
3024 }
3025
3026 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3027 {
3028         struct vcpu_svm *svm = to_svm(vcpu);
3029
3030         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3031         vcpu->arch.hflags |= HF_NMI_MASK;
3032         set_intercept(svm, INTERCEPT_IRET);
3033         ++vcpu->stat.nmi_injections;
3034 }
3035
3036 static void svm_set_irq(struct kvm_vcpu *vcpu)
3037 {
3038         struct vcpu_svm *svm = to_svm(vcpu);
3039
3040         BUG_ON(!(gif_set(svm)));
3041
3042         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3043         ++vcpu->stat.irq_injections;
3044
3045         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3046                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3047 }
3048
3049 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3050 {
3051         struct vcpu_svm *svm = to_svm(vcpu);
3052
3053         if (svm_nested_virtualize_tpr(vcpu))
3054                 return;
3055
3056         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3057
3058         if (irr == -1)
3059                 return;
3060
3061         if (tpr >= irr)
3062                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3063 }
3064
3065 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3066 {
3067         struct vcpu_svm *svm = to_svm(vcpu);
3068         struct vmcb *vmcb = svm->vmcb;
3069         int ret;
3070         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3071               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3072         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3073
3074         return ret;
3075 }
3076
3077 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3078 {
3079         struct vcpu_svm *svm = to_svm(vcpu);
3080
3081         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3082 }
3083
3084 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3085 {
3086         struct vcpu_svm *svm = to_svm(vcpu);
3087
3088         if (masked) {
3089                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3090                 set_intercept(svm, INTERCEPT_IRET);
3091         } else {
3092                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3093                 clr_intercept(svm, INTERCEPT_IRET);
3094         }
3095 }
3096
3097 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3098 {
3099         struct vcpu_svm *svm = to_svm(vcpu);
3100         struct vmcb *vmcb = svm->vmcb;
3101
3102         if (!gif_set(svm) ||
3103              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3104                 return 0;
3105
3106         if (is_guest_mode(vcpu) && (svm->vcpu.arch.hflags & HF_VINTR_MASK))
3107                 return !!(svm->vcpu.arch.hflags & HF_HIF_MASK);
3108         else
3109                 return !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
3110 }
3111
3112 static void enable_irq_window(struct kvm_vcpu *vcpu)
3113 {
3114         struct vcpu_svm *svm = to_svm(vcpu);
3115
3116         /*
3117          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3118          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3119          * get that intercept, this function will be called again though and
3120          * we'll get the vintr intercept. However, if the vGIF feature is
3121          * enabled, the STGI interception will not occur. Enable the irq
3122          * window under the assumption that the hardware will set the GIF.
3123          */
3124         if (vgif_enabled(svm) || gif_set(svm)) {
3125                 /*
3126                  * IRQ window is not needed when AVIC is enabled,
3127                  * unless we have pending ExtINT since it cannot be injected
3128                  * via AVIC. In such case, we need to temporarily disable AVIC,
3129                  * and fallback to injecting IRQ via V_IRQ.
3130                  */
3131                 svm_toggle_avic_for_irq_window(vcpu, false);
3132                 svm_set_vintr(svm);
3133         }
3134 }
3135
3136 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3137 {
3138         struct vcpu_svm *svm = to_svm(vcpu);
3139
3140         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3141             == HF_NMI_MASK)
3142                 return; /* IRET will cause a vm exit */
3143
3144         if (!gif_set(svm)) {
3145                 if (vgif_enabled(svm))
3146                         set_intercept(svm, INTERCEPT_STGI);
3147                 return; /* STGI will cause a vm exit */
3148         }
3149
3150         if (svm->nested.exit_required)
3151                 return; /* we're not going to run the guest yet */
3152
3153         /*
3154          * Something prevents NMI from been injected. Single step over possible
3155          * problem (IRET or exception injection or interrupt shadow)
3156          */
3157         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3158         svm->nmi_singlestep = true;
3159         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3160 }
3161
3162 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3163 {
3164         return 0;
3165 }
3166
3167 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3168 {
3169         return 0;
3170 }
3171
3172 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3173 {
3174         struct vcpu_svm *svm = to_svm(vcpu);
3175
3176         /*
3177          * Flush only the current ASID even if the TLB flush was invoked via
3178          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3179          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3180          * unconditionally does a TLB flush on both nested VM-Enter and nested
3181          * VM-Exit (via kvm_mmu_reset_context()).
3182          */
3183         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3184                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3185         else
3186                 svm->asid_generation--;
3187 }
3188
3189 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3190 {
3191         struct vcpu_svm *svm = to_svm(vcpu);
3192
3193         invlpga(gva, svm->vmcb->control.asid);
3194 }
3195
3196 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3197 {
3198 }
3199
3200 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3201 {
3202         struct vcpu_svm *svm = to_svm(vcpu);
3203
3204         if (svm_nested_virtualize_tpr(vcpu))
3205                 return;
3206
3207         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3208                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3209                 kvm_set_cr8(vcpu, cr8);
3210         }
3211 }
3212
3213 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3214 {
3215         struct vcpu_svm *svm = to_svm(vcpu);
3216         u64 cr8;
3217
3218         if (svm_nested_virtualize_tpr(vcpu) ||
3219             kvm_vcpu_apicv_active(vcpu))
3220                 return;
3221
3222         cr8 = kvm_get_cr8(vcpu);
3223         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3224         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3225 }
3226
3227 static void svm_complete_interrupts(struct vcpu_svm *svm)
3228 {
3229         u8 vector;
3230         int type;
3231         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3232         unsigned int3_injected = svm->int3_injected;
3233
3234         svm->int3_injected = 0;
3235
3236         /*
3237          * If we've made progress since setting HF_IRET_MASK, we've
3238          * executed an IRET and can allow NMI injection.
3239          */
3240         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3241             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3242                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3243                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3244         }
3245
3246         svm->vcpu.arch.nmi_injected = false;
3247         kvm_clear_exception_queue(&svm->vcpu);
3248         kvm_clear_interrupt_queue(&svm->vcpu);
3249
3250         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3251                 return;
3252
3253         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3254
3255         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3256         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3257
3258         switch (type) {
3259         case SVM_EXITINTINFO_TYPE_NMI:
3260                 svm->vcpu.arch.nmi_injected = true;
3261                 break;
3262         case SVM_EXITINTINFO_TYPE_EXEPT:
3263                 /*
3264                  * In case of software exceptions, do not reinject the vector,
3265                  * but re-execute the instruction instead. Rewind RIP first
3266                  * if we emulated INT3 before.
3267                  */
3268                 if (kvm_exception_is_soft(vector)) {
3269                         if (vector == BP_VECTOR && int3_injected &&
3270                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3271                                 kvm_rip_write(&svm->vcpu,
3272                                               kvm_rip_read(&svm->vcpu) -
3273                                               int3_injected);
3274                         break;
3275                 }
3276                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3277                         u32 err = svm->vmcb->control.exit_int_info_err;
3278                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3279
3280                 } else
3281                         kvm_requeue_exception(&svm->vcpu, vector);
3282                 break;
3283         case SVM_EXITINTINFO_TYPE_INTR:
3284                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3285                 break;
3286         default:
3287                 break;
3288         }
3289 }
3290
3291 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3292 {
3293         struct vcpu_svm *svm = to_svm(vcpu);
3294         struct vmcb_control_area *control = &svm->vmcb->control;
3295
3296         control->exit_int_info = control->event_inj;
3297         control->exit_int_info_err = control->event_inj_err;
3298         control->event_inj = 0;
3299         svm_complete_interrupts(svm);
3300 }
3301
3302 static enum exit_fastpath_completion svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3303 {
3304         if (!is_guest_mode(vcpu) &&
3305             to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3306             to_svm(vcpu)->vmcb->control.exit_info_1)
3307                 return handle_fastpath_set_msr_irqoff(vcpu);
3308
3309         return EXIT_FASTPATH_NONE;
3310 }
3311
3312 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3313
3314 static enum exit_fastpath_completion svm_vcpu_run(struct kvm_vcpu *vcpu)
3315 {
3316         enum exit_fastpath_completion exit_fastpath;
3317         struct vcpu_svm *svm = to_svm(vcpu);
3318
3319         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3320         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3321         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3322
3323         /*
3324          * A vmexit emulation is required before the vcpu can be executed
3325          * again.
3326          */
3327         if (unlikely(svm->nested.exit_required))
3328                 return EXIT_FASTPATH_NONE;
3329
3330         /*
3331          * Disable singlestep if we're injecting an interrupt/exception.
3332          * We don't want our modified rflags to be pushed on the stack where
3333          * we might not be able to easily reset them if we disabled NMI
3334          * singlestep later.
3335          */
3336         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3337                 /*
3338                  * Event injection happens before external interrupts cause a
3339                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3340                  * is enough to force an immediate vmexit.
3341                  */
3342                 disable_nmi_singlestep(svm);
3343                 smp_send_reschedule(vcpu->cpu);
3344         }
3345
3346         pre_svm_run(svm);
3347
3348         sync_lapic_to_cr8(vcpu);
3349
3350         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3351
3352         clgi();
3353         kvm_load_guest_xsave_state(vcpu);
3354
3355         if (lapic_in_kernel(vcpu) &&
3356                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3357                 kvm_wait_lapic_expire(vcpu);
3358
3359         /*
3360          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3361          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3362          * is no need to worry about the conditional branch over the wrmsr
3363          * being speculatively taken.
3364          */
3365         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3366
3367         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3368
3369 #ifdef CONFIG_X86_64
3370         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3371 #else
3372         loadsegment(fs, svm->host.fs);
3373 #ifndef CONFIG_X86_32_LAZY_GS
3374         loadsegment(gs, svm->host.gs);
3375 #endif
3376 #endif
3377
3378         /*
3379          * We do not use IBRS in the kernel. If this vCPU has used the
3380          * SPEC_CTRL MSR it may have left it on; save the value and
3381          * turn it off. This is much more efficient than blindly adding
3382          * it to the atomic save/restore list. Especially as the former
3383          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3384          *
3385          * For non-nested case:
3386          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3387          * save it.
3388          *
3389          * For nested case:
3390          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3391          * save it.
3392          */
3393         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3394                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3395
3396         reload_tss(vcpu);
3397
3398         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3399
3400         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3401         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3402         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3403         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3404
3405         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3406                 kvm_before_interrupt(&svm->vcpu);
3407
3408         kvm_load_host_xsave_state(vcpu);
3409         stgi();
3410
3411         /* Any pending NMI will happen here */
3412         exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3413
3414         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3415                 kvm_after_interrupt(&svm->vcpu);
3416
3417         sync_cr8_to_lapic(vcpu);
3418
3419         svm->next_rip = 0;
3420
3421         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3422
3423         /* if exit due to PF check for async PF */
3424         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3425                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
3426
3427         if (npt_enabled) {
3428                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3429                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3430         }
3431
3432         /*
3433          * We need to handle MC intercepts here before the vcpu has a chance to
3434          * change the physical cpu
3435          */
3436         if (unlikely(svm->vmcb->control.exit_code ==
3437                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3438                 svm_handle_mce(svm);
3439
3440         mark_all_clean(svm->vmcb);
3441         return exit_fastpath;
3442 }
3443
3444 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
3445 {
3446         struct vcpu_svm *svm = to_svm(vcpu);
3447         bool update_guest_cr3 = true;
3448         unsigned long cr3;
3449
3450         cr3 = __sme_set(root);
3451         if (npt_enabled) {
3452                 svm->vmcb->control.nested_cr3 = cr3;
3453                 mark_dirty(svm->vmcb, VMCB_NPT);
3454
3455                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3456                 if (is_guest_mode(vcpu))
3457                         update_guest_cr3 = false;
3458                 else if (test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3459                         cr3 = vcpu->arch.cr3;
3460                 else /* CR3 is already up-to-date.  */
3461                         update_guest_cr3 = false;
3462         }
3463
3464         if (update_guest_cr3) {
3465                 svm->vmcb->save.cr3 = cr3;
3466                 mark_dirty(svm->vmcb, VMCB_CR);
3467         }
3468 }
3469
3470 static int is_disabled(void)
3471 {
3472         u64 vm_cr;
3473
3474         rdmsrl(MSR_VM_CR, vm_cr);
3475         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3476                 return 1;
3477
3478         return 0;
3479 }
3480
3481 static void
3482 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3483 {
3484         /*
3485          * Patch in the VMMCALL instruction:
3486          */
3487         hypercall[0] = 0x0f;
3488         hypercall[1] = 0x01;
3489         hypercall[2] = 0xd9;
3490 }
3491
3492 static int __init svm_check_processor_compat(void)
3493 {
3494         return 0;
3495 }
3496
3497 static bool svm_cpu_has_accelerated_tpr(void)
3498 {
3499         return false;
3500 }
3501
3502 static bool svm_has_emulated_msr(int index)
3503 {
3504         switch (index) {
3505         case MSR_IA32_MCG_EXT_CTL:
3506         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3507                 return false;
3508         default:
3509                 break;
3510         }
3511
3512         return true;
3513 }
3514
3515 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3516 {
3517         return 0;
3518 }
3519
3520 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3521 {
3522         struct vcpu_svm *svm = to_svm(vcpu);
3523
3524         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3525                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3526                                     boot_cpu_has(X86_FEATURE_XSAVES);
3527
3528         /* Update nrips enabled cache */
3529         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3530                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3531
3532         if (!kvm_vcpu_apicv_active(vcpu))
3533                 return;
3534
3535         /*
3536          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3537          * is exposed to the guest, disable AVIC.
3538          */
3539         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3540                 kvm_request_apicv_update(vcpu->kvm, false,
3541                                          APICV_INHIBIT_REASON_X2APIC);
3542
3543         /*
3544          * Currently, AVIC does not work with nested virtualization.
3545          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3546          */
3547         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3548                 kvm_request_apicv_update(vcpu->kvm, false,
3549                                          APICV_INHIBIT_REASON_NESTED);
3550 }
3551
3552 static bool svm_has_wbinvd_exit(void)
3553 {
3554         return true;
3555 }
3556
3557 #define PRE_EX(exit)  { .exit_code = (exit), \
3558                         .stage = X86_ICPT_PRE_EXCEPT, }
3559 #define POST_EX(exit) { .exit_code = (exit), \
3560                         .stage = X86_ICPT_POST_EXCEPT, }
3561 #define POST_MEM(exit) { .exit_code = (exit), \
3562                         .stage = X86_ICPT_POST_MEMACCESS, }
3563
3564 static const struct __x86_intercept {
3565         u32 exit_code;
3566         enum x86_intercept_stage stage;
3567 } x86_intercept_map[] = {
3568         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3569         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3570         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3571         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3572         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3573         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3574         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3575         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3576         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3577         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3578         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3579         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3580         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3581         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3582         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3583         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3584         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3585         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3586         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3587         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3588         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3589         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3590         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3591         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3592         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3593         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3594         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3595         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3596         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3597         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3598         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3599         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3600         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3601         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3602         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3603         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3604         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3605         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3606         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3607         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
3608         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
3609         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
3610         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
3611         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
3612         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
3613         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
3614         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
3615 };
3616
3617 #undef PRE_EX
3618 #undef POST_EX
3619 #undef POST_MEM
3620
3621 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3622                                struct x86_instruction_info *info,
3623                                enum x86_intercept_stage stage,
3624                                struct x86_exception *exception)
3625 {
3626         struct vcpu_svm *svm = to_svm(vcpu);
3627         int vmexit, ret = X86EMUL_CONTINUE;
3628         struct __x86_intercept icpt_info;
3629         struct vmcb *vmcb = svm->vmcb;
3630
3631         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3632                 goto out;
3633
3634         icpt_info = x86_intercept_map[info->intercept];
3635
3636         if (stage != icpt_info.stage)
3637                 goto out;
3638
3639         switch (icpt_info.exit_code) {
3640         case SVM_EXIT_READ_CR0:
3641                 if (info->intercept == x86_intercept_cr_read)
3642                         icpt_info.exit_code += info->modrm_reg;
3643                 break;
3644         case SVM_EXIT_WRITE_CR0: {
3645                 unsigned long cr0, val;
3646                 u64 intercept;
3647
3648                 if (info->intercept == x86_intercept_cr_write)
3649                         icpt_info.exit_code += info->modrm_reg;
3650
3651                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3652                     info->intercept == x86_intercept_clts)
3653                         break;
3654
3655                 intercept = svm->nested.intercept;
3656
3657                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3658                         break;
3659
3660                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3661                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
3662
3663                 if (info->intercept == x86_intercept_lmsw) {
3664                         cr0 &= 0xfUL;
3665                         val &= 0xfUL;
3666                         /* lmsw can't clear PE - catch this here */
3667                         if (cr0 & X86_CR0_PE)
3668                                 val |= X86_CR0_PE;
3669                 }
3670
3671                 if (cr0 ^ val)
3672                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3673
3674                 break;
3675         }
3676         case SVM_EXIT_READ_DR0:
3677         case SVM_EXIT_WRITE_DR0:
3678                 icpt_info.exit_code += info->modrm_reg;
3679                 break;
3680         case SVM_EXIT_MSR:
3681                 if (info->intercept == x86_intercept_wrmsr)
3682                         vmcb->control.exit_info_1 = 1;
3683                 else
3684                         vmcb->control.exit_info_1 = 0;
3685                 break;
3686         case SVM_EXIT_PAUSE:
3687                 /*
3688                  * We get this for NOP only, but pause
3689                  * is rep not, check this here
3690                  */
3691                 if (info->rep_prefix != REPE_PREFIX)
3692                         goto out;
3693                 break;
3694         case SVM_EXIT_IOIO: {
3695                 u64 exit_info;
3696                 u32 bytes;
3697
3698                 if (info->intercept == x86_intercept_in ||
3699                     info->intercept == x86_intercept_ins) {
3700                         exit_info = ((info->src_val & 0xffff) << 16) |
3701                                 SVM_IOIO_TYPE_MASK;
3702                         bytes = info->dst_bytes;
3703                 } else {
3704                         exit_info = (info->dst_val & 0xffff) << 16;
3705                         bytes = info->src_bytes;
3706                 }
3707
3708                 if (info->intercept == x86_intercept_outs ||
3709                     info->intercept == x86_intercept_ins)
3710                         exit_info |= SVM_IOIO_STR_MASK;
3711
3712                 if (info->rep_prefix)
3713                         exit_info |= SVM_IOIO_REP_MASK;
3714
3715                 bytes = min(bytes, 4u);
3716
3717                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3718
3719                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3720
3721                 vmcb->control.exit_info_1 = exit_info;
3722                 vmcb->control.exit_info_2 = info->next_rip;
3723
3724                 break;
3725         }
3726         default:
3727                 break;
3728         }
3729
3730         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3731         if (static_cpu_has(X86_FEATURE_NRIPS))
3732                 vmcb->control.next_rip  = info->next_rip;
3733         vmcb->control.exit_code = icpt_info.exit_code;
3734         vmexit = nested_svm_exit_handled(svm);
3735
3736         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3737                                            : X86EMUL_CONTINUE;
3738
3739 out:
3740         return ret;
3741 }
3742
3743 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3744 {
3745 }
3746
3747 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3748 {
3749         if (pause_filter_thresh)
3750                 shrink_ple_window(vcpu);
3751 }
3752
3753 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3754 {
3755         /* [63:9] are reserved. */
3756         vcpu->arch.mcg_cap &= 0x1ff;
3757 }
3758
3759 static int svm_smi_allowed(struct kvm_vcpu *vcpu)
3760 {
3761         struct vcpu_svm *svm = to_svm(vcpu);
3762
3763         /* Per APM Vol.2 15.22.2 "Response to SMI" */
3764         if (!gif_set(svm))
3765                 return 0;
3766
3767         if (is_guest_mode(&svm->vcpu) &&
3768             svm->nested.intercept & (1ULL << INTERCEPT_SMI)) {
3769                 /* TODO: Might need to set exit_info_1 and exit_info_2 here */
3770                 svm->vmcb->control.exit_code = SVM_EXIT_SMI;
3771                 svm->nested.exit_required = true;
3772                 return 0;
3773         }
3774
3775         return 1;
3776 }
3777
3778 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3779 {
3780         struct vcpu_svm *svm = to_svm(vcpu);
3781         int ret;
3782
3783         if (is_guest_mode(vcpu)) {
3784                 /* FED8h - SVM Guest */
3785                 put_smstate(u64, smstate, 0x7ed8, 1);
3786                 /* FEE0h - SVM Guest VMCB Physical Address */
3787                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3788
3789                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3790                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3791                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3792
3793                 ret = nested_svm_vmexit(svm);
3794                 if (ret)
3795                         return ret;
3796         }
3797         return 0;
3798 }
3799
3800 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
3801 {
3802         struct vcpu_svm *svm = to_svm(vcpu);
3803         struct vmcb *nested_vmcb;
3804         struct kvm_host_map map;
3805         u64 guest;
3806         u64 vmcb;
3807
3808         guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3809         vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
3810
3811         if (guest) {
3812                 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
3813                         return 1;
3814                 nested_vmcb = map.hva;
3815                 enter_svm_guest_mode(svm, vmcb, nested_vmcb, &map);
3816         }
3817         return 0;
3818 }
3819
3820 static int enable_smi_window(struct kvm_vcpu *vcpu)
3821 {
3822         struct vcpu_svm *svm = to_svm(vcpu);
3823
3824         if (!gif_set(svm)) {
3825                 if (vgif_enabled(svm))
3826                         set_intercept(svm, INTERCEPT_STGI);
3827                 /* STGI will cause a vm exit */
3828                 return 1;
3829         }
3830         return 0;
3831 }
3832
3833 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3834 {
3835         unsigned long cr4 = kvm_read_cr4(vcpu);
3836         bool smep = cr4 & X86_CR4_SMEP;
3837         bool smap = cr4 & X86_CR4_SMAP;
3838         bool is_user = svm_get_cpl(vcpu) == 3;
3839
3840         /*
3841          * If RIP is invalid, go ahead with emulation which will cause an
3842          * internal error exit.
3843          */
3844         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3845                 return true;
3846
3847         /*
3848          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3849          *
3850          * Errata:
3851          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3852          * possible that CPU microcode implementing DecodeAssist will fail
3853          * to read bytes of instruction which caused #NPF. In this case,
3854          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3855          * return 0 instead of the correct guest instruction bytes.
3856          *
3857          * This happens because CPU microcode reading instruction bytes
3858          * uses a special opcode which attempts to read data using CPL=0
3859          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3860          * fault, it gives up and returns no instruction bytes.
3861          *
3862          * Detection:
3863          * We reach here in case CPU supports DecodeAssist, raised #NPF and
3864          * returned 0 in GuestIntrBytes field of the VMCB.
3865          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3866          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3867          * in case vCPU CPL==3 (Because otherwise guest would have triggered
3868          * a SMEP fault instead of #NPF).
3869          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3870          * As most guests enable SMAP if they have also enabled SMEP, use above
3871          * logic in order to attempt minimize false-positive of detecting errata
3872          * while still preserving all cases semantic correctness.
3873          *
3874          * Workaround:
3875          * To determine what instruction the guest was executing, the hypervisor
3876          * will have to decode the instruction at the instruction pointer.
3877          *
3878          * In non SEV guest, hypervisor will be able to read the guest
3879          * memory to decode the instruction pointer when insn_len is zero
3880          * so we return true to indicate that decoding is possible.
3881          *
3882          * But in the SEV guest, the guest memory is encrypted with the
3883          * guest specific key and hypervisor will not be able to decode the
3884          * instruction pointer so we will not able to workaround it. Lets
3885          * print the error and request to kill the guest.
3886          */
3887         if (smap && (!smep || is_user)) {
3888                 if (!sev_guest(vcpu->kvm))
3889                         return true;
3890
3891                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
3892                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3893         }
3894
3895         return false;
3896 }
3897
3898 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3899 {
3900         struct vcpu_svm *svm = to_svm(vcpu);
3901
3902         /*
3903          * TODO: Last condition latch INIT signals on vCPU when
3904          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
3905          * To properly emulate the INIT intercept,
3906          * svm_check_nested_events() should call nested_svm_vmexit()
3907          * if an INIT signal is pending.
3908          */
3909         return !gif_set(svm) ||
3910                    (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3911 }
3912
3913 static void svm_vm_destroy(struct kvm *kvm)
3914 {
3915         avic_vm_destroy(kvm);
3916         sev_vm_destroy(kvm);
3917 }
3918
3919 static int svm_vm_init(struct kvm *kvm)
3920 {
3921         if (avic) {
3922                 int ret = avic_vm_init(kvm);
3923                 if (ret)
3924                         return ret;
3925         }
3926
3927         kvm_apicv_init(kvm, avic);
3928         return 0;
3929 }
3930
3931 static struct kvm_x86_ops svm_x86_ops __initdata = {
3932         .hardware_unsetup = svm_hardware_teardown,
3933         .hardware_enable = svm_hardware_enable,
3934         .hardware_disable = svm_hardware_disable,
3935         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3936         .has_emulated_msr = svm_has_emulated_msr,
3937
3938         .vcpu_create = svm_create_vcpu,
3939         .vcpu_free = svm_free_vcpu,
3940         .vcpu_reset = svm_vcpu_reset,
3941
3942         .vm_size = sizeof(struct kvm_svm),
3943         .vm_init = svm_vm_init,
3944         .vm_destroy = svm_vm_destroy,
3945
3946         .prepare_guest_switch = svm_prepare_guest_switch,
3947         .vcpu_load = svm_vcpu_load,
3948         .vcpu_put = svm_vcpu_put,
3949         .vcpu_blocking = svm_vcpu_blocking,
3950         .vcpu_unblocking = svm_vcpu_unblocking,
3951
3952         .update_bp_intercept = update_bp_intercept,
3953         .get_msr_feature = svm_get_msr_feature,
3954         .get_msr = svm_get_msr,
3955         .set_msr = svm_set_msr,
3956         .get_segment_base = svm_get_segment_base,
3957         .get_segment = svm_get_segment,
3958         .set_segment = svm_set_segment,
3959         .get_cpl = svm_get_cpl,
3960         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3961         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3962         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3963         .set_cr0 = svm_set_cr0,
3964         .set_cr4 = svm_set_cr4,
3965         .set_efer = svm_set_efer,
3966         .get_idt = svm_get_idt,
3967         .set_idt = svm_set_idt,
3968         .get_gdt = svm_get_gdt,
3969         .set_gdt = svm_set_gdt,
3970         .get_dr6 = svm_get_dr6,
3971         .set_dr6 = svm_set_dr6,
3972         .set_dr7 = svm_set_dr7,
3973         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
3974         .cache_reg = svm_cache_reg,
3975         .get_rflags = svm_get_rflags,
3976         .set_rflags = svm_set_rflags,
3977
3978         .tlb_flush_all = svm_flush_tlb,
3979         .tlb_flush_current = svm_flush_tlb,
3980         .tlb_flush_gva = svm_flush_tlb_gva,
3981         .tlb_flush_guest = svm_flush_tlb,
3982
3983         .run = svm_vcpu_run,
3984         .handle_exit = handle_exit,
3985         .skip_emulated_instruction = skip_emulated_instruction,
3986         .update_emulated_instruction = NULL,
3987         .set_interrupt_shadow = svm_set_interrupt_shadow,
3988         .get_interrupt_shadow = svm_get_interrupt_shadow,
3989         .patch_hypercall = svm_patch_hypercall,
3990         .set_irq = svm_set_irq,
3991         .set_nmi = svm_inject_nmi,
3992         .queue_exception = svm_queue_exception,
3993         .cancel_injection = svm_cancel_injection,
3994         .interrupt_allowed = svm_interrupt_allowed,
3995         .nmi_allowed = svm_nmi_allowed,
3996         .get_nmi_mask = svm_get_nmi_mask,
3997         .set_nmi_mask = svm_set_nmi_mask,
3998         .enable_nmi_window = enable_nmi_window,
3999         .enable_irq_window = enable_irq_window,
4000         .update_cr8_intercept = update_cr8_intercept,
4001         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4002         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4003         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4004         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4005         .load_eoi_exitmap = svm_load_eoi_exitmap,
4006         .hwapic_irr_update = svm_hwapic_irr_update,
4007         .hwapic_isr_update = svm_hwapic_isr_update,
4008         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4009         .apicv_post_state_restore = avic_post_state_restore,
4010
4011         .set_tss_addr = svm_set_tss_addr,
4012         .set_identity_map_addr = svm_set_identity_map_addr,
4013         .get_tdp_level = get_npt_level,
4014         .get_mt_mask = svm_get_mt_mask,
4015
4016         .get_exit_info = svm_get_exit_info,
4017
4018         .cpuid_update = svm_cpuid_update,
4019
4020         .has_wbinvd_exit = svm_has_wbinvd_exit,
4021
4022         .read_l1_tsc_offset = svm_read_l1_tsc_offset,
4023         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4024
4025         .load_mmu_pgd = svm_load_mmu_pgd,
4026
4027         .check_intercept = svm_check_intercept,
4028         .handle_exit_irqoff = svm_handle_exit_irqoff,
4029
4030         .request_immediate_exit = __kvm_request_immediate_exit,
4031
4032         .sched_in = svm_sched_in,
4033
4034         .pmu_ops = &amd_pmu_ops,
4035         .nested_ops = &svm_nested_ops,
4036
4037         .deliver_posted_interrupt = svm_deliver_avic_intr,
4038         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4039         .update_pi_irte = svm_update_pi_irte,
4040         .setup_mce = svm_setup_mce,
4041
4042         .smi_allowed = svm_smi_allowed,
4043         .pre_enter_smm = svm_pre_enter_smm,
4044         .pre_leave_smm = svm_pre_leave_smm,
4045         .enable_smi_window = enable_smi_window,
4046
4047         .mem_enc_op = svm_mem_enc_op,
4048         .mem_enc_reg_region = svm_register_enc_region,
4049         .mem_enc_unreg_region = svm_unregister_enc_region,
4050
4051         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4052
4053         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4054 };
4055
4056 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4057         .cpu_has_kvm_support = has_svm,
4058         .disabled_by_bios = is_disabled,
4059         .hardware_setup = svm_hardware_setup,
4060         .check_processor_compatibility = svm_check_processor_compat,
4061
4062         .runtime_ops = &svm_x86_ops,
4063 };
4064
4065 static int __init svm_init(void)
4066 {
4067         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4068                         __alignof__(struct vcpu_svm), THIS_MODULE);
4069 }
4070
4071 static void __exit svm_exit(void)
4072 {
4073         kvm_exit();
4074 }
4075
4076 module_init(svm_init)
4077 module_exit(svm_exit)