arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/objtool.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/spec-ctrl.h>
  37 #include <asm/cpu_device_id.h>
  38 #include <asm/traps.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is always on */
  94 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_INVALID,                         .always = false },
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 bool npt_enabled = true;
 117 #else
 118 bool npt_enabled;
 119 #endif
 120
 121 /*
 122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 123  * pause_filter_count: On processors that support Pause filtering(indicated
 124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 125  *      count value. On VMRUN this value is loaded into an internal counter.
 126  *      Each time a pause instruction is executed, this counter is decremented
 127  *      until it reaches zero at which time a #VMEXIT is generated if pause
 128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 129  *      Intercept Filtering for more details.
 130  *      This also indicate if ple logic enabled.
 131  *
 132  * pause_filter_thresh: In addition, some processor families support advanced
 133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 134  *      the amount of time a guest is allowed to execute in a pause loop.
 135  *      In this mode, a 16-bit pause filter threshold field is added in the
 136  *      VMCB. The threshold value is a cycle count that is used to reset the
 137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 138  *      count value from VMCB into an internal counter. Then, on each pause
 139  *      instruction the hardware checks the elapsed number of cycles since
 140  *      the most recent pause instruction against the pause filter threshold.
 141  *      If the elapsed cycle count is greater than the pause filter threshold,
 142  *      then the internal pause count is reloaded from the VMCB and execution
 143  *      continues. If the elapsed cycle count is less than the pause filter
 144  *      threshold, then the internal pause count is decremented. If the count
 145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 146  *      triggered. If advanced pause filtering is supported and pause filter
 147  *      threshold field is set to zero, the filter will operate in the simpler,
 148  *      count only mode.
 149  */
 150
 151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 152 module_param(pause_filter_thresh, ushort, 0444);
 153
 154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 155 module_param(pause_filter_count, ushort, 0444);
 156
 157 /* Default doubles per-vcpu window every exit. */
 158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 159 module_param(pause_filter_count_grow, ushort, 0444);
 160
 161 /* Default resets per-vcpu window every exit to pause_filter_count. */
 162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 163 module_param(pause_filter_count_shrink, ushort, 0444);
 164
 165 /* Default is to compute the maximum so we can never overflow. */
 166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 167 module_param(pause_filter_count_max, ushort, 0444);
 168
 169 /* allow nested paging (virtualized MMU) for all guests */
 170 static int npt = true;
 171 module_param(npt, int, S_IRUGO);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 /* enable/disable SEV-ES support */
 194 int sev_es = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 195 module_param(sev_es, int, 0444);
 196
 197 bool __read_mostly dump_invalid_vmcb;
 198 module_param(dump_invalid_vmcb, bool, 0644);
 199
 200 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 201
 202 static void svm_complete_interrupts(struct vcpu_svm *svm);
 203
 204 static unsigned long iopm_base;
 205
 206 struct kvm_ldttss_desc {
 207         u16 limit0;
 208         u16 base0;
 209         unsigned base1:8, type:5, dpl:2, p:1;
 210         unsigned limit1:4, zero0:3, g:1, base2:8;
 211         u32 base3;
 212         u32 zero1;
 213 } __attribute__((packed));
 214
 215 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 216
 217 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 218
 219 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 220 #define MSRS_RANGE_SIZE 2048
 221 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 222
 223 u32 svm_msrpm_offset(u32 msr)
 224 {
 225         u32 offset;
 226         int i;
 227
 228         for (i = 0; i < NUM_MSR_MAPS; i++) {
 229                 if (msr < msrpm_ranges[i] ||
 230                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 231                         continue;
 232
 233                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 234                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 235
 236                 /* Now we have the u8 offset - but need the u32 offset */
 237                 return offset / 4;
 238         }
 239
 240         /* MSR not in any range */
 241         return MSR_INVALID;
 242 }
 243
 244 #define MAX_INST_SIZE 15
 245
 246 static inline void clgi(void)
 247 {
 248         asm volatile (__ex("clgi"));
 249 }
 250
 251 static inline void stgi(void)
 252 {
 253         asm volatile (__ex("stgi"));
 254 }
 255
 256 static inline void invlpga(unsigned long addr, u32 asid)
 257 {
 258         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 259 }
 260
 261 static int get_max_npt_level(void)
 262 {
 263 #ifdef CONFIG_X86_64
 264         return PT64_ROOT_4LEVEL;
 265 #else
 266         return PT32E_ROOT_LEVEL;
 267 #endif
 268 }
 269
 270 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 271 {
 272         struct vcpu_svm *svm = to_svm(vcpu);
 273         u64 old_efer = vcpu->arch.efer;
 274         vcpu->arch.efer = efer;
 275
 276         if (!npt_enabled) {
 277                 /* Shadow paging assumes NX to be available.  */
 278                 efer |= EFER_NX;
 279
 280                 if (!(efer & EFER_LMA))
 281                         efer &= ~EFER_LME;
 282         }
 283
 284         if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
 285                 if (!(efer & EFER_SVME)) {
 286                         svm_leave_nested(svm);
 287                         svm_set_gif(svm, true);
 288
 289                         /*
 290                          * Free the nested guest state, unless we are in SMM.
 291                          * In this case we will return to the nested guest
 292                          * as soon as we leave SMM.
 293                          */
 294                         if (!is_smm(&svm->vcpu))
 295                                 svm_free_nested(svm);
 296
 297                 } else {
 298                         int ret = svm_allocate_nested(svm);
 299
 300                         if (ret) {
 301                                 vcpu->arch.efer = old_efer;
 302                                 return ret;
 303                         }
 304                 }
 305         }
 306
 307         svm->vmcb->save.efer = efer | EFER_SVME;
 308         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
 309         return 0;
 310 }
 311
 312 static int is_external_interrupt(u32 info)
 313 {
 314         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 315         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 316 }
 317
 318 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 319 {
 320         struct vcpu_svm *svm = to_svm(vcpu);
 321         u32 ret = 0;
 322
 323         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 324                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 325         return ret;
 326 }
 327
 328 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 329 {
 330         struct vcpu_svm *svm = to_svm(vcpu);
 331
 332         if (mask == 0)
 333                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 334         else
 335                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 336
 337 }
 338
 339 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 340 {
 341         struct vcpu_svm *svm = to_svm(vcpu);
 342
 343         /*
 344          * SEV-ES does not expose the next RIP. The RIP update is controlled by
 345          * the type of exit and the #VC handler in the guest.
 346          */
 347         if (sev_es_guest(vcpu->kvm))
 348                 goto done;
 349
 350         if (nrips && svm->vmcb->control.next_rip != 0) {
 351                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 352                 svm->next_rip = svm->vmcb->control.next_rip;
 353         }
 354
 355         if (!svm->next_rip) {
 356                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 357                         return 0;
 358         } else {
 359                 kvm_rip_write(vcpu, svm->next_rip);
 360         }
 361
 362 done:
 363         svm_set_interrupt_shadow(vcpu, 0);
 364
 365         return 1;
 366 }
 367
 368 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 369 {
 370         struct vcpu_svm *svm = to_svm(vcpu);
 371         unsigned nr = vcpu->arch.exception.nr;
 372         bool has_error_code = vcpu->arch.exception.has_error_code;
 373         u32 error_code = vcpu->arch.exception.error_code;
 374
 375         kvm_deliver_exception_payload(&svm->vcpu);
 376
 377         if (nr == BP_VECTOR && !nrips) {
 378                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 379
 380                 /*
 381                  * For guest debugging where we have to reinject #BP if some
 382                  * INT3 is guest-owned:
 383                  * Emulate nRIP by moving RIP forward. Will fail if injection
 384                  * raises a fault that is not intercepted. Still better than
 385                  * failing in all cases.
 386                  */
 387                 (void)skip_emulated_instruction(&svm->vcpu);
 388                 rip = kvm_rip_read(&svm->vcpu);
 389                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 390                 svm->int3_injected = rip - old_rip;
 391         }
 392
 393         svm->vmcb->control.event_inj = nr
 394                 | SVM_EVTINJ_VALID
 395                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 396                 | SVM_EVTINJ_TYPE_EXEPT;
 397         svm->vmcb->control.event_inj_err = error_code;
 398 }
 399
 400 static void svm_init_erratum_383(void)
 401 {
 402         u32 low, high;
 403         int err;
 404         u64 val;
 405
 406         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 407                 return;
 408
 409         /* Use _safe variants to not break nested virtualization */
 410         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 411         if (err)
 412                 return;
 413
 414         val |= (1ULL << 47);
 415
 416         low  = lower_32_bits(val);
 417         high = upper_32_bits(val);
 418
 419         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 420
 421         erratum_383_found = true;
 422 }
 423
 424 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 425 {
 426         /*
 427          * Guests should see errata 400 and 415 as fixed (assuming that
 428          * HLT and IO instructions are intercepted).
 429          */
 430         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 431         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 432
 433         /*
 434          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 435          * all osvw.status bits inside that length, including bit 0 (which is
 436          * reserved for erratum 298), are valid. However, if host processor's
 437          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 438          * be conservative here and therefore we tell the guest that erratum 298
 439          * is present (because we really don't know).
 440          */
 441         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 442                 vcpu->arch.osvw.status |= 1;
 443 }
 444
 445 static int has_svm(void)
 446 {
 447         const char *msg;
 448
 449         if (!cpu_has_svm(&msg)) {
 450                 printk(KERN_INFO "has_svm: %s\n", msg);
 451                 return 0;
 452         }
 453
 454         return 1;
 455 }
 456
 457 static void svm_hardware_disable(void)
 458 {
 459         /* Make sure we clean up behind us */
 460         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 461                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 462
 463         cpu_svm_disable();
 464
 465         amd_pmu_disable_virt();
 466 }
 467
 468 static int svm_hardware_enable(void)
 469 {
 470
 471         struct svm_cpu_data *sd;
 472         uint64_t efer;
 473         struct desc_struct *gdt;
 474         int me = raw_smp_processor_id();
 475
 476         rdmsrl(MSR_EFER, efer);
 477         if (efer & EFER_SVME)
 478                 return -EBUSY;
 479
 480         if (!has_svm()) {
 481                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 482                 return -EINVAL;
 483         }
 484         sd = per_cpu(svm_data, me);
 485         if (!sd) {
 486                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 487                 return -EINVAL;
 488         }
 489
 490         sd->asid_generation = 1;
 491         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 492         sd->next_asid = sd->max_asid + 1;
 493         sd->min_asid = max_sev_asid + 1;
 494
 495         gdt = get_current_gdt_rw();
 496         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 497
 498         wrmsrl(MSR_EFER, efer | EFER_SVME);
 499
 500         wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
 501
 502         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 503                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 504                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 505         }
 506
 507
 508         /*
 509          * Get OSVW bits.
 510          *
 511          * Note that it is possible to have a system with mixed processor
 512          * revisions and therefore different OSVW bits. If bits are not the same
 513          * on different processors then choose the worst case (i.e. if erratum
 514          * is present on one processor and not on another then assume that the
 515          * erratum is present everywhere).
 516          */
 517         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 518                 uint64_t len, status = 0;
 519                 int err;
 520
 521                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 522                 if (!err)
 523                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 524                                                       &err);
 525
 526                 if (err)
 527                         osvw_status = osvw_len = 0;
 528                 else {
 529                         if (len < osvw_len)
 530                                 osvw_len = len;
 531                         osvw_status |= status;
 532                         osvw_status &= (1ULL << osvw_len) - 1;
 533                 }
 534         } else
 535                 osvw_status = osvw_len = 0;
 536
 537         svm_init_erratum_383();
 538
 539         amd_pmu_enable_virt();
 540
 541         return 0;
 542 }
 543
 544 static void svm_cpu_uninit(int cpu)
 545 {
 546         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 547
 548         if (!sd)
 549                 return;
 550
 551         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 552         kfree(sd->sev_vmcbs);
 553         __free_page(sd->save_area);
 554         kfree(sd);
 555 }
 556
 557 static int svm_cpu_init(int cpu)
 558 {
 559         struct svm_cpu_data *sd;
 560
 561         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 562         if (!sd)
 563                 return -ENOMEM;
 564         sd->cpu = cpu;
 565         sd->save_area = alloc_page(GFP_KERNEL);
 566         if (!sd->save_area)
 567                 goto free_cpu_data;
 568         clear_page(page_address(sd->save_area));
 569
 570         if (svm_sev_enabled()) {
 571                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 572                                               sizeof(void *),
 573                                               GFP_KERNEL);
 574                 if (!sd->sev_vmcbs)
 575                         goto free_save_area;
 576         }
 577
 578         per_cpu(svm_data, cpu) = sd;
 579
 580         return 0;
 581
 582 free_save_area:
 583         __free_page(sd->save_area);
 584 free_cpu_data:
 585         kfree(sd);
 586         return -ENOMEM;
 587
 588 }
 589
 590 static int direct_access_msr_slot(u32 msr)
 591 {
 592         u32 i;
 593
 594         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 595                 if (direct_access_msrs[i].index == msr)
 596                         return i;
 597
 598         return -ENOENT;
 599 }
 600
 601 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
 602                                      int write)
 603 {
 604         struct vcpu_svm *svm = to_svm(vcpu);
 605         int slot = direct_access_msr_slot(msr);
 606
 607         if (slot == -ENOENT)
 608                 return;
 609
 610         /* Set the shadow bitmaps to the desired intercept states */
 611         if (read)
 612                 set_bit(slot, svm->shadow_msr_intercept.read);
 613         else
 614                 clear_bit(slot, svm->shadow_msr_intercept.read);
 615
 616         if (write)
 617                 set_bit(slot, svm->shadow_msr_intercept.write);
 618         else
 619                 clear_bit(slot, svm->shadow_msr_intercept.write);
 620 }
 621
 622 static bool valid_msr_intercept(u32 index)
 623 {
 624         return direct_access_msr_slot(index) != -ENOENT;
 625 }
 626
 627 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
 628 {
 629         u8 bit_write;
 630         unsigned long tmp;
 631         u32 offset;
 632         u32 *msrpm;
 633
 634         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 635                                       to_svm(vcpu)->msrpm;
 636
 637         offset    = svm_msrpm_offset(msr);
 638         bit_write = 2 * (msr & 0x0f) + 1;
 639         tmp       = msrpm[offset];
 640
 641         BUG_ON(offset == MSR_INVALID);
 642
 643         return !!test_bit(bit_write,  &tmp);
 644 }
 645
 646 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
 647                                         u32 msr, int read, int write)
 648 {
 649         u8 bit_read, bit_write;
 650         unsigned long tmp;
 651         u32 offset;
 652
 653         /*
 654          * If this warning triggers extend the direct_access_msrs list at the
 655          * beginning of the file
 656          */
 657         WARN_ON(!valid_msr_intercept(msr));
 658
 659         /* Enforce non allowed MSRs to trap */
 660         if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
 661                 read = 0;
 662
 663         if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
 664                 write = 0;
 665
 666         offset    = svm_msrpm_offset(msr);
 667         bit_read  = 2 * (msr & 0x0f);
 668         bit_write = 2 * (msr & 0x0f) + 1;
 669         tmp       = msrpm[offset];
 670
 671         BUG_ON(offset == MSR_INVALID);
 672
 673         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 674         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 675
 676         msrpm[offset] = tmp;
 677 }
 678
 679 static void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
 680                                  int read, int write)
 681 {
 682         set_shadow_msr_intercept(vcpu, msr, read, write);
 683         set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
 684 }
 685
 686 u32 *svm_vcpu_alloc_msrpm(void)
 687 {
 688         struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
 689         u32 *msrpm;
 690
 691         if (!pages)
 692                 return NULL;
 693
 694         msrpm = page_address(pages);
 695         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 696
 697         return msrpm;
 698 }
 699
 700 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
 701 {
 702         int i;
 703
 704         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 705                 if (!direct_access_msrs[i].always)
 706                         continue;
 707                 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
 708         }
 709 }
 710
 711
 712 void svm_vcpu_free_msrpm(u32 *msrpm)
 713 {
 714         __free_pages(virt_to_page(msrpm), MSRPM_ALLOC_ORDER);
 715 }
 716
 717 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
 718 {
 719         struct vcpu_svm *svm = to_svm(vcpu);
 720         u32 i;
 721
 722         /*
 723          * Set intercept permissions for all direct access MSRs again. They
 724          * will automatically get filtered through the MSR filter, so we are
 725          * back in sync after this.
 726          */
 727         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 728                 u32 msr = direct_access_msrs[i].index;
 729                 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
 730                 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
 731
 732                 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
 733         }
 734 }
 735
 736 static void add_msr_offset(u32 offset)
 737 {
 738         int i;
 739
 740         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 741
 742                 /* Offset already in list? */
 743                 if (msrpm_offsets[i] == offset)
 744                         return;
 745
 746                 /* Slot used by another offset? */
 747                 if (msrpm_offsets[i] != MSR_INVALID)
 748                         continue;
 749
 750                 /* Add offset to list */
 751                 msrpm_offsets[i] = offset;
 752
 753                 return;
 754         }
 755
 756         /*
 757          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 758          * increase MSRPM_OFFSETS in this case.
 759          */
 760         BUG();
 761 }
 762
 763 static void init_msrpm_offsets(void)
 764 {
 765         int i;
 766
 767         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 768
 769         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 770                 u32 offset;
 771
 772                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 773                 BUG_ON(offset == MSR_INVALID);
 774
 775                 add_msr_offset(offset);
 776         }
 777 }
 778
 779 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
 780 {
 781         struct vcpu_svm *svm = to_svm(vcpu);
 782
 783         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 784         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 785         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 786         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 787         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 788 }
 789
 790 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
 791 {
 792         struct vcpu_svm *svm = to_svm(vcpu);
 793
 794         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 795         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 796         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 797         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 798         set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 799 }
 800
 801 void disable_nmi_singlestep(struct vcpu_svm *svm)
 802 {
 803         svm->nmi_singlestep = false;
 804
 805         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 806                 /* Clear our flags if they were not set by the guest */
 807                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 808                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 809                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 810                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 811         }
 812 }
 813
 814 static void grow_ple_window(struct kvm_vcpu *vcpu)
 815 {
 816         struct vcpu_svm *svm = to_svm(vcpu);
 817         struct vmcb_control_area *control = &svm->vmcb->control;
 818         int old = control->pause_filter_count;
 819
 820         control->pause_filter_count = __grow_ple_window(old,
 821                                                         pause_filter_count,
 822                                                         pause_filter_count_grow,
 823                                                         pause_filter_count_max);
 824
 825         if (control->pause_filter_count != old) {
 826                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 827                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 828                                             control->pause_filter_count, old);
 829         }
 830 }
 831
 832 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 833 {
 834         struct vcpu_svm *svm = to_svm(vcpu);
 835         struct vmcb_control_area *control = &svm->vmcb->control;
 836         int old = control->pause_filter_count;
 837
 838         control->pause_filter_count =
 839                                 __shrink_ple_window(old,
 840                                                     pause_filter_count,
 841                                                     pause_filter_count_shrink,
 842                                                     pause_filter_count);
 843         if (control->pause_filter_count != old) {
 844                 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 845                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 846                                             control->pause_filter_count, old);
 847         }
 848 }
 849
 850 /*
 851  * The default MMIO mask is a single bit (excluding the present bit),
 852  * which could conflict with the memory encryption bit. Check for
 853  * memory encryption support and override the default MMIO mask if
 854  * memory encryption is enabled.
 855  */
 856 static __init void svm_adjust_mmio_mask(void)
 857 {
 858         unsigned int enc_bit, mask_bit;
 859         u64 msr, mask;
 860
 861         /* If there is no memory encryption support, use existing mask */
 862         if (cpuid_eax(0x80000000) < 0x8000001f)
 863                 return;
 864
 865         /* If memory encryption is not enabled, use existing mask */
 866         rdmsrl(MSR_K8_SYSCFG, msr);
 867         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 868                 return;
 869
 870         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 871         mask_bit = boot_cpu_data.x86_phys_bits;
 872
 873         /* Increment the mask bit if it is the same as the encryption bit */
 874         if (enc_bit == mask_bit)
 875                 mask_bit++;
 876
 877         /*
 878          * If the mask bit location is below 52, then some bits above the
 879          * physical addressing limit will always be reserved, so use the
 880          * rsvd_bits() function to generate the mask. This mask, along with
 881          * the present bit, will be used to generate a page fault with
 882          * PFER.RSV = 1.
 883          *
 884          * If the mask bit location is 52 (or above), then clear the mask.
 885          */
 886         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 887
 888         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 889 }
 890
 891 static void svm_hardware_teardown(void)
 892 {
 893         int cpu;
 894
 895         if (svm_sev_enabled())
 896                 sev_hardware_teardown();
 897
 898         for_each_possible_cpu(cpu)
 899                 svm_cpu_uninit(cpu);
 900
 901         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 902         iopm_base = 0;
 903 }
 904
 905 static __init void svm_set_cpu_caps(void)
 906 {
 907         kvm_set_cpu_caps();
 908
 909         supported_xss = 0;
 910
 911         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 912         if (nested) {
 913                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 914
 915                 if (nrips)
 916                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 917
 918                 if (npt_enabled)
 919                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 920         }
 921
 922         /* CPUID 0x80000008 */
 923         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 924             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 925                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 926
 927         /* Enable INVPCID feature */
 928         kvm_cpu_cap_check_and_set(X86_FEATURE_INVPCID);
 929 }
 930
 931 static __init int svm_hardware_setup(void)
 932 {
 933         int cpu;
 934         struct page *iopm_pages;
 935         void *iopm_va;
 936         int r;
 937
 938         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 939
 940         if (!iopm_pages)
 941                 return -ENOMEM;
 942
 943         iopm_va = page_address(iopm_pages);
 944         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 945         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 946
 947         init_msrpm_offsets();
 948
 949         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 950
 951         if (boot_cpu_has(X86_FEATURE_NX))
 952                 kvm_enable_efer_bits(EFER_NX);
 953
 954         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 955                 kvm_enable_efer_bits(EFER_FFXSR);
 956
 957         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 958                 kvm_has_tsc_control = true;
 959                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 960                 kvm_tsc_scaling_ratio_frac_bits = 32;
 961         }
 962
 963         /* Check for pause filtering support */
 964         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 965                 pause_filter_count = 0;
 966                 pause_filter_thresh = 0;
 967         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 968                 pause_filter_thresh = 0;
 969         }
 970
 971         if (nested) {
 972                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 973                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 974         }
 975
 976         if (IS_ENABLED(CONFIG_KVM_AMD_SEV) && sev) {
 977                 sev_hardware_setup();
 978         } else {
 979                 sev = false;
 980                 sev_es = false;
 981         }
 982
 983         svm_adjust_mmio_mask();
 984
 985         for_each_possible_cpu(cpu) {
 986                 r = svm_cpu_init(cpu);
 987                 if (r)
 988                         goto err;
 989         }
 990
 991         if (!boot_cpu_has(X86_FEATURE_NPT))
 992                 npt_enabled = false;
 993
 994         if (npt_enabled && !npt)
 995                 npt_enabled = false;
 996
 997         kvm_configure_mmu(npt_enabled, get_max_npt_level(), PG_LEVEL_1G);
 998         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 999
1000         if (nrips) {
1001                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
1002                         nrips = false;
1003         }
1004
1005         if (avic) {
1006                 if (!npt_enabled ||
1007                     !boot_cpu_has(X86_FEATURE_AVIC) ||
1008                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
1009                         avic = false;
1010                 } else {
1011                         pr_info("AVIC enabled\n");
1012
1013                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
1014                 }
1015         }
1016
1017         if (vls) {
1018                 if (!npt_enabled ||
1019                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
1020                     !IS_ENABLED(CONFIG_X86_64)) {
1021                         vls = false;
1022                 } else {
1023                         pr_info("Virtual VMLOAD VMSAVE supported\n");
1024                 }
1025         }
1026
1027         if (vgif) {
1028                 if (!boot_cpu_has(X86_FEATURE_VGIF))
1029                         vgif = false;
1030                 else
1031                         pr_info("Virtual GIF supported\n");
1032         }
1033
1034         svm_set_cpu_caps();
1035
1036         /*
1037          * It seems that on AMD processors PTE's accessed bit is
1038          * being set by the CPU hardware before the NPF vmexit.
1039          * This is not expected behaviour and our tests fail because
1040          * of it.
1041          * A workaround here is to disable support for
1042          * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
1043          * In this case userspace can know if there is support using
1044          * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
1045          * it
1046          * If future AMD CPU models change the behaviour described above,
1047          * this variable can be changed accordingly
1048          */
1049         allow_smaller_maxphyaddr = !npt_enabled;
1050
1051         return 0;
1052
1053 err:
1054         svm_hardware_teardown();
1055         return r;
1056 }
1057
1058 static void init_seg(struct vmcb_seg *seg)
1059 {
1060         seg->selector = 0;
1061         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1062                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1063         seg->limit = 0xffff;
1064         seg->base = 0;
1065 }
1066
1067 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1068 {
1069         seg->selector = 0;
1070         seg->attrib = SVM_SELECTOR_P_MASK | type;
1071         seg->limit = 0xffff;
1072         seg->base = 0;
1073 }
1074
1075 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1076 {
1077         struct vcpu_svm *svm = to_svm(vcpu);
1078         u64 g_tsc_offset = 0;
1079
1080         if (is_guest_mode(vcpu)) {
1081                 /* Write L1's TSC offset.  */
1082                 g_tsc_offset = svm->vmcb->control.tsc_offset -
1083                                svm->nested.hsave->control.tsc_offset;
1084                 svm->nested.hsave->control.tsc_offset = offset;
1085         }
1086
1087         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1088                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
1089                                    offset);
1090
1091         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
1092
1093         vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1094         return svm->vmcb->control.tsc_offset;
1095 }
1096
1097 static void svm_check_invpcid(struct vcpu_svm *svm)
1098 {
1099         /*
1100          * Intercept INVPCID instruction only if shadow page table is
1101          * enabled. Interception is not required with nested page table
1102          * enabled.
1103          */
1104         if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1105                 if (!npt_enabled)
1106                         svm_set_intercept(svm, INTERCEPT_INVPCID);
1107                 else
1108                         svm_clr_intercept(svm, INTERCEPT_INVPCID);
1109         }
1110 }
1111
1112 static void init_vmcb(struct vcpu_svm *svm)
1113 {
1114         struct vmcb_control_area *control = &svm->vmcb->control;
1115         struct vmcb_save_area *save = &svm->vmcb->save;
1116
1117         svm->vcpu.arch.hflags = 0;
1118
1119         svm_set_intercept(svm, INTERCEPT_CR0_READ);
1120         svm_set_intercept(svm, INTERCEPT_CR3_READ);
1121         svm_set_intercept(svm, INTERCEPT_CR4_READ);
1122         svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1123         svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1124         svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1125         if (!kvm_vcpu_apicv_active(&svm->vcpu))
1126                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1127
1128         set_dr_intercepts(svm);
1129
1130         set_exception_intercept(svm, PF_VECTOR);
1131         set_exception_intercept(svm, UD_VECTOR);
1132         set_exception_intercept(svm, MC_VECTOR);
1133         set_exception_intercept(svm, AC_VECTOR);
1134         set_exception_intercept(svm, DB_VECTOR);
1135         /*
1136          * Guest access to VMware backdoor ports could legitimately
1137          * trigger #GP because of TSS I/O permission bitmap.
1138          * We intercept those #GP and allow access to them anyway
1139          * as VMware does.
1140          */
1141         if (enable_vmware_backdoor)
1142                 set_exception_intercept(svm, GP_VECTOR);
1143
1144         svm_set_intercept(svm, INTERCEPT_INTR);
1145         svm_set_intercept(svm, INTERCEPT_NMI);
1146         svm_set_intercept(svm, INTERCEPT_SMI);
1147         svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1148         svm_set_intercept(svm, INTERCEPT_RDPMC);
1149         svm_set_intercept(svm, INTERCEPT_CPUID);
1150         svm_set_intercept(svm, INTERCEPT_INVD);
1151         svm_set_intercept(svm, INTERCEPT_INVLPG);
1152         svm_set_intercept(svm, INTERCEPT_INVLPGA);
1153         svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1154         svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1155         svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1156         svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1157         svm_set_intercept(svm, INTERCEPT_VMRUN);
1158         svm_set_intercept(svm, INTERCEPT_VMMCALL);
1159         svm_set_intercept(svm, INTERCEPT_VMLOAD);
1160         svm_set_intercept(svm, INTERCEPT_VMSAVE);
1161         svm_set_intercept(svm, INTERCEPT_STGI);
1162         svm_set_intercept(svm, INTERCEPT_CLGI);
1163         svm_set_intercept(svm, INTERCEPT_SKINIT);
1164         svm_set_intercept(svm, INTERCEPT_WBINVD);
1165         svm_set_intercept(svm, INTERCEPT_XSETBV);
1166         svm_set_intercept(svm, INTERCEPT_RDPRU);
1167         svm_set_intercept(svm, INTERCEPT_RSM);
1168
1169         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1170                 svm_set_intercept(svm, INTERCEPT_MONITOR);
1171                 svm_set_intercept(svm, INTERCEPT_MWAIT);
1172         }
1173
1174         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1175                 svm_set_intercept(svm, INTERCEPT_HLT);
1176
1177         control->iopm_base_pa = __sme_set(iopm_base);
1178         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1179         control->int_ctl = V_INTR_MASKING_MASK;
1180
1181         init_seg(&save->es);
1182         init_seg(&save->ss);
1183         init_seg(&save->ds);
1184         init_seg(&save->fs);
1185         init_seg(&save->gs);
1186
1187         save->cs.selector = 0xf000;
1188         save->cs.base = 0xffff0000;
1189         /* Executable/Readable Code Segment */
1190         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1191                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1192         save->cs.limit = 0xffff;
1193
1194         save->gdtr.limit = 0xffff;
1195         save->idtr.limit = 0xffff;
1196
1197         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1198         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1199
1200         svm_set_efer(&svm->vcpu, 0);
1201         save->dr6 = 0xffff0ff0;
1202         kvm_set_rflags(&svm->vcpu, 2);
1203         save->rip = 0x0000fff0;
1204         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1205
1206         /*
1207          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1208          * It also updates the guest-visible cr0 value.
1209          */
1210         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1211         kvm_mmu_reset_context(&svm->vcpu);
1212
1213         save->cr4 = X86_CR4_PAE;
1214         /* rdx = ?? */
1215
1216         if (npt_enabled) {
1217                 /* Setup VMCB for Nested Paging */
1218                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1219                 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1220                 clr_exception_intercept(svm, PF_VECTOR);
1221                 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1222                 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1223                 save->g_pat = svm->vcpu.arch.pat;
1224                 save->cr3 = 0;
1225                 save->cr4 = 0;
1226         }
1227         svm->asid_generation = 0;
1228         svm->asid = 0;
1229
1230         svm->nested.vmcb12_gpa = 0;
1231         svm->vcpu.arch.hflags = 0;
1232
1233         if (!kvm_pause_in_guest(svm->vcpu.kvm)) {
1234                 control->pause_filter_count = pause_filter_count;
1235                 if (pause_filter_thresh)
1236                         control->pause_filter_thresh = pause_filter_thresh;
1237                 svm_set_intercept(svm, INTERCEPT_PAUSE);
1238         } else {
1239                 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1240         }
1241
1242         svm_check_invpcid(svm);
1243
1244         if (kvm_vcpu_apicv_active(&svm->vcpu))
1245                 avic_init_vmcb(svm);
1246
1247         /*
1248          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1249          * in VMCB and clear intercepts to avoid #VMEXIT.
1250          */
1251         if (vls) {
1252                 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1253                 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1254                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1255         }
1256
1257         if (vgif) {
1258                 svm_clr_intercept(svm, INTERCEPT_STGI);
1259                 svm_clr_intercept(svm, INTERCEPT_CLGI);
1260                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1261         }
1262
1263         if (sev_guest(svm->vcpu.kvm)) {
1264                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1265                 clr_exception_intercept(svm, UD_VECTOR);
1266         }
1267
1268         vmcb_mark_all_dirty(svm->vmcb);
1269
1270         enable_gif(svm);
1271
1272 }
1273
1274 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277         u32 dummy;
1278         u32 eax = 1;
1279
1280         svm->spec_ctrl = 0;
1281         svm->virt_spec_ctrl = 0;
1282
1283         if (!init_event) {
1284                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1285                                            MSR_IA32_APICBASE_ENABLE;
1286                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1287                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1288         }
1289         init_vmcb(svm);
1290
1291         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1292         kvm_rdx_write(vcpu, eax);
1293
1294         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1295                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1296 }
1297
1298 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1299 {
1300         struct vcpu_svm *svm;
1301         struct page *vmcb_page;
1302         struct page *vmsa_page = NULL;
1303         int err;
1304
1305         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1306         svm = to_svm(vcpu);
1307
1308         err = -ENOMEM;
1309         vmcb_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1310         if (!vmcb_page)
1311                 goto out;
1312
1313         if (sev_es_guest(svm->vcpu.kvm)) {
1314                 /*
1315                  * SEV-ES guests require a separate VMSA page used to contain
1316                  * the encrypted register state of the guest.
1317                  */
1318                 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1319                 if (!vmsa_page)
1320                         goto error_free_vmcb_page;
1321
1322                 /*
1323                  * SEV-ES guests maintain an encrypted version of their FPU
1324                  * state which is restored and saved on VMRUN and VMEXIT.
1325                  * Free the fpu structure to prevent KVM from attempting to
1326                  * access the FPU state.
1327                  */
1328                 kvm_free_guest_fpu(vcpu);
1329         }
1330
1331         err = avic_init_vcpu(svm);
1332         if (err)
1333                 goto error_free_vmsa_page;
1334
1335         /* We initialize this flag to true to make sure that the is_running
1336          * bit would be set the first time the vcpu is loaded.
1337          */
1338         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1339                 svm->avic_is_running = true;
1340
1341         svm->msrpm = svm_vcpu_alloc_msrpm();
1342         if (!svm->msrpm)
1343                 goto error_free_vmsa_page;
1344
1345         svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1346
1347         svm->vmcb = page_address(vmcb_page);
1348         svm->vmcb_pa = __sme_set(page_to_pfn(vmcb_page) << PAGE_SHIFT);
1349
1350         if (vmsa_page)
1351                 svm->vmsa = page_address(vmsa_page);
1352
1353         svm->asid_generation = 0;
1354         init_vmcb(svm);
1355
1356         svm_init_osvw(vcpu);
1357         vcpu->arch.microcode_version = 0x01000065;
1358
1359         return 0;
1360
1361 error_free_vmsa_page:
1362         if (vmsa_page)
1363                 __free_page(vmsa_page);
1364 error_free_vmcb_page:
1365         __free_page(vmcb_page);
1366 out:
1367         return err;
1368 }
1369
1370 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1371 {
1372         int i;
1373
1374         for_each_online_cpu(i)
1375                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1376 }
1377
1378 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1379 {
1380         struct vcpu_svm *svm = to_svm(vcpu);
1381
1382         /*
1383          * The vmcb page can be recycled, causing a false negative in
1384          * svm_vcpu_load(). So, ensure that no logical CPU has this
1385          * vmcb page recorded as its current vmcb.
1386          */
1387         svm_clear_current_vmcb(svm->vmcb);
1388
1389         svm_free_nested(svm);
1390
1391         sev_free_vcpu(vcpu);
1392
1393         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1394         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1395 }
1396
1397 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1398 {
1399         struct vcpu_svm *svm = to_svm(vcpu);
1400         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1401         int i;
1402
1403         if (unlikely(cpu != vcpu->cpu)) {
1404                 svm->asid_generation = 0;
1405                 vmcb_mark_all_dirty(svm->vmcb);
1406         }
1407
1408 #ifdef CONFIG_X86_64
1409         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1410 #endif
1411         savesegment(fs, svm->host.fs);
1412         savesegment(gs, svm->host.gs);
1413         svm->host.ldt = kvm_read_ldt();
1414
1415         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1416                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1417
1418         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1419                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1420                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1421                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1422                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1423                 }
1424         }
1425         /* This assumes that the kernel never uses MSR_TSC_AUX */
1426         if (static_cpu_has(X86_FEATURE_RDTSCP))
1427                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1428
1429         if (sd->current_vmcb != svm->vmcb) {
1430                 sd->current_vmcb = svm->vmcb;
1431                 indirect_branch_prediction_barrier();
1432         }
1433         avic_vcpu_load(vcpu, cpu);
1434 }
1435
1436 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1437 {
1438         struct vcpu_svm *svm = to_svm(vcpu);
1439         int i;
1440
1441         avic_vcpu_put(vcpu);
1442
1443         ++vcpu->stat.host_state_reload;
1444         kvm_load_ldt(svm->host.ldt);
1445 #ifdef CONFIG_X86_64
1446         loadsegment(fs, svm->host.fs);
1447         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1448         load_gs_index(svm->host.gs);
1449 #else
1450 #ifdef CONFIG_X86_32_LAZY_GS
1451         loadsegment(gs, svm->host.gs);
1452 #endif
1453 #endif
1454         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1455                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1456 }
1457
1458 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1459 {
1460         struct vcpu_svm *svm = to_svm(vcpu);
1461         unsigned long rflags = svm->vmcb->save.rflags;
1462
1463         if (svm->nmi_singlestep) {
1464                 /* Hide our flags if they were not set by the guest */
1465                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1466                         rflags &= ~X86_EFLAGS_TF;
1467                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1468                         rflags &= ~X86_EFLAGS_RF;
1469         }
1470         return rflags;
1471 }
1472
1473 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1474 {
1475         if (to_svm(vcpu)->nmi_singlestep)
1476                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1477
1478        /*
1479         * Any change of EFLAGS.VM is accompanied by a reload of SS
1480         * (caused by either a task switch or an inter-privilege IRET),
1481         * so we do not need to update the CPL here.
1482         */
1483         to_svm(vcpu)->vmcb->save.rflags = rflags;
1484 }
1485
1486 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1487 {
1488         switch (reg) {
1489         case VCPU_EXREG_PDPTR:
1490                 BUG_ON(!npt_enabled);
1491                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1492                 break;
1493         default:
1494                 WARN_ON_ONCE(1);
1495         }
1496 }
1497
1498 static void svm_set_vintr(struct vcpu_svm *svm)
1499 {
1500         struct vmcb_control_area *control;
1501
1502         /* The following fields are ignored when AVIC is enabled */
1503         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1504         svm_set_intercept(svm, INTERCEPT_VINTR);
1505
1506         /*
1507          * This is just a dummy VINTR to actually cause a vmexit to happen.
1508          * Actual injection of virtual interrupts happens through EVENTINJ.
1509          */
1510         control = &svm->vmcb->control;
1511         control->int_vector = 0x0;
1512         control->int_ctl &= ~V_INTR_PRIO_MASK;
1513         control->int_ctl |= V_IRQ_MASK |
1514                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1515         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1516 }
1517
1518 static void svm_clear_vintr(struct vcpu_svm *svm)
1519 {
1520         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1521         svm_clr_intercept(svm, INTERCEPT_VINTR);
1522
1523         /* Drop int_ctl fields related to VINTR injection.  */
1524         svm->vmcb->control.int_ctl &= mask;
1525         if (is_guest_mode(&svm->vcpu)) {
1526                 svm->nested.hsave->control.int_ctl &= mask;
1527
1528                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1529                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1530                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1531         }
1532
1533         vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1534 }
1535
1536 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1537 {
1538         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1539
1540         switch (seg) {
1541         case VCPU_SREG_CS: return &save->cs;
1542         case VCPU_SREG_DS: return &save->ds;
1543         case VCPU_SREG_ES: return &save->es;
1544         case VCPU_SREG_FS: return &save->fs;
1545         case VCPU_SREG_GS: return &save->gs;
1546         case VCPU_SREG_SS: return &save->ss;
1547         case VCPU_SREG_TR: return &save->tr;
1548         case VCPU_SREG_LDTR: return &save->ldtr;
1549         }
1550         BUG();
1551         return NULL;
1552 }
1553
1554 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1555 {
1556         struct vmcb_seg *s = svm_seg(vcpu, seg);
1557
1558         return s->base;
1559 }
1560
1561 static void svm_get_segment(struct kvm_vcpu *vcpu,
1562                             struct kvm_segment *var, int seg)
1563 {
1564         struct vmcb_seg *s = svm_seg(vcpu, seg);
1565
1566         var->base = s->base;
1567         var->limit = s->limit;
1568         var->selector = s->selector;
1569         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1570         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1571         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1572         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1573         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1574         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1575         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1576
1577         /*
1578          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1579          * However, the SVM spec states that the G bit is not observed by the
1580          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1581          * So let's synthesize a legal G bit for all segments, this helps
1582          * running KVM nested. It also helps cross-vendor migration, because
1583          * Intel's vmentry has a check on the 'G' bit.
1584          */
1585         var->g = s->limit > 0xfffff;
1586
1587         /*
1588          * AMD's VMCB does not have an explicit unusable field, so emulate it
1589          * for cross vendor migration purposes by "not present"
1590          */
1591         var->unusable = !var->present;
1592
1593         switch (seg) {
1594         case VCPU_SREG_TR:
1595                 /*
1596                  * Work around a bug where the busy flag in the tr selector
1597                  * isn't exposed
1598                  */
1599                 var->type |= 0x2;
1600                 break;
1601         case VCPU_SREG_DS:
1602         case VCPU_SREG_ES:
1603         case VCPU_SREG_FS:
1604         case VCPU_SREG_GS:
1605                 /*
1606                  * The accessed bit must always be set in the segment
1607                  * descriptor cache, although it can be cleared in the
1608                  * descriptor, the cached bit always remains at 1. Since
1609                  * Intel has a check on this, set it here to support
1610                  * cross-vendor migration.
1611                  */
1612                 if (!var->unusable)
1613                         var->type |= 0x1;
1614                 break;
1615         case VCPU_SREG_SS:
1616                 /*
1617                  * On AMD CPUs sometimes the DB bit in the segment
1618                  * descriptor is left as 1, although the whole segment has
1619                  * been made unusable. Clear it here to pass an Intel VMX
1620                  * entry check when cross vendor migrating.
1621                  */
1622                 if (var->unusable)
1623                         var->db = 0;
1624                 /* This is symmetric with svm_set_segment() */
1625                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1626                 break;
1627         }
1628 }
1629
1630 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1631 {
1632         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1633
1634         return save->cpl;
1635 }
1636
1637 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1638 {
1639         struct vcpu_svm *svm = to_svm(vcpu);
1640
1641         dt->size = svm->vmcb->save.idtr.limit;
1642         dt->address = svm->vmcb->save.idtr.base;
1643 }
1644
1645 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1646 {
1647         struct vcpu_svm *svm = to_svm(vcpu);
1648
1649         svm->vmcb->save.idtr.limit = dt->size;
1650         svm->vmcb->save.idtr.base = dt->address ;
1651         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1652 }
1653
1654 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1655 {
1656         struct vcpu_svm *svm = to_svm(vcpu);
1657
1658         dt->size = svm->vmcb->save.gdtr.limit;
1659         dt->address = svm->vmcb->save.gdtr.base;
1660 }
1661
1662 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1663 {
1664         struct vcpu_svm *svm = to_svm(vcpu);
1665
1666         svm->vmcb->save.gdtr.limit = dt->size;
1667         svm->vmcb->save.gdtr.base = dt->address ;
1668         vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1669 }
1670
1671 static void update_cr0_intercept(struct vcpu_svm *svm)
1672 {
1673         ulong gcr0;
1674         u64 *hcr0;
1675
1676         /*
1677          * SEV-ES guests must always keep the CR intercepts cleared. CR
1678          * tracking is done using the CR write traps.
1679          */
1680         if (sev_es_guest(svm->vcpu.kvm))
1681                 return;
1682
1683         gcr0 = svm->vcpu.arch.cr0;
1684         hcr0 = &svm->vmcb->save.cr0;
1685         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1686                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1687
1688         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1689
1690         if (gcr0 == *hcr0) {
1691                 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1692                 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1693         } else {
1694                 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1695                 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1696         }
1697 }
1698
1699 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1700 {
1701         struct vcpu_svm *svm = to_svm(vcpu);
1702
1703 #ifdef CONFIG_X86_64
1704         if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1705                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1706                         vcpu->arch.efer |= EFER_LMA;
1707                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1708                 }
1709
1710                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1711                         vcpu->arch.efer &= ~EFER_LMA;
1712                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1713                 }
1714         }
1715 #endif
1716         vcpu->arch.cr0 = cr0;
1717
1718         if (!npt_enabled)
1719                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1720
1721         /*
1722          * re-enable caching here because the QEMU bios
1723          * does not do it - this results in some delay at
1724          * reboot
1725          */
1726         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1727                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1728         svm->vmcb->save.cr0 = cr0;
1729         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1730         update_cr0_intercept(svm);
1731 }
1732
1733 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1734 {
1735         return true;
1736 }
1737
1738 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1739 {
1740         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1741         unsigned long old_cr4 = vcpu->arch.cr4;
1742
1743         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1744                 svm_flush_tlb(vcpu);
1745
1746         vcpu->arch.cr4 = cr4;
1747         if (!npt_enabled)
1748                 cr4 |= X86_CR4_PAE;
1749         cr4 |= host_cr4_mce;
1750         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1751         vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1752
1753         if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1754                 kvm_update_cpuid_runtime(vcpu);
1755 }
1756
1757 static void svm_set_segment(struct kvm_vcpu *vcpu,
1758                             struct kvm_segment *var, int seg)
1759 {
1760         struct vcpu_svm *svm = to_svm(vcpu);
1761         struct vmcb_seg *s = svm_seg(vcpu, seg);
1762
1763         s->base = var->base;
1764         s->limit = var->limit;
1765         s->selector = var->selector;
1766         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1767         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1768         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1769         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1770         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1771         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1772         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1773         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1774
1775         /*
1776          * This is always accurate, except if SYSRET returned to a segment
1777          * with SS.DPL != 3.  Intel does not have this quirk, and always
1778          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1779          * would entail passing the CPL to userspace and back.
1780          */
1781         if (seg == VCPU_SREG_SS)
1782                 /* This is symmetric with svm_get_segment() */
1783                 svm->vmcb->save.cpl = (var->dpl & 3);
1784
1785         vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1786 }
1787
1788 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1789 {
1790         struct vcpu_svm *svm = to_svm(vcpu);
1791
1792         clr_exception_intercept(svm, BP_VECTOR);
1793
1794         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1795                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1796                         set_exception_intercept(svm, BP_VECTOR);
1797         }
1798 }
1799
1800 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1801 {
1802         if (sd->next_asid > sd->max_asid) {
1803                 ++sd->asid_generation;
1804                 sd->next_asid = sd->min_asid;
1805                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1806                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1807         }
1808
1809         svm->asid_generation = sd->asid_generation;
1810         svm->asid = sd->next_asid++;
1811 }
1812
1813 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1814 {
1815         struct vmcb *vmcb = svm->vmcb;
1816
1817         if (svm->vcpu.arch.guest_state_protected)
1818                 return;
1819
1820         if (unlikely(value != vmcb->save.dr6)) {
1821                 vmcb->save.dr6 = value;
1822                 vmcb_mark_dirty(vmcb, VMCB_DR);
1823         }
1824 }
1825
1826 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1827 {
1828         struct vcpu_svm *svm = to_svm(vcpu);
1829
1830         if (vcpu->arch.guest_state_protected)
1831                 return;
1832
1833         get_debugreg(vcpu->arch.db[0], 0);
1834         get_debugreg(vcpu->arch.db[1], 1);
1835         get_debugreg(vcpu->arch.db[2], 2);
1836         get_debugreg(vcpu->arch.db[3], 3);
1837         /*
1838          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1839          * because db_interception might need it.  We can do it before vmentry.
1840          */
1841         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1842         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1843         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1844         set_dr_intercepts(svm);
1845 }
1846
1847 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1848 {
1849         struct vcpu_svm *svm = to_svm(vcpu);
1850
1851         if (vcpu->arch.guest_state_protected)
1852                 return;
1853
1854         svm->vmcb->save.dr7 = value;
1855         vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1856 }
1857
1858 static int pf_interception(struct vcpu_svm *svm)
1859 {
1860         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1861         u64 error_code = svm->vmcb->control.exit_info_1;
1862
1863         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1864                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1865                         svm->vmcb->control.insn_bytes : NULL,
1866                         svm->vmcb->control.insn_len);
1867 }
1868
1869 static int npf_interception(struct vcpu_svm *svm)
1870 {
1871         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1872         u64 error_code = svm->vmcb->control.exit_info_1;
1873
1874         trace_kvm_page_fault(fault_address, error_code);
1875         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1876                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1877                         svm->vmcb->control.insn_bytes : NULL,
1878                         svm->vmcb->control.insn_len);
1879 }
1880
1881 static int db_interception(struct vcpu_svm *svm)
1882 {
1883         struct kvm_run *kvm_run = svm->vcpu.run;
1884         struct kvm_vcpu *vcpu = &svm->vcpu;
1885
1886         if (!(svm->vcpu.guest_debug &
1887               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1888                 !svm->nmi_singlestep) {
1889                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1890                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1891                 return 1;
1892         }
1893
1894         if (svm->nmi_singlestep) {
1895                 disable_nmi_singlestep(svm);
1896                 /* Make sure we check for pending NMIs upon entry */
1897                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1898         }
1899
1900         if (svm->vcpu.guest_debug &
1901             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1902                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1903                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1904                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1905                 kvm_run->debug.arch.pc =
1906                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1907                 kvm_run->debug.arch.exception = DB_VECTOR;
1908                 return 0;
1909         }
1910
1911         return 1;
1912 }
1913
1914 static int bp_interception(struct vcpu_svm *svm)
1915 {
1916         struct kvm_run *kvm_run = svm->vcpu.run;
1917
1918         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1919         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1920         kvm_run->debug.arch.exception = BP_VECTOR;
1921         return 0;
1922 }
1923
1924 static int ud_interception(struct vcpu_svm *svm)
1925 {
1926         return handle_ud(&svm->vcpu);
1927 }
1928
1929 static int ac_interception(struct vcpu_svm *svm)
1930 {
1931         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1932         return 1;
1933 }
1934
1935 static int gp_interception(struct vcpu_svm *svm)
1936 {
1937         struct kvm_vcpu *vcpu = &svm->vcpu;
1938         u32 error_code = svm->vmcb->control.exit_info_1;
1939
1940         WARN_ON_ONCE(!enable_vmware_backdoor);
1941
1942         /*
1943          * VMware backdoor emulation on #GP interception only handles IN{S},
1944          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1945          */
1946         if (error_code) {
1947                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1948                 return 1;
1949         }
1950         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1951 }
1952
1953 static bool is_erratum_383(void)
1954 {
1955         int err, i;
1956         u64 value;
1957
1958         if (!erratum_383_found)
1959                 return false;
1960
1961         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1962         if (err)
1963                 return false;
1964
1965         /* Bit 62 may or may not be set for this mce */
1966         value &= ~(1ULL << 62);
1967
1968         if (value != 0xb600000000010015ULL)
1969                 return false;
1970
1971         /* Clear MCi_STATUS registers */
1972         for (i = 0; i < 6; ++i)
1973                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1974
1975         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1976         if (!err) {
1977                 u32 low, high;
1978
1979                 value &= ~(1ULL << 2);
1980                 low    = lower_32_bits(value);
1981                 high   = upper_32_bits(value);
1982
1983                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1984         }
1985
1986         /* Flush tlb to evict multi-match entries */
1987         __flush_tlb_all();
1988
1989         return true;
1990 }
1991
1992 static void svm_handle_mce(struct vcpu_svm *svm)
1993 {
1994         if (is_erratum_383()) {
1995                 /*
1996                  * Erratum 383 triggered. Guest state is corrupt so kill the
1997                  * guest.
1998                  */
1999                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2000
2001                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
2002
2003                 return;
2004         }
2005
2006         /*
2007          * On an #MC intercept the MCE handler is not called automatically in
2008          * the host. So do it by hand here.
2009          */
2010         kvm_machine_check();
2011 }
2012
2013 static int mc_interception(struct vcpu_svm *svm)
2014 {
2015         return 1;
2016 }
2017
2018 static int shutdown_interception(struct vcpu_svm *svm)
2019 {
2020         struct kvm_run *kvm_run = svm->vcpu.run;
2021
2022         /*
2023          * The VM save area has already been encrypted so it
2024          * cannot be reinitialized - just terminate.
2025          */
2026         if (sev_es_guest(svm->vcpu.kvm))
2027                 return -EINVAL;
2028
2029         /*
2030          * VMCB is undefined after a SHUTDOWN intercept
2031          * so reinitialize it.
2032          */
2033         clear_page(svm->vmcb);
2034         init_vmcb(svm);
2035
2036         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2037         return 0;
2038 }
2039
2040 static int io_interception(struct vcpu_svm *svm)
2041 {
2042         struct kvm_vcpu *vcpu = &svm->vcpu;
2043         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2044         int size, in, string;
2045         unsigned port;
2046
2047         ++svm->vcpu.stat.io_exits;
2048         string = (io_info & SVM_IOIO_STR_MASK) != 0;
2049         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2050         port = io_info >> 16;
2051         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2052
2053         if (string) {
2054                 if (sev_es_guest(vcpu->kvm))
2055                         return sev_es_string_io(svm, size, port, in);
2056                 else
2057                         return kvm_emulate_instruction(vcpu, 0);
2058         }
2059
2060         svm->next_rip = svm->vmcb->control.exit_info_2;
2061
2062         return kvm_fast_pio(&svm->vcpu, size, port, in);
2063 }
2064
2065 static int nmi_interception(struct vcpu_svm *svm)
2066 {
2067         return 1;
2068 }
2069
2070 static int intr_interception(struct vcpu_svm *svm)
2071 {
2072         ++svm->vcpu.stat.irq_exits;
2073         return 1;
2074 }
2075
2076 static int nop_on_interception(struct vcpu_svm *svm)
2077 {
2078         return 1;
2079 }
2080
2081 static int halt_interception(struct vcpu_svm *svm)
2082 {
2083         return kvm_emulate_halt(&svm->vcpu);
2084 }
2085
2086 static int vmmcall_interception(struct vcpu_svm *svm)
2087 {
2088         return kvm_emulate_hypercall(&svm->vcpu);
2089 }
2090
2091 static int vmload_interception(struct vcpu_svm *svm)
2092 {
2093         struct vmcb *nested_vmcb;
2094         struct kvm_host_map map;
2095         int ret;
2096
2097         if (nested_svm_check_permissions(svm))
2098                 return 1;
2099
2100         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2101         if (ret) {
2102                 if (ret == -EINVAL)
2103                         kvm_inject_gp(&svm->vcpu, 0);
2104                 return 1;
2105         }
2106
2107         nested_vmcb = map.hva;
2108
2109         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2110
2111         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2112         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2113
2114         return ret;
2115 }
2116
2117 static int vmsave_interception(struct vcpu_svm *svm)
2118 {
2119         struct vmcb *nested_vmcb;
2120         struct kvm_host_map map;
2121         int ret;
2122
2123         if (nested_svm_check_permissions(svm))
2124                 return 1;
2125
2126         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2127         if (ret) {
2128                 if (ret == -EINVAL)
2129                         kvm_inject_gp(&svm->vcpu, 0);
2130                 return 1;
2131         }
2132
2133         nested_vmcb = map.hva;
2134
2135         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2136
2137         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2138         kvm_vcpu_unmap(&svm->vcpu, &map, true);
2139
2140         return ret;
2141 }
2142
2143 static int vmrun_interception(struct vcpu_svm *svm)
2144 {
2145         if (nested_svm_check_permissions(svm))
2146                 return 1;
2147
2148         return nested_svm_vmrun(svm);
2149 }
2150
2151 void svm_set_gif(struct vcpu_svm *svm, bool value)
2152 {
2153         if (value) {
2154                 /*
2155                  * If VGIF is enabled, the STGI intercept is only added to
2156                  * detect the opening of the SMI/NMI window; remove it now.
2157                  * Likewise, clear the VINTR intercept, we will set it
2158                  * again while processing KVM_REQ_EVENT if needed.
2159                  */
2160                 if (vgif_enabled(svm))
2161                         svm_clr_intercept(svm, INTERCEPT_STGI);
2162                 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2163                         svm_clear_vintr(svm);
2164
2165                 enable_gif(svm);
2166                 if (svm->vcpu.arch.smi_pending ||
2167                     svm->vcpu.arch.nmi_pending ||
2168                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2169                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2170         } else {
2171                 disable_gif(svm);
2172
2173                 /*
2174                  * After a CLGI no interrupts should come.  But if vGIF is
2175                  * in use, we still rely on the VINTR intercept (rather than
2176                  * STGI) to detect an open interrupt window.
2177                 */
2178                 if (!vgif_enabled(svm))
2179                         svm_clear_vintr(svm);
2180         }
2181 }
2182
2183 static int stgi_interception(struct vcpu_svm *svm)
2184 {
2185         int ret;
2186
2187         if (nested_svm_check_permissions(svm))
2188                 return 1;
2189
2190         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2191         svm_set_gif(svm, true);
2192         return ret;
2193 }
2194
2195 static int clgi_interception(struct vcpu_svm *svm)
2196 {
2197         int ret;
2198
2199         if (nested_svm_check_permissions(svm))
2200                 return 1;
2201
2202         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2203         svm_set_gif(svm, false);
2204         return ret;
2205 }
2206
2207 static int invlpga_interception(struct vcpu_svm *svm)
2208 {
2209         struct kvm_vcpu *vcpu = &svm->vcpu;
2210
2211         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2212                           kvm_rax_read(&svm->vcpu));
2213
2214         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2215         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2216
2217         return kvm_skip_emulated_instruction(&svm->vcpu);
2218 }
2219
2220 static int skinit_interception(struct vcpu_svm *svm)
2221 {
2222         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2223
2224         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2225         return 1;
2226 }
2227
2228 static int wbinvd_interception(struct vcpu_svm *svm)
2229 {
2230         return kvm_emulate_wbinvd(&svm->vcpu);
2231 }
2232
2233 static int xsetbv_interception(struct vcpu_svm *svm)
2234 {
2235         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2236         u32 index = kvm_rcx_read(&svm->vcpu);
2237
2238         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2239                 return kvm_skip_emulated_instruction(&svm->vcpu);
2240         }
2241
2242         return 1;
2243 }
2244
2245 static int rdpru_interception(struct vcpu_svm *svm)
2246 {
2247         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2248         return 1;
2249 }
2250
2251 static int task_switch_interception(struct vcpu_svm *svm)
2252 {
2253         u16 tss_selector;
2254         int reason;
2255         int int_type = svm->vmcb->control.exit_int_info &
2256                 SVM_EXITINTINFO_TYPE_MASK;
2257         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2258         uint32_t type =
2259                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2260         uint32_t idt_v =
2261                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2262         bool has_error_code = false;
2263         u32 error_code = 0;
2264
2265         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2266
2267         if (svm->vmcb->control.exit_info_2 &
2268             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2269                 reason = TASK_SWITCH_IRET;
2270         else if (svm->vmcb->control.exit_info_2 &
2271                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2272                 reason = TASK_SWITCH_JMP;
2273         else if (idt_v)
2274                 reason = TASK_SWITCH_GATE;
2275         else
2276                 reason = TASK_SWITCH_CALL;
2277
2278         if (reason == TASK_SWITCH_GATE) {
2279                 switch (type) {
2280                 case SVM_EXITINTINFO_TYPE_NMI:
2281                         svm->vcpu.arch.nmi_injected = false;
2282                         break;
2283                 case SVM_EXITINTINFO_TYPE_EXEPT:
2284                         if (svm->vmcb->control.exit_info_2 &
2285                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2286                                 has_error_code = true;
2287                                 error_code =
2288                                         (u32)svm->vmcb->control.exit_info_2;
2289                         }
2290                         kvm_clear_exception_queue(&svm->vcpu);
2291                         break;
2292                 case SVM_EXITINTINFO_TYPE_INTR:
2293                         kvm_clear_interrupt_queue(&svm->vcpu);
2294                         break;
2295                 default:
2296                         break;
2297                 }
2298         }
2299
2300         if (reason != TASK_SWITCH_GATE ||
2301             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2302             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2303              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2304                 if (!skip_emulated_instruction(&svm->vcpu))
2305                         return 0;
2306         }
2307
2308         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2309                 int_vec = -1;
2310
2311         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2312                                has_error_code, error_code);
2313 }
2314
2315 static int cpuid_interception(struct vcpu_svm *svm)
2316 {
2317         return kvm_emulate_cpuid(&svm->vcpu);
2318 }
2319
2320 static int iret_interception(struct vcpu_svm *svm)
2321 {
2322         ++svm->vcpu.stat.nmi_window_exits;
2323         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2324         if (!sev_es_guest(svm->vcpu.kvm)) {
2325                 svm_clr_intercept(svm, INTERCEPT_IRET);
2326                 svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2327         }
2328         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2329         return 1;
2330 }
2331
2332 static int invd_interception(struct vcpu_svm *svm)
2333 {
2334         /* Treat an INVD instruction as a NOP and just skip it. */
2335         return kvm_skip_emulated_instruction(&svm->vcpu);
2336 }
2337
2338 static int invlpg_interception(struct vcpu_svm *svm)
2339 {
2340         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2341                 return kvm_emulate_instruction(&svm->vcpu, 0);
2342
2343         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2344         return kvm_skip_emulated_instruction(&svm->vcpu);
2345 }
2346
2347 static int emulate_on_interception(struct vcpu_svm *svm)
2348 {
2349         return kvm_emulate_instruction(&svm->vcpu, 0);
2350 }
2351
2352 static int rsm_interception(struct vcpu_svm *svm)
2353 {
2354         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2355 }
2356
2357 static int rdpmc_interception(struct vcpu_svm *svm)
2358 {
2359         int err;
2360
2361         if (!nrips)
2362                 return emulate_on_interception(svm);
2363
2364         err = kvm_rdpmc(&svm->vcpu);
2365         return kvm_complete_insn_gp(&svm->vcpu, err);
2366 }
2367
2368 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2369                                             unsigned long val)
2370 {
2371         unsigned long cr0 = svm->vcpu.arch.cr0;
2372         bool ret = false;
2373
2374         if (!is_guest_mode(&svm->vcpu) ||
2375             (!(vmcb_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2376                 return false;
2377
2378         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2379         val &= ~SVM_CR0_SELECTIVE_MASK;
2380
2381         if (cr0 ^ val) {
2382                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2383                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2384         }
2385
2386         return ret;
2387 }
2388
2389 #define CR_VALID (1ULL << 63)
2390
2391 static int cr_interception(struct vcpu_svm *svm)
2392 {
2393         int reg, cr;
2394         unsigned long val;
2395         int err;
2396
2397         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2398                 return emulate_on_interception(svm);
2399
2400         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2401                 return emulate_on_interception(svm);
2402
2403         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2404         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2405                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2406         else
2407                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2408
2409         err = 0;
2410         if (cr >= 16) { /* mov to cr */
2411                 cr -= 16;
2412                 val = kvm_register_read(&svm->vcpu, reg);
2413                 trace_kvm_cr_write(cr, val);
2414                 switch (cr) {
2415                 case 0:
2416                         if (!check_selective_cr0_intercepted(svm, val))
2417                                 err = kvm_set_cr0(&svm->vcpu, val);
2418                         else
2419                                 return 1;
2420
2421                         break;
2422                 case 3:
2423                         err = kvm_set_cr3(&svm->vcpu, val);
2424                         break;
2425                 case 4:
2426                         err = kvm_set_cr4(&svm->vcpu, val);
2427                         break;
2428                 case 8:
2429                         err = kvm_set_cr8(&svm->vcpu, val);
2430                         break;
2431                 default:
2432                         WARN(1, "unhandled write to CR%d", cr);
2433                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2434                         return 1;
2435                 }
2436         } else { /* mov from cr */
2437                 switch (cr) {
2438                 case 0:
2439                         val = kvm_read_cr0(&svm->vcpu);
2440                         break;
2441                 case 2:
2442                         val = svm->vcpu.arch.cr2;
2443                         break;
2444                 case 3:
2445                         val = kvm_read_cr3(&svm->vcpu);
2446                         break;
2447                 case 4:
2448                         val = kvm_read_cr4(&svm->vcpu);
2449                         break;
2450                 case 8:
2451                         val = kvm_get_cr8(&svm->vcpu);
2452                         break;
2453                 default:
2454                         WARN(1, "unhandled read from CR%d", cr);
2455                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2456                         return 1;
2457                 }
2458                 kvm_register_write(&svm->vcpu, reg, val);
2459                 trace_kvm_cr_read(cr, val);
2460         }
2461         return kvm_complete_insn_gp(&svm->vcpu, err);
2462 }
2463
2464 static int cr_trap(struct vcpu_svm *svm)
2465 {
2466         struct kvm_vcpu *vcpu = &svm->vcpu;
2467         unsigned long old_value, new_value;
2468         unsigned int cr;
2469         int ret = 0;
2470
2471         new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2472
2473         cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2474         switch (cr) {
2475         case 0:
2476                 old_value = kvm_read_cr0(vcpu);
2477                 svm_set_cr0(vcpu, new_value);
2478
2479                 kvm_post_set_cr0(vcpu, old_value, new_value);
2480                 break;
2481         case 4:
2482                 old_value = kvm_read_cr4(vcpu);
2483                 svm_set_cr4(vcpu, new_value);
2484
2485                 kvm_post_set_cr4(vcpu, old_value, new_value);
2486                 break;
2487         case 8:
2488                 ret = kvm_set_cr8(&svm->vcpu, new_value);
2489                 break;
2490         default:
2491                 WARN(1, "unhandled CR%d write trap", cr);
2492                 kvm_queue_exception(vcpu, UD_VECTOR);
2493                 return 1;
2494         }
2495
2496         return kvm_complete_insn_gp(vcpu, ret);
2497 }
2498
2499 static int dr_interception(struct vcpu_svm *svm)
2500 {
2501         int reg, dr;
2502         unsigned long val;
2503
2504         if (svm->vcpu.guest_debug == 0) {
2505                 /*
2506                  * No more DR vmexits; force a reload of the debug registers
2507                  * and reenter on this instruction.  The next vmexit will
2508                  * retrieve the full state of the debug registers.
2509                  */
2510                 clr_dr_intercepts(svm);
2511                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2512                 return 1;
2513         }
2514
2515         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2516                 return emulate_on_interception(svm);
2517
2518         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2519         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2520
2521         if (dr >= 16) { /* mov to DRn */
2522                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2523                         return 1;
2524                 val = kvm_register_read(&svm->vcpu, reg);
2525                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2526         } else {
2527                 if (!kvm_require_dr(&svm->vcpu, dr))
2528                         return 1;
2529                 kvm_get_dr(&svm->vcpu, dr, &val);
2530                 kvm_register_write(&svm->vcpu, reg, val);
2531         }
2532
2533         return kvm_skip_emulated_instruction(&svm->vcpu);
2534 }
2535
2536 static int cr8_write_interception(struct vcpu_svm *svm)
2537 {
2538         struct kvm_run *kvm_run = svm->vcpu.run;
2539         int r;
2540
2541         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2542         /* instruction emulation calls kvm_set_cr8() */
2543         r = cr_interception(svm);
2544         if (lapic_in_kernel(&svm->vcpu))
2545                 return r;
2546         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2547                 return r;
2548         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2549         return 0;
2550 }
2551
2552 static int efer_trap(struct vcpu_svm *svm)
2553 {
2554         struct msr_data msr_info;
2555         int ret;
2556
2557         /*
2558          * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2559          * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2560          * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2561          * the guest doesn't have X86_FEATURE_SVM.
2562          */
2563         msr_info.host_initiated = false;
2564         msr_info.index = MSR_EFER;
2565         msr_info.data = svm->vmcb->control.exit_info_1 & ~EFER_SVME;
2566         ret = kvm_set_msr_common(&svm->vcpu, &msr_info);
2567
2568         return kvm_complete_insn_gp(&svm->vcpu, ret);
2569 }
2570
2571 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2572 {
2573         msr->data = 0;
2574
2575         switch (msr->index) {
2576         case MSR_F10H_DECFG:
2577                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2578                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2579                 break;
2580         case MSR_IA32_PERF_CAPABILITIES:
2581                 return 0;
2582         default:
2583                 return KVM_MSR_RET_INVALID;
2584         }
2585
2586         return 0;
2587 }
2588
2589 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2590 {
2591         struct vcpu_svm *svm = to_svm(vcpu);
2592
2593         switch (msr_info->index) {
2594         case MSR_STAR:
2595                 msr_info->data = svm->vmcb->save.star;
2596                 break;
2597 #ifdef CONFIG_X86_64
2598         case MSR_LSTAR:
2599                 msr_info->data = svm->vmcb->save.lstar;
2600                 break;
2601         case MSR_CSTAR:
2602                 msr_info->data = svm->vmcb->save.cstar;
2603                 break;
2604         case MSR_KERNEL_GS_BASE:
2605                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2606                 break;
2607         case MSR_SYSCALL_MASK:
2608                 msr_info->data = svm->vmcb->save.sfmask;
2609                 break;
2610 #endif
2611         case MSR_IA32_SYSENTER_CS:
2612                 msr_info->data = svm->vmcb->save.sysenter_cs;
2613                 break;
2614         case MSR_IA32_SYSENTER_EIP:
2615                 msr_info->data = svm->sysenter_eip;
2616                 break;
2617         case MSR_IA32_SYSENTER_ESP:
2618                 msr_info->data = svm->sysenter_esp;
2619                 break;
2620         case MSR_TSC_AUX:
2621                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2622                         return 1;
2623                 msr_info->data = svm->tsc_aux;
2624                 break;
2625         /*
2626          * Nobody will change the following 5 values in the VMCB so we can
2627          * safely return them on rdmsr. They will always be 0 until LBRV is
2628          * implemented.
2629          */
2630         case MSR_IA32_DEBUGCTLMSR:
2631                 msr_info->data = svm->vmcb->save.dbgctl;
2632                 break;
2633         case MSR_IA32_LASTBRANCHFROMIP:
2634                 msr_info->data = svm->vmcb->save.br_from;
2635                 break;
2636         case MSR_IA32_LASTBRANCHTOIP:
2637                 msr_info->data = svm->vmcb->save.br_to;
2638                 break;
2639         case MSR_IA32_LASTINTFROMIP:
2640                 msr_info->data = svm->vmcb->save.last_excp_from;
2641                 break;
2642         case MSR_IA32_LASTINTTOIP:
2643                 msr_info->data = svm->vmcb->save.last_excp_to;
2644                 break;
2645         case MSR_VM_HSAVE_PA:
2646                 msr_info->data = svm->nested.hsave_msr;
2647                 break;
2648         case MSR_VM_CR:
2649                 msr_info->data = svm->nested.vm_cr_msr;
2650                 break;
2651         case MSR_IA32_SPEC_CTRL:
2652                 if (!msr_info->host_initiated &&
2653                     !guest_has_spec_ctrl_msr(vcpu))
2654                         return 1;
2655
2656                 msr_info->data = svm->spec_ctrl;
2657                 break;
2658         case MSR_AMD64_VIRT_SPEC_CTRL:
2659                 if (!msr_info->host_initiated &&
2660                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2661                         return 1;
2662
2663                 msr_info->data = svm->virt_spec_ctrl;
2664                 break;
2665         case MSR_F15H_IC_CFG: {
2666
2667                 int family, model;
2668
2669                 family = guest_cpuid_family(vcpu);
2670                 model  = guest_cpuid_model(vcpu);
2671
2672                 if (family < 0 || model < 0)
2673                         return kvm_get_msr_common(vcpu, msr_info);
2674
2675                 msr_info->data = 0;
2676
2677                 if (family == 0x15 &&
2678                     (model >= 0x2 && model < 0x20))
2679                         msr_info->data = 0x1E;
2680                 }
2681                 break;
2682         case MSR_F10H_DECFG:
2683                 msr_info->data = svm->msr_decfg;
2684                 break;
2685         default:
2686                 return kvm_get_msr_common(vcpu, msr_info);
2687         }
2688         return 0;
2689 }
2690
2691 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2692 {
2693         struct vcpu_svm *svm = to_svm(vcpu);
2694         if (!sev_es_guest(svm->vcpu.kvm) || !err)
2695                 return kvm_complete_insn_gp(&svm->vcpu, err);
2696
2697         ghcb_set_sw_exit_info_1(svm->ghcb, 1);
2698         ghcb_set_sw_exit_info_2(svm->ghcb,
2699                                 X86_TRAP_GP |
2700                                 SVM_EVTINJ_TYPE_EXEPT |
2701                                 SVM_EVTINJ_VALID);
2702         return 1;
2703 }
2704
2705 static int rdmsr_interception(struct vcpu_svm *svm)
2706 {
2707         return kvm_emulate_rdmsr(&svm->vcpu);
2708 }
2709
2710 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2711 {
2712         struct vcpu_svm *svm = to_svm(vcpu);
2713         int svm_dis, chg_mask;
2714
2715         if (data & ~SVM_VM_CR_VALID_MASK)
2716                 return 1;
2717
2718         chg_mask = SVM_VM_CR_VALID_MASK;
2719
2720         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2721                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2722
2723         svm->nested.vm_cr_msr &= ~chg_mask;
2724         svm->nested.vm_cr_msr |= (data & chg_mask);
2725
2726         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2727
2728         /* check for svm_disable while efer.svme is set */
2729         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2730                 return 1;
2731
2732         return 0;
2733 }
2734
2735 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2736 {
2737         struct vcpu_svm *svm = to_svm(vcpu);
2738
2739         u32 ecx = msr->index;
2740         u64 data = msr->data;
2741         switch (ecx) {
2742         case MSR_IA32_CR_PAT:
2743                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2744                         return 1;
2745                 vcpu->arch.pat = data;
2746                 svm->vmcb->save.g_pat = data;
2747                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2748                 break;
2749         case MSR_IA32_SPEC_CTRL:
2750                 if (!msr->host_initiated &&
2751                     !guest_has_spec_ctrl_msr(vcpu))
2752                         return 1;
2753
2754                 if (kvm_spec_ctrl_test_value(data))
2755                         return 1;
2756
2757                 svm->spec_ctrl = data;
2758                 if (!data)
2759                         break;
2760
2761                 /*
2762                  * For non-nested:
2763                  * When it's written (to non-zero) for the first time, pass
2764                  * it through.
2765                  *
2766                  * For nested:
2767                  * The handling of the MSR bitmap for L2 guests is done in
2768                  * nested_svm_vmrun_msrpm.
2769                  * We update the L1 MSR bit as well since it will end up
2770                  * touching the MSR anyway now.
2771                  */
2772                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2773                 break;
2774         case MSR_IA32_PRED_CMD:
2775                 if (!msr->host_initiated &&
2776                     !guest_has_pred_cmd_msr(vcpu))
2777                         return 1;
2778
2779                 if (data & ~PRED_CMD_IBPB)
2780                         return 1;
2781                 if (!boot_cpu_has(X86_FEATURE_IBPB))
2782                         return 1;
2783                 if (!data)
2784                         break;
2785
2786                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2787                 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2788                 break;
2789         case MSR_AMD64_VIRT_SPEC_CTRL:
2790                 if (!msr->host_initiated &&
2791                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2792                         return 1;
2793
2794                 if (data & ~SPEC_CTRL_SSBD)
2795                         return 1;
2796
2797                 svm->virt_spec_ctrl = data;
2798                 break;
2799         case MSR_STAR:
2800                 svm->vmcb->save.star = data;
2801                 break;
2802 #ifdef CONFIG_X86_64
2803         case MSR_LSTAR:
2804                 svm->vmcb->save.lstar = data;
2805                 break;
2806         case MSR_CSTAR:
2807                 svm->vmcb->save.cstar = data;
2808                 break;
2809         case MSR_KERNEL_GS_BASE:
2810                 svm->vmcb->save.kernel_gs_base = data;
2811                 break;
2812         case MSR_SYSCALL_MASK:
2813                 svm->vmcb->save.sfmask = data;
2814                 break;
2815 #endif
2816         case MSR_IA32_SYSENTER_CS:
2817                 svm->vmcb->save.sysenter_cs = data;
2818                 break;
2819         case MSR_IA32_SYSENTER_EIP:
2820                 svm->sysenter_eip = data;
2821                 svm->vmcb->save.sysenter_eip = data;
2822                 break;
2823         case MSR_IA32_SYSENTER_ESP:
2824                 svm->sysenter_esp = data;
2825                 svm->vmcb->save.sysenter_esp = data;
2826                 break;
2827         case MSR_TSC_AUX:
2828                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2829                         return 1;
2830
2831                 /*
2832                  * This is rare, so we update the MSR here instead of using
2833                  * direct_access_msrs.  Doing that would require a rdmsr in
2834                  * svm_vcpu_put.
2835                  */
2836                 svm->tsc_aux = data;
2837                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2838                 break;
2839         case MSR_IA32_DEBUGCTLMSR:
2840                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2841                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2842                                     __func__, data);
2843                         break;
2844                 }
2845                 if (data & DEBUGCTL_RESERVED_BITS)
2846                         return 1;
2847
2848                 svm->vmcb->save.dbgctl = data;
2849                 vmcb_mark_dirty(svm->vmcb, VMCB_LBR);
2850                 if (data & (1ULL<<0))
2851                         svm_enable_lbrv(vcpu);
2852                 else
2853                         svm_disable_lbrv(vcpu);
2854                 break;
2855         case MSR_VM_HSAVE_PA:
2856                 svm->nested.hsave_msr = data;
2857                 break;
2858         case MSR_VM_CR:
2859                 return svm_set_vm_cr(vcpu, data);
2860         case MSR_VM_IGNNE:
2861                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2862                 break;
2863         case MSR_F10H_DECFG: {
2864                 struct kvm_msr_entry msr_entry;
2865
2866                 msr_entry.index = msr->index;
2867                 if (svm_get_msr_feature(&msr_entry))
2868                         return 1;
2869
2870                 /* Check the supported bits */
2871                 if (data & ~msr_entry.data)
2872                         return 1;
2873
2874                 /* Don't allow the guest to change a bit, #GP */
2875                 if (!msr->host_initiated && (data ^ msr_entry.data))
2876                         return 1;
2877
2878                 svm->msr_decfg = data;
2879                 break;
2880         }
2881         case MSR_IA32_APICBASE:
2882                 if (kvm_vcpu_apicv_active(vcpu))
2883                         avic_update_vapic_bar(to_svm(vcpu), data);
2884                 fallthrough;
2885         default:
2886                 return kvm_set_msr_common(vcpu, msr);
2887         }
2888         return 0;
2889 }
2890
2891 static int wrmsr_interception(struct vcpu_svm *svm)
2892 {
2893         return kvm_emulate_wrmsr(&svm->vcpu);
2894 }
2895
2896 static int msr_interception(struct vcpu_svm *svm)
2897 {
2898         if (svm->vmcb->control.exit_info_1)
2899                 return wrmsr_interception(svm);
2900         else
2901                 return rdmsr_interception(svm);
2902 }
2903
2904 static int interrupt_window_interception(struct vcpu_svm *svm)
2905 {
2906         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2907         svm_clear_vintr(svm);
2908
2909         /*
2910          * For AVIC, the only reason to end up here is ExtINTs.
2911          * In this case AVIC was temporarily disabled for
2912          * requesting the IRQ window and we have to re-enable it.
2913          */
2914         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2915
2916         ++svm->vcpu.stat.irq_window_exits;
2917         return 1;
2918 }
2919
2920 static int pause_interception(struct vcpu_svm *svm)
2921 {
2922         struct kvm_vcpu *vcpu = &svm->vcpu;
2923         bool in_kernel;
2924
2925         /*
2926          * CPL is not made available for an SEV-ES guest, therefore
2927          * vcpu->arch.preempted_in_kernel can never be true.  Just
2928          * set in_kernel to false as well.
2929          */
2930         in_kernel = !sev_es_guest(svm->vcpu.kvm) && svm_get_cpl(vcpu) == 0;
2931
2932         if (!kvm_pause_in_guest(vcpu->kvm))
2933                 grow_ple_window(vcpu);
2934
2935         kvm_vcpu_on_spin(vcpu, in_kernel);
2936         return 1;
2937 }
2938
2939 static int nop_interception(struct vcpu_svm *svm)
2940 {
2941         return kvm_skip_emulated_instruction(&(svm->vcpu));
2942 }
2943
2944 static int monitor_interception(struct vcpu_svm *svm)
2945 {
2946         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2947         return nop_interception(svm);
2948 }
2949
2950 static int mwait_interception(struct vcpu_svm *svm)
2951 {
2952         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2953         return nop_interception(svm);
2954 }
2955
2956 static int invpcid_interception(struct vcpu_svm *svm)
2957 {
2958         struct kvm_vcpu *vcpu = &svm->vcpu;
2959         unsigned long type;
2960         gva_t gva;
2961
2962         if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
2963                 kvm_queue_exception(vcpu, UD_VECTOR);
2964                 return 1;
2965         }
2966
2967         /*
2968          * For an INVPCID intercept:
2969          * EXITINFO1 provides the linear address of the memory operand.
2970          * EXITINFO2 provides the contents of the register operand.
2971          */
2972         type = svm->vmcb->control.exit_info_2;
2973         gva = svm->vmcb->control.exit_info_1;
2974
2975         if (type > 3) {
2976                 kvm_inject_gp(vcpu, 0);
2977                 return 1;
2978         }
2979
2980         return kvm_handle_invpcid(vcpu, type, gva);
2981 }
2982
2983 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2984         [SVM_EXIT_READ_CR0]                     = cr_interception,
2985         [SVM_EXIT_READ_CR3]                     = cr_interception,
2986         [SVM_EXIT_READ_CR4]                     = cr_interception,
2987         [SVM_EXIT_READ_CR8]                     = cr_interception,
2988         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2989         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2990         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2991         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2992         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2993         [SVM_EXIT_READ_DR0]                     = dr_interception,
2994         [SVM_EXIT_READ_DR1]                     = dr_interception,
2995         [SVM_EXIT_READ_DR2]                     = dr_interception,
2996         [SVM_EXIT_READ_DR3]                     = dr_interception,
2997         [SVM_EXIT_READ_DR4]                     = dr_interception,
2998         [SVM_EXIT_READ_DR5]                     = dr_interception,
2999         [SVM_EXIT_READ_DR6]                     = dr_interception,
3000         [SVM_EXIT_READ_DR7]                     = dr_interception,
3001         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
3002         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
3003         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
3004         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
3005         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
3006         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
3007         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
3008         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
3009         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
3010         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
3011         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
3012         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
3013         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
3014         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
3015         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
3016         [SVM_EXIT_INTR]                         = intr_interception,
3017         [SVM_EXIT_NMI]                          = nmi_interception,
3018         [SVM_EXIT_SMI]                          = nop_on_interception,
3019         [SVM_EXIT_INIT]                         = nop_on_interception,
3020         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
3021         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
3022         [SVM_EXIT_CPUID]                        = cpuid_interception,
3023         [SVM_EXIT_IRET]                         = iret_interception,
3024         [SVM_EXIT_INVD]                         = invd_interception,
3025         [SVM_EXIT_PAUSE]                        = pause_interception,
3026         [SVM_EXIT_HLT]                          = halt_interception,
3027         [SVM_EXIT_INVLPG]                       = invlpg_interception,
3028         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
3029         [SVM_EXIT_IOIO]                         = io_interception,
3030         [SVM_EXIT_MSR]                          = msr_interception,
3031         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
3032         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
3033         [SVM_EXIT_VMRUN]                        = vmrun_interception,
3034         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
3035         [SVM_EXIT_VMLOAD]                       = vmload_interception,
3036         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
3037         [SVM_EXIT_STGI]                         = stgi_interception,
3038         [SVM_EXIT_CLGI]                         = clgi_interception,
3039         [SVM_EXIT_SKINIT]                       = skinit_interception,
3040         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
3041         [SVM_EXIT_MONITOR]                      = monitor_interception,
3042         [SVM_EXIT_MWAIT]                        = mwait_interception,
3043         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
3044         [SVM_EXIT_RDPRU]                        = rdpru_interception,
3045         [SVM_EXIT_EFER_WRITE_TRAP]              = efer_trap,
3046         [SVM_EXIT_CR0_WRITE_TRAP]               = cr_trap,
3047         [SVM_EXIT_CR4_WRITE_TRAP]               = cr_trap,
3048         [SVM_EXIT_CR8_WRITE_TRAP]               = cr_trap,
3049         [SVM_EXIT_INVPCID]                      = invpcid_interception,
3050         [SVM_EXIT_NPF]                          = npf_interception,
3051         [SVM_EXIT_RSM]                          = rsm_interception,
3052         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
3053         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
3054         [SVM_EXIT_VMGEXIT]                      = sev_handle_vmgexit,
3055 };
3056
3057 static void dump_vmcb(struct kvm_vcpu *vcpu)
3058 {
3059         struct vcpu_svm *svm = to_svm(vcpu);
3060         struct vmcb_control_area *control = &svm->vmcb->control;
3061         struct vmcb_save_area *save = &svm->vmcb->save;
3062
3063         if (!dump_invalid_vmcb) {
3064                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3065                 return;
3066         }
3067
3068         pr_err("VMCB Control Area:\n");
3069         pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3070         pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3071         pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3072         pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3073         pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3074         pr_err("%-20s%08x %08x\n", "intercepts:",
3075               control->intercepts[INTERCEPT_WORD3],
3076                control->intercepts[INTERCEPT_WORD4]);
3077         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3078         pr_err("%-20s%d\n", "pause filter threshold:",
3079                control->pause_filter_thresh);
3080         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3081         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3082         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3083         pr_err("%-20s%d\n", "asid:", control->asid);
3084         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3085         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3086         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3087         pr_err("%-20s%08x\n", "int_state:", control->int_state);
3088         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3089         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3090         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3091         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3092         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3093         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3094         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3095         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3096         pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3097         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3098         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3099         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3100         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3101         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3102         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3103         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3104         pr_err("VMCB State Save Area:\n");
3105         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3106                "es:",
3107                save->es.selector, save->es.attrib,
3108                save->es.limit, save->es.base);
3109         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3110                "cs:",
3111                save->cs.selector, save->cs.attrib,
3112                save->cs.limit, save->cs.base);
3113         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3114                "ss:",
3115                save->ss.selector, save->ss.attrib,
3116                save->ss.limit, save->ss.base);
3117         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3118                "ds:",
3119                save->ds.selector, save->ds.attrib,
3120                save->ds.limit, save->ds.base);
3121         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3122                "fs:",
3123                save->fs.selector, save->fs.attrib,
3124                save->fs.limit, save->fs.base);
3125         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3126                "gs:",
3127                save->gs.selector, save->gs.attrib,
3128                save->gs.limit, save->gs.base);
3129         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3130                "gdtr:",
3131                save->gdtr.selector, save->gdtr.attrib,
3132                save->gdtr.limit, save->gdtr.base);
3133         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3134                "ldtr:",
3135                save->ldtr.selector, save->ldtr.attrib,
3136                save->ldtr.limit, save->ldtr.base);
3137         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3138                "idtr:",
3139                save->idtr.selector, save->idtr.attrib,
3140                save->idtr.limit, save->idtr.base);
3141         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3142                "tr:",
3143                save->tr.selector, save->tr.attrib,
3144                save->tr.limit, save->tr.base);
3145         pr_err("cpl:            %d                efer:         %016llx\n",
3146                 save->cpl, save->efer);
3147         pr_err("%-15s %016llx %-13s %016llx\n",
3148                "cr0:", save->cr0, "cr2:", save->cr2);
3149         pr_err("%-15s %016llx %-13s %016llx\n",
3150                "cr3:", save->cr3, "cr4:", save->cr4);
3151         pr_err("%-15s %016llx %-13s %016llx\n",
3152                "dr6:", save->dr6, "dr7:", save->dr7);
3153         pr_err("%-15s %016llx %-13s %016llx\n",
3154                "rip:", save->rip, "rflags:", save->rflags);
3155         pr_err("%-15s %016llx %-13s %016llx\n",
3156                "rsp:", save->rsp, "rax:", save->rax);
3157         pr_err("%-15s %016llx %-13s %016llx\n",
3158                "star:", save->star, "lstar:", save->lstar);
3159         pr_err("%-15s %016llx %-13s %016llx\n",
3160                "cstar:", save->cstar, "sfmask:", save->sfmask);
3161         pr_err("%-15s %016llx %-13s %016llx\n",
3162                "kernel_gs_base:", save->kernel_gs_base,
3163                "sysenter_cs:", save->sysenter_cs);
3164         pr_err("%-15s %016llx %-13s %016llx\n",
3165                "sysenter_esp:", save->sysenter_esp,
3166                "sysenter_eip:", save->sysenter_eip);
3167         pr_err("%-15s %016llx %-13s %016llx\n",
3168                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3169         pr_err("%-15s %016llx %-13s %016llx\n",
3170                "br_from:", save->br_from, "br_to:", save->br_to);
3171         pr_err("%-15s %016llx %-13s %016llx\n",
3172                "excp_from:", save->last_excp_from,
3173                "excp_to:", save->last_excp_to);
3174 }
3175
3176 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3177 {
3178         if (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3179             svm_exit_handlers[exit_code])
3180                 return 0;
3181
3182         vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3183         dump_vmcb(vcpu);
3184         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3185         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3186         vcpu->run->internal.ndata = 2;
3187         vcpu->run->internal.data[0] = exit_code;
3188         vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3189
3190         return -EINVAL;
3191 }
3192
3193 int svm_invoke_exit_handler(struct vcpu_svm *svm, u64 exit_code)
3194 {
3195         if (svm_handle_invalid_exit(&svm->vcpu, exit_code))
3196                 return 0;
3197
3198 #ifdef CONFIG_RETPOLINE
3199         if (exit_code == SVM_EXIT_MSR)
3200                 return msr_interception(svm);
3201         else if (exit_code == SVM_EXIT_VINTR)
3202                 return interrupt_window_interception(svm);
3203         else if (exit_code == SVM_EXIT_INTR)
3204                 return intr_interception(svm);
3205         else if (exit_code == SVM_EXIT_HLT)
3206                 return halt_interception(svm);
3207         else if (exit_code == SVM_EXIT_NPF)
3208                 return npf_interception(svm);
3209 #endif
3210         return svm_exit_handlers[exit_code](svm);
3211 }
3212
3213 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2,
3214                               u32 *intr_info, u32 *error_code)
3215 {
3216         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3217
3218         *info1 = control->exit_info_1;
3219         *info2 = control->exit_info_2;
3220         *intr_info = control->exit_int_info;
3221         if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3222             (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3223                 *error_code = control->exit_int_info_err;
3224         else
3225                 *error_code = 0;
3226 }
3227
3228 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3229 {
3230         struct vcpu_svm *svm = to_svm(vcpu);
3231         struct kvm_run *kvm_run = vcpu->run;
3232         u32 exit_code = svm->vmcb->control.exit_code;
3233
3234         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3235
3236         /* SEV-ES guests must use the CR write traps to track CR registers. */
3237         if (!sev_es_guest(vcpu->kvm)) {
3238                 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3239                         vcpu->arch.cr0 = svm->vmcb->save.cr0;
3240                 if (npt_enabled)
3241                         vcpu->arch.cr3 = svm->vmcb->save.cr3;
3242         }
3243
3244         if (is_guest_mode(vcpu)) {
3245                 int vmexit;
3246
3247                 trace_kvm_nested_vmexit(exit_code, vcpu, KVM_ISA_SVM);
3248
3249                 vmexit = nested_svm_exit_special(svm);
3250
3251                 if (vmexit == NESTED_EXIT_CONTINUE)
3252                         vmexit = nested_svm_exit_handled(svm);
3253
3254                 if (vmexit == NESTED_EXIT_DONE)
3255                         return 1;
3256         }
3257
3258         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3259                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3260                 kvm_run->fail_entry.hardware_entry_failure_reason
3261                         = svm->vmcb->control.exit_code;
3262                 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3263                 dump_vmcb(vcpu);
3264                 return 0;
3265         }
3266
3267         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3268             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3269             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3270             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3271                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3272                        "exit_code 0x%x\n",
3273                        __func__, svm->vmcb->control.exit_int_info,
3274                        exit_code);
3275
3276         if (exit_fastpath != EXIT_FASTPATH_NONE)
3277                 return 1;
3278
3279         return svm_invoke_exit_handler(svm, exit_code);
3280 }
3281
3282 static void reload_tss(struct kvm_vcpu *vcpu)
3283 {
3284         struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3285
3286         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3287         load_TR_desc();
3288 }
3289
3290 static void pre_svm_run(struct vcpu_svm *svm)
3291 {
3292         struct svm_cpu_data *sd = per_cpu(svm_data, svm->vcpu.cpu);
3293
3294         if (sev_guest(svm->vcpu.kvm))
3295                 return pre_sev_run(svm, svm->vcpu.cpu);
3296
3297         /* FIXME: handle wraparound of asid_generation */
3298         if (svm->asid_generation != sd->asid_generation)
3299                 new_asid(svm, sd);
3300 }
3301
3302 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3303 {
3304         struct vcpu_svm *svm = to_svm(vcpu);
3305
3306         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3307         vcpu->arch.hflags |= HF_NMI_MASK;
3308         if (!sev_es_guest(svm->vcpu.kvm))
3309                 svm_set_intercept(svm, INTERCEPT_IRET);
3310         ++vcpu->stat.nmi_injections;
3311 }
3312
3313 static void svm_set_irq(struct kvm_vcpu *vcpu)
3314 {
3315         struct vcpu_svm *svm = to_svm(vcpu);
3316
3317         BUG_ON(!(gif_set(svm)));
3318
3319         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3320         ++vcpu->stat.irq_injections;
3321
3322         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3323                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3324 }
3325
3326 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3327 {
3328         struct vcpu_svm *svm = to_svm(vcpu);
3329
3330         /*
3331          * SEV-ES guests must always keep the CR intercepts cleared. CR
3332          * tracking is done using the CR write traps.
3333          */
3334         if (sev_es_guest(vcpu->kvm))
3335                 return;
3336
3337         if (nested_svm_virtualize_tpr(vcpu))
3338                 return;
3339
3340         svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3341
3342         if (irr == -1)
3343                 return;
3344
3345         if (tpr >= irr)
3346                 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3347 }
3348
3349 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3350 {
3351         struct vcpu_svm *svm = to_svm(vcpu);
3352         struct vmcb *vmcb = svm->vmcb;
3353         bool ret;
3354
3355         if (!gif_set(svm))
3356                 return true;
3357
3358         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3359                 return false;
3360
3361         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3362               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3363
3364         return ret;
3365 }
3366
3367 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3368 {
3369         struct vcpu_svm *svm = to_svm(vcpu);
3370         if (svm->nested.nested_run_pending)
3371                 return -EBUSY;
3372
3373         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3374         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3375                 return -EBUSY;
3376
3377         return !svm_nmi_blocked(vcpu);
3378 }
3379
3380 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3381 {
3382         struct vcpu_svm *svm = to_svm(vcpu);
3383
3384         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3385 }
3386
3387 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3388 {
3389         struct vcpu_svm *svm = to_svm(vcpu);
3390
3391         if (masked) {
3392                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3393                 if (!sev_es_guest(svm->vcpu.kvm))
3394                         svm_set_intercept(svm, INTERCEPT_IRET);
3395         } else {
3396                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3397                 if (!sev_es_guest(svm->vcpu.kvm))
3398                         svm_clr_intercept(svm, INTERCEPT_IRET);
3399         }
3400 }
3401
3402 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3403 {
3404         struct vcpu_svm *svm = to_svm(vcpu);
3405         struct vmcb *vmcb = svm->vmcb;
3406
3407         if (!gif_set(svm))
3408                 return true;
3409
3410         if (sev_es_guest(svm->vcpu.kvm)) {
3411                 /*
3412                  * SEV-ES guests to not expose RFLAGS. Use the VMCB interrupt mask
3413                  * bit to determine the state of the IF flag.
3414                  */
3415                 if (!(vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK))
3416                         return true;
3417         } else if (is_guest_mode(vcpu)) {
3418                 /* As long as interrupts are being delivered...  */
3419                 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3420                     ? !(svm->nested.hsave->save.rflags & X86_EFLAGS_IF)
3421                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3422                         return true;
3423
3424                 /* ... vmexits aren't blocked by the interrupt shadow  */
3425                 if (nested_exit_on_intr(svm))
3426                         return false;
3427         } else {
3428                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3429                         return true;
3430         }
3431
3432         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3433 }
3434
3435 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3436 {
3437         struct vcpu_svm *svm = to_svm(vcpu);
3438         if (svm->nested.nested_run_pending)
3439                 return -EBUSY;
3440
3441         /*
3442          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3443          * e.g. if the IRQ arrived asynchronously after checking nested events.
3444          */
3445         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3446                 return -EBUSY;
3447
3448         return !svm_interrupt_blocked(vcpu);
3449 }
3450
3451 static void enable_irq_window(struct kvm_vcpu *vcpu)
3452 {
3453         struct vcpu_svm *svm = to_svm(vcpu);
3454
3455         /*
3456          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3457          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3458          * get that intercept, this function will be called again though and
3459          * we'll get the vintr intercept. However, if the vGIF feature is
3460          * enabled, the STGI interception will not occur. Enable the irq
3461          * window under the assumption that the hardware will set the GIF.
3462          */
3463         if (vgif_enabled(svm) || gif_set(svm)) {
3464                 /*
3465                  * IRQ window is not needed when AVIC is enabled,
3466                  * unless we have pending ExtINT since it cannot be injected
3467                  * via AVIC. In such case, we need to temporarily disable AVIC,
3468                  * and fallback to injecting IRQ via V_IRQ.
3469                  */
3470                 svm_toggle_avic_for_irq_window(vcpu, false);
3471                 svm_set_vintr(svm);
3472         }
3473 }
3474
3475 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3476 {
3477         struct vcpu_svm *svm = to_svm(vcpu);
3478
3479         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3480             == HF_NMI_MASK)
3481                 return; /* IRET will cause a vm exit */
3482
3483         if (!gif_set(svm)) {
3484                 if (vgif_enabled(svm))
3485                         svm_set_intercept(svm, INTERCEPT_STGI);
3486                 return; /* STGI will cause a vm exit */
3487         }
3488
3489         /*
3490          * Something prevents NMI from been injected. Single step over possible
3491          * problem (IRET or exception injection or interrupt shadow)
3492          */
3493         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3494         svm->nmi_singlestep = true;
3495         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3496 }
3497
3498 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3499 {
3500         return 0;
3501 }
3502
3503 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3504 {
3505         return 0;
3506 }
3507
3508 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3509 {
3510         struct vcpu_svm *svm = to_svm(vcpu);
3511
3512         /*
3513          * Flush only the current ASID even if the TLB flush was invoked via
3514          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3515          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3516          * unconditionally does a TLB flush on both nested VM-Enter and nested
3517          * VM-Exit (via kvm_mmu_reset_context()).
3518          */
3519         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3520                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3521         else
3522                 svm->asid_generation--;
3523 }
3524
3525 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3526 {
3527         struct vcpu_svm *svm = to_svm(vcpu);
3528
3529         invlpga(gva, svm->vmcb->control.asid);
3530 }
3531
3532 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3533 {
3534 }
3535
3536 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3537 {
3538         struct vcpu_svm *svm = to_svm(vcpu);
3539
3540         if (nested_svm_virtualize_tpr(vcpu))
3541                 return;
3542
3543         if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3544                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3545                 kvm_set_cr8(vcpu, cr8);
3546         }
3547 }
3548
3549 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3550 {
3551         struct vcpu_svm *svm = to_svm(vcpu);
3552         u64 cr8;
3553
3554         if (nested_svm_virtualize_tpr(vcpu) ||
3555             kvm_vcpu_apicv_active(vcpu))
3556                 return;
3557
3558         cr8 = kvm_get_cr8(vcpu);
3559         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3560         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3561 }
3562
3563 static void svm_complete_interrupts(struct vcpu_svm *svm)
3564 {
3565         u8 vector;
3566         int type;
3567         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3568         unsigned int3_injected = svm->int3_injected;
3569
3570         svm->int3_injected = 0;
3571
3572         /*
3573          * If we've made progress since setting HF_IRET_MASK, we've
3574          * executed an IRET and can allow NMI injection.
3575          */
3576         if ((svm->vcpu.arch.hflags & HF_IRET_MASK) &&
3577             (sev_es_guest(svm->vcpu.kvm) ||
3578              kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip)) {
3579                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3580                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3581         }
3582
3583         svm->vcpu.arch.nmi_injected = false;
3584         kvm_clear_exception_queue(&svm->vcpu);
3585         kvm_clear_interrupt_queue(&svm->vcpu);
3586
3587         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3588                 return;
3589
3590         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3591
3592         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3593         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3594
3595         switch (type) {
3596         case SVM_EXITINTINFO_TYPE_NMI:
3597                 svm->vcpu.arch.nmi_injected = true;
3598                 break;
3599         case SVM_EXITINTINFO_TYPE_EXEPT:
3600                 /*
3601                  * Never re-inject a #VC exception.
3602                  */
3603                 if (vector == X86_TRAP_VC)
3604                         break;
3605
3606                 /*
3607                  * In case of software exceptions, do not reinject the vector,
3608                  * but re-execute the instruction instead. Rewind RIP first
3609                  * if we emulated INT3 before.
3610                  */
3611                 if (kvm_exception_is_soft(vector)) {
3612                         if (vector == BP_VECTOR && int3_injected &&
3613                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3614                                 kvm_rip_write(&svm->vcpu,
3615                                               kvm_rip_read(&svm->vcpu) -
3616                                               int3_injected);
3617                         break;
3618                 }
3619                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3620                         u32 err = svm->vmcb->control.exit_int_info_err;
3621                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3622
3623                 } else
3624                         kvm_requeue_exception(&svm->vcpu, vector);
3625                 break;
3626         case SVM_EXITINTINFO_TYPE_INTR:
3627                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3628                 break;
3629         default:
3630                 break;
3631         }
3632 }
3633
3634 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3635 {
3636         struct vcpu_svm *svm = to_svm(vcpu);
3637         struct vmcb_control_area *control = &svm->vmcb->control;
3638
3639         control->exit_int_info = control->event_inj;
3640         control->exit_int_info_err = control->event_inj_err;
3641         control->event_inj = 0;
3642         svm_complete_interrupts(svm);
3643 }
3644
3645 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3646 {
3647         if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3648             to_svm(vcpu)->vmcb->control.exit_info_1)
3649                 return handle_fastpath_set_msr_irqoff(vcpu);
3650
3651         return EXIT_FASTPATH_NONE;
3652 }
3653
3654 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3655
3656 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu,
3657                                         struct vcpu_svm *svm)
3658 {
3659         /*
3660          * VMENTER enables interrupts (host state), but the kernel state is
3661          * interrupts disabled when this is invoked. Also tell RCU about
3662          * it. This is the same logic as for exit_to_user_mode().
3663          *
3664          * This ensures that e.g. latency analysis on the host observes
3665          * guest mode as interrupt enabled.
3666          *
3667          * guest_enter_irqoff() informs context tracking about the
3668          * transition to guest mode and if enabled adjusts RCU state
3669          * accordingly.
3670          */
3671         instrumentation_begin();
3672         trace_hardirqs_on_prepare();
3673         lockdep_hardirqs_on_prepare(CALLER_ADDR0);
3674         instrumentation_end();
3675
3676         guest_enter_irqoff();
3677         lockdep_hardirqs_on(CALLER_ADDR0);
3678
3679         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3680
3681 #ifdef CONFIG_X86_64
3682         native_wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3683 #else
3684         loadsegment(fs, svm->host.fs);
3685 #ifndef CONFIG_X86_32_LAZY_GS
3686         loadsegment(gs, svm->host.gs);
3687 #endif
3688 #endif
3689
3690         /*
3691          * VMEXIT disables interrupts (host state), but tracing and lockdep
3692          * have them in state 'on' as recorded before entering guest mode.
3693          * Same as enter_from_user_mode().
3694          *
3695          * guest_exit_irqoff() restores host context and reinstates RCU if
3696          * enabled and required.
3697          *
3698          * This needs to be done before the below as native_read_msr()
3699          * contains a tracepoint and x86_spec_ctrl_restore_host() calls
3700          * into world and some more.
3701          */
3702         lockdep_hardirqs_off(CALLER_ADDR0);
3703         guest_exit_irqoff();
3704
3705         instrumentation_begin();
3706         trace_hardirqs_off_finish();
3707         instrumentation_end();
3708 }
3709
3710 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3711 {
3712         struct vcpu_svm *svm = to_svm(vcpu);
3713
3714         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3715         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3716         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3717
3718         /*
3719          * Disable singlestep if we're injecting an interrupt/exception.
3720          * We don't want our modified rflags to be pushed on the stack where
3721          * we might not be able to easily reset them if we disabled NMI
3722          * singlestep later.
3723          */
3724         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3725                 /*
3726                  * Event injection happens before external interrupts cause a
3727                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3728                  * is enough to force an immediate vmexit.
3729                  */
3730                 disable_nmi_singlestep(svm);
3731                 smp_send_reschedule(vcpu->cpu);
3732         }
3733
3734         pre_svm_run(svm);
3735
3736         sync_lapic_to_cr8(vcpu);
3737
3738         if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3739                 svm->vmcb->control.asid = svm->asid;
3740                 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3741         }
3742         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3743
3744         /*
3745          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3746          * of a #DB.
3747          */
3748         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3749                 svm_set_dr6(svm, vcpu->arch.dr6);
3750         else
3751                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3752
3753         clgi();
3754         kvm_load_guest_xsave_state(vcpu);
3755
3756         kvm_wait_lapic_expire(vcpu);
3757
3758         /*
3759          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3760          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3761          * is no need to worry about the conditional branch over the wrmsr
3762          * being speculatively taken.
3763          */
3764         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3765
3766         svm_vcpu_enter_exit(vcpu, svm);
3767
3768         /*
3769          * We do not use IBRS in the kernel. If this vCPU has used the
3770          * SPEC_CTRL MSR it may have left it on; save the value and
3771          * turn it off. This is much more efficient than blindly adding
3772          * it to the atomic save/restore list. Especially as the former
3773          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3774          *
3775          * For non-nested case:
3776          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3777          * save it.
3778          *
3779          * For nested case:
3780          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3781          * save it.
3782          */
3783         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3784                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3785
3786         reload_tss(vcpu);
3787
3788         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3789
3790         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3791         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3792         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3793         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3794
3795         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3796                 kvm_before_interrupt(&svm->vcpu);
3797
3798         kvm_load_host_xsave_state(vcpu);
3799         stgi();
3800
3801         /* Any pending NMI will happen here */
3802
3803         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3804                 kvm_after_interrupt(&svm->vcpu);
3805
3806         sync_cr8_to_lapic(vcpu);
3807
3808         svm->next_rip = 0;
3809         if (is_guest_mode(&svm->vcpu)) {
3810                 sync_nested_vmcb_control(svm);
3811                 svm->nested.nested_run_pending = 0;
3812         }
3813
3814         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3815         vmcb_mark_all_clean(svm->vmcb);
3816
3817         /* if exit due to PF check for async PF */
3818         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3819                 svm->vcpu.arch.apf.host_apf_flags =
3820                         kvm_read_and_reset_apf_flags();
3821
3822         if (npt_enabled) {
3823                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3824                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3825         }
3826
3827         /*
3828          * We need to handle MC intercepts here before the vcpu has a chance to
3829          * change the physical cpu
3830          */
3831         if (unlikely(svm->vmcb->control.exit_code ==
3832                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3833                 svm_handle_mce(svm);
3834
3835         svm_complete_interrupts(svm);
3836
3837         if (is_guest_mode(vcpu))
3838                 return EXIT_FASTPATH_NONE;
3839
3840         return svm_exit_handlers_fastpath(vcpu);
3841 }
3842
3843 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root,
3844                              int root_level)
3845 {
3846         struct vcpu_svm *svm = to_svm(vcpu);
3847         unsigned long cr3;
3848
3849         cr3 = __sme_set(root);
3850         if (npt_enabled) {
3851                 svm->vmcb->control.nested_cr3 = cr3;
3852                 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
3853
3854                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3855                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3856                         return;
3857                 cr3 = vcpu->arch.cr3;
3858         }
3859
3860         svm->vmcb->save.cr3 = cr3;
3861         vmcb_mark_dirty(svm->vmcb, VMCB_CR);
3862 }
3863
3864 static int is_disabled(void)
3865 {
3866         u64 vm_cr;
3867
3868         rdmsrl(MSR_VM_CR, vm_cr);
3869         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3870                 return 1;
3871
3872         return 0;
3873 }
3874
3875 static void
3876 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3877 {
3878         /*
3879          * Patch in the VMMCALL instruction:
3880          */
3881         hypercall[0] = 0x0f;
3882         hypercall[1] = 0x01;
3883         hypercall[2] = 0xd9;
3884 }
3885
3886 static int __init svm_check_processor_compat(void)
3887 {
3888         return 0;
3889 }
3890
3891 static bool svm_cpu_has_accelerated_tpr(void)
3892 {
3893         return false;
3894 }
3895
3896 /*
3897  * The kvm parameter can be NULL (module initialization, or invocation before
3898  * VM creation). Be sure to check the kvm parameter before using it.
3899  */
3900 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
3901 {
3902         switch (index) {
3903         case MSR_IA32_MCG_EXT_CTL:
3904         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3905                 return false;
3906         case MSR_IA32_SMBASE:
3907                 /* SEV-ES guests do not support SMM, so report false */
3908                 if (kvm && sev_es_guest(kvm))
3909                         return false;
3910                 break;
3911         default:
3912                 break;
3913         }
3914
3915         return true;
3916 }
3917
3918 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3919 {
3920         return 0;
3921 }
3922
3923 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
3924 {
3925         struct vcpu_svm *svm = to_svm(vcpu);
3926         struct kvm_cpuid_entry2 *best;
3927
3928         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3929                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3930                                     boot_cpu_has(X86_FEATURE_XSAVES);
3931
3932         /* Update nrips enabled cache */
3933         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3934                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3935
3936         /* Check again if INVPCID interception if required */
3937         svm_check_invpcid(svm);
3938
3939         /* For sev guests, the memory encryption bit is not reserved in CR3.  */
3940         if (sev_guest(vcpu->kvm)) {
3941                 best = kvm_find_cpuid_entry(vcpu, 0x8000001F, 0);
3942                 if (best)
3943                         vcpu->arch.cr3_lm_rsvd_bits &= ~(1UL << (best->ebx & 0x3f));
3944         }
3945
3946         if (!kvm_vcpu_apicv_active(vcpu))
3947                 return;
3948
3949         /*
3950          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3951          * is exposed to the guest, disable AVIC.
3952          */
3953         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3954                 kvm_request_apicv_update(vcpu->kvm, false,
3955                                          APICV_INHIBIT_REASON_X2APIC);
3956
3957         /*
3958          * Currently, AVIC does not work with nested virtualization.
3959          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3960          */
3961         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3962                 kvm_request_apicv_update(vcpu->kvm, false,
3963                                          APICV_INHIBIT_REASON_NESTED);
3964 }
3965
3966 static bool svm_has_wbinvd_exit(void)
3967 {
3968         return true;
3969 }
3970
3971 #define PRE_EX(exit)  { .exit_code = (exit), \
3972                         .stage = X86_ICPT_PRE_EXCEPT, }
3973 #define POST_EX(exit) { .exit_code = (exit), \
3974                         .stage = X86_ICPT_POST_EXCEPT, }
3975 #define POST_MEM(exit) { .exit_code = (exit), \
3976                         .stage = X86_ICPT_POST_MEMACCESS, }
3977
3978 static const struct __x86_intercept {
3979         u32 exit_code;
3980         enum x86_intercept_stage stage;
3981 } x86_intercept_map[] = {
3982         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3983         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3984         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3985         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3986         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3987         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3988         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3989         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3990         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3991         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3992         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3993         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3994         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3995         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3996         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3997         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3998         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3999         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
4000         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
4001         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
4002         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
4003         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
4004         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
4005         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
4006         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
4007         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
4008         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
4009         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
4010         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
4011         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
4012         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
4013         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
4014         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
4015         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
4016         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
4017         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
4018         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
4019         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
4020         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
4021         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
4022         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
4023         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
4024         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
4025         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
4026         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
4027         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
4028         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
4029 };
4030
4031 #undef PRE_EX
4032 #undef POST_EX
4033 #undef POST_MEM
4034
4035 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4036                                struct x86_instruction_info *info,
4037                                enum x86_intercept_stage stage,
4038                                struct x86_exception *exception)
4039 {
4040         struct vcpu_svm *svm = to_svm(vcpu);
4041         int vmexit, ret = X86EMUL_CONTINUE;
4042         struct __x86_intercept icpt_info;
4043         struct vmcb *vmcb = svm->vmcb;
4044
4045         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4046                 goto out;
4047
4048         icpt_info = x86_intercept_map[info->intercept];
4049
4050         if (stage != icpt_info.stage)
4051                 goto out;
4052
4053         switch (icpt_info.exit_code) {
4054         case SVM_EXIT_READ_CR0:
4055                 if (info->intercept == x86_intercept_cr_read)
4056                         icpt_info.exit_code += info->modrm_reg;
4057                 break;
4058         case SVM_EXIT_WRITE_CR0: {
4059                 unsigned long cr0, val;
4060
4061                 if (info->intercept == x86_intercept_cr_write)
4062                         icpt_info.exit_code += info->modrm_reg;
4063
4064                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4065                     info->intercept == x86_intercept_clts)
4066                         break;
4067
4068                 if (!(vmcb_is_intercept(&svm->nested.ctl,
4069                                         INTERCEPT_SELECTIVE_CR0)))
4070                         break;
4071
4072                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4073                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
4074
4075                 if (info->intercept == x86_intercept_lmsw) {
4076                         cr0 &= 0xfUL;
4077                         val &= 0xfUL;
4078                         /* lmsw can't clear PE - catch this here */
4079                         if (cr0 & X86_CR0_PE)
4080                                 val |= X86_CR0_PE;
4081                 }
4082
4083                 if (cr0 ^ val)
4084                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4085
4086                 break;
4087         }
4088         case SVM_EXIT_READ_DR0:
4089         case SVM_EXIT_WRITE_DR0:
4090                 icpt_info.exit_code += info->modrm_reg;
4091                 break;
4092         case SVM_EXIT_MSR:
4093                 if (info->intercept == x86_intercept_wrmsr)
4094                         vmcb->control.exit_info_1 = 1;
4095                 else
4096                         vmcb->control.exit_info_1 = 0;
4097                 break;
4098         case SVM_EXIT_PAUSE:
4099                 /*
4100                  * We get this for NOP only, but pause
4101                  * is rep not, check this here
4102                  */
4103                 if (info->rep_prefix != REPE_PREFIX)
4104                         goto out;
4105                 break;
4106         case SVM_EXIT_IOIO: {
4107                 u64 exit_info;
4108                 u32 bytes;
4109
4110                 if (info->intercept == x86_intercept_in ||
4111                     info->intercept == x86_intercept_ins) {
4112                         exit_info = ((info->src_val & 0xffff) << 16) |
4113                                 SVM_IOIO_TYPE_MASK;
4114                         bytes = info->dst_bytes;
4115                 } else {
4116                         exit_info = (info->dst_val & 0xffff) << 16;
4117                         bytes = info->src_bytes;
4118                 }
4119
4120                 if (info->intercept == x86_intercept_outs ||
4121                     info->intercept == x86_intercept_ins)
4122                         exit_info |= SVM_IOIO_STR_MASK;
4123
4124                 if (info->rep_prefix)
4125                         exit_info |= SVM_IOIO_REP_MASK;
4126
4127                 bytes = min(bytes, 4u);
4128
4129                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4130
4131                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4132
4133                 vmcb->control.exit_info_1 = exit_info;
4134                 vmcb->control.exit_info_2 = info->next_rip;
4135
4136                 break;
4137         }
4138         default:
4139                 break;
4140         }
4141
4142         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4143         if (static_cpu_has(X86_FEATURE_NRIPS))
4144                 vmcb->control.next_rip  = info->next_rip;
4145         vmcb->control.exit_code = icpt_info.exit_code;
4146         vmexit = nested_svm_exit_handled(svm);
4147
4148         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4149                                            : X86EMUL_CONTINUE;
4150
4151 out:
4152         return ret;
4153 }
4154
4155 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4156 {
4157 }
4158
4159 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4160 {
4161         if (!kvm_pause_in_guest(vcpu->kvm))
4162                 shrink_ple_window(vcpu);
4163 }
4164
4165 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4166 {
4167         /* [63:9] are reserved. */
4168         vcpu->arch.mcg_cap &= 0x1ff;
4169 }
4170
4171 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4172 {
4173         struct vcpu_svm *svm = to_svm(vcpu);
4174
4175         /* Per APM Vol.2 15.22.2 "Response to SMI" */
4176         if (!gif_set(svm))
4177                 return true;
4178
4179         return is_smm(vcpu);
4180 }
4181
4182 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4183 {
4184         struct vcpu_svm *svm = to_svm(vcpu);
4185         if (svm->nested.nested_run_pending)
4186                 return -EBUSY;
4187
4188         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
4189         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4190                 return -EBUSY;
4191
4192         return !svm_smi_blocked(vcpu);
4193 }
4194
4195 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4196 {
4197         struct vcpu_svm *svm = to_svm(vcpu);
4198         int ret;
4199
4200         if (is_guest_mode(vcpu)) {
4201                 /* FED8h - SVM Guest */
4202                 put_smstate(u64, smstate, 0x7ed8, 1);
4203                 /* FEE0h - SVM Guest VMCB Physical Address */
4204                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4205
4206                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4207                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4208                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4209
4210                 ret = nested_svm_vmexit(svm);
4211                 if (ret)
4212                         return ret;
4213         }
4214         return 0;
4215 }
4216
4217 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4218 {
4219         struct vcpu_svm *svm = to_svm(vcpu);
4220         struct kvm_host_map map;
4221         int ret = 0;
4222
4223         if (guest_cpuid_has(vcpu, X86_FEATURE_LM)) {
4224                 u64 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4225                 u64 guest = GET_SMSTATE(u64, smstate, 0x7ed8);
4226                 u64 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4227
4228                 if (guest) {
4229                         if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4230                                 return 1;
4231
4232                         if (!(saved_efer & EFER_SVME))
4233                                 return 1;
4234
4235                         if (kvm_vcpu_map(&svm->vcpu,
4236                                          gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4237                                 return 1;
4238
4239                         if (svm_allocate_nested(svm))
4240                                 return 1;
4241
4242                         ret = enter_svm_guest_mode(svm, vmcb12_gpa, map.hva);
4243                         kvm_vcpu_unmap(&svm->vcpu, &map, true);
4244                 }
4245         }
4246
4247         return ret;
4248 }
4249
4250 static void enable_smi_window(struct kvm_vcpu *vcpu)
4251 {
4252         struct vcpu_svm *svm = to_svm(vcpu);
4253
4254         if (!gif_set(svm)) {
4255                 if (vgif_enabled(svm))
4256                         svm_set_intercept(svm, INTERCEPT_STGI);
4257                 /* STGI will cause a vm exit */
4258         } else {
4259                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
4260         }
4261 }
4262
4263 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, void *insn, int insn_len)
4264 {
4265         bool smep, smap, is_user;
4266         unsigned long cr4;
4267
4268         /*
4269          * When the guest is an SEV-ES guest, emulation is not possible.
4270          */
4271         if (sev_es_guest(vcpu->kvm))
4272                 return false;
4273
4274         /*
4275          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4276          *
4277          * Errata:
4278          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
4279          * possible that CPU microcode implementing DecodeAssist will fail
4280          * to read bytes of instruction which caused #NPF. In this case,
4281          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
4282          * return 0 instead of the correct guest instruction bytes.
4283          *
4284          * This happens because CPU microcode reading instruction bytes
4285          * uses a special opcode which attempts to read data using CPL=0
4286          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
4287          * fault, it gives up and returns no instruction bytes.
4288          *
4289          * Detection:
4290          * We reach here in case CPU supports DecodeAssist, raised #NPF and
4291          * returned 0 in GuestIntrBytes field of the VMCB.
4292          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
4293          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
4294          * in case vCPU CPL==3 (Because otherwise guest would have triggered
4295          * a SMEP fault instead of #NPF).
4296          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
4297          * As most guests enable SMAP if they have also enabled SMEP, use above
4298          * logic in order to attempt minimize false-positive of detecting errata
4299          * while still preserving all cases semantic correctness.
4300          *
4301          * Workaround:
4302          * To determine what instruction the guest was executing, the hypervisor
4303          * will have to decode the instruction at the instruction pointer.
4304          *
4305          * In non SEV guest, hypervisor will be able to read the guest
4306          * memory to decode the instruction pointer when insn_len is zero
4307          * so we return true to indicate that decoding is possible.
4308          *
4309          * But in the SEV guest, the guest memory is encrypted with the
4310          * guest specific key and hypervisor will not be able to decode the
4311          * instruction pointer so we will not able to workaround it. Lets
4312          * print the error and request to kill the guest.
4313          */
4314         if (likely(!insn || insn_len))
4315                 return true;
4316
4317         /*
4318          * If RIP is invalid, go ahead with emulation which will cause an
4319          * internal error exit.
4320          */
4321         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
4322                 return true;
4323
4324         cr4 = kvm_read_cr4(vcpu);
4325         smep = cr4 & X86_CR4_SMEP;
4326         smap = cr4 & X86_CR4_SMAP;
4327         is_user = svm_get_cpl(vcpu) == 3;
4328         if (smap && (!smep || is_user)) {
4329                 if (!sev_guest(vcpu->kvm))
4330                         return true;
4331
4332                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4333                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4334         }
4335
4336         return false;
4337 }
4338
4339 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4340 {
4341         struct vcpu_svm *svm = to_svm(vcpu);
4342
4343         /*
4344          * TODO: Last condition latch INIT signals on vCPU when
4345          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4346          * To properly emulate the INIT intercept,
4347          * svm_check_nested_events() should call nested_svm_vmexit()
4348          * if an INIT signal is pending.
4349          */
4350         return !gif_set(svm) ||
4351                    (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4352 }
4353
4354 static void svm_vm_destroy(struct kvm *kvm)
4355 {
4356         avic_vm_destroy(kvm);
4357         sev_vm_destroy(kvm);
4358 }
4359
4360 static int svm_vm_init(struct kvm *kvm)
4361 {
4362         if (!pause_filter_count || !pause_filter_thresh)
4363                 kvm->arch.pause_in_guest = true;
4364
4365         if (avic) {
4366                 int ret = avic_vm_init(kvm);
4367                 if (ret)
4368                         return ret;
4369         }
4370
4371         kvm_apicv_init(kvm, avic);
4372         return 0;
4373 }
4374
4375 static struct kvm_x86_ops svm_x86_ops __initdata = {
4376         .hardware_unsetup = svm_hardware_teardown,
4377         .hardware_enable = svm_hardware_enable,
4378         .hardware_disable = svm_hardware_disable,
4379         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
4380         .has_emulated_msr = svm_has_emulated_msr,
4381
4382         .vcpu_create = svm_create_vcpu,
4383         .vcpu_free = svm_free_vcpu,
4384         .vcpu_reset = svm_vcpu_reset,
4385
4386         .vm_size = sizeof(struct kvm_svm),
4387         .vm_init = svm_vm_init,
4388         .vm_destroy = svm_vm_destroy,
4389
4390         .prepare_guest_switch = svm_prepare_guest_switch,
4391         .vcpu_load = svm_vcpu_load,
4392         .vcpu_put = svm_vcpu_put,
4393         .vcpu_blocking = svm_vcpu_blocking,
4394         .vcpu_unblocking = svm_vcpu_unblocking,
4395
4396         .update_exception_bitmap = update_exception_bitmap,
4397         .get_msr_feature = svm_get_msr_feature,
4398         .get_msr = svm_get_msr,
4399         .set_msr = svm_set_msr,
4400         .get_segment_base = svm_get_segment_base,
4401         .get_segment = svm_get_segment,
4402         .set_segment = svm_set_segment,
4403         .get_cpl = svm_get_cpl,
4404         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
4405         .set_cr0 = svm_set_cr0,
4406         .is_valid_cr4 = svm_is_valid_cr4,
4407         .set_cr4 = svm_set_cr4,
4408         .set_efer = svm_set_efer,
4409         .get_idt = svm_get_idt,
4410         .set_idt = svm_set_idt,
4411         .get_gdt = svm_get_gdt,
4412         .set_gdt = svm_set_gdt,
4413         .set_dr7 = svm_set_dr7,
4414         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4415         .cache_reg = svm_cache_reg,
4416         .get_rflags = svm_get_rflags,
4417         .set_rflags = svm_set_rflags,
4418
4419         .tlb_flush_all = svm_flush_tlb,
4420         .tlb_flush_current = svm_flush_tlb,
4421         .tlb_flush_gva = svm_flush_tlb_gva,
4422         .tlb_flush_guest = svm_flush_tlb,
4423
4424         .run = svm_vcpu_run,
4425         .handle_exit = handle_exit,
4426         .skip_emulated_instruction = skip_emulated_instruction,
4427         .update_emulated_instruction = NULL,
4428         .set_interrupt_shadow = svm_set_interrupt_shadow,
4429         .get_interrupt_shadow = svm_get_interrupt_shadow,
4430         .patch_hypercall = svm_patch_hypercall,
4431         .set_irq = svm_set_irq,
4432         .set_nmi = svm_inject_nmi,
4433         .queue_exception = svm_queue_exception,
4434         .cancel_injection = svm_cancel_injection,
4435         .interrupt_allowed = svm_interrupt_allowed,
4436         .nmi_allowed = svm_nmi_allowed,
4437         .get_nmi_mask = svm_get_nmi_mask,
4438         .set_nmi_mask = svm_set_nmi_mask,
4439         .enable_nmi_window = enable_nmi_window,
4440         .enable_irq_window = enable_irq_window,
4441         .update_cr8_intercept = update_cr8_intercept,
4442         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4443         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4444         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4445         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4446         .load_eoi_exitmap = svm_load_eoi_exitmap,
4447         .hwapic_irr_update = svm_hwapic_irr_update,
4448         .hwapic_isr_update = svm_hwapic_isr_update,
4449         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4450         .apicv_post_state_restore = avic_post_state_restore,
4451
4452         .set_tss_addr = svm_set_tss_addr,
4453         .set_identity_map_addr = svm_set_identity_map_addr,
4454         .get_mt_mask = svm_get_mt_mask,
4455
4456         .get_exit_info = svm_get_exit_info,
4457
4458         .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4459
4460         .has_wbinvd_exit = svm_has_wbinvd_exit,
4461
4462         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4463
4464         .load_mmu_pgd = svm_load_mmu_pgd,
4465
4466         .check_intercept = svm_check_intercept,
4467         .handle_exit_irqoff = svm_handle_exit_irqoff,
4468
4469         .request_immediate_exit = __kvm_request_immediate_exit,
4470
4471         .sched_in = svm_sched_in,
4472
4473         .pmu_ops = &amd_pmu_ops,
4474         .nested_ops = &svm_nested_ops,
4475
4476         .deliver_posted_interrupt = svm_deliver_avic_intr,
4477         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4478         .update_pi_irte = svm_update_pi_irte,
4479         .setup_mce = svm_setup_mce,
4480
4481         .smi_allowed = svm_smi_allowed,
4482         .pre_enter_smm = svm_pre_enter_smm,
4483         .pre_leave_smm = svm_pre_leave_smm,
4484         .enable_smi_window = enable_smi_window,
4485
4486         .mem_enc_op = svm_mem_enc_op,
4487         .mem_enc_reg_region = svm_register_enc_region,
4488         .mem_enc_unreg_region = svm_unregister_enc_region,
4489
4490         .can_emulate_instruction = svm_can_emulate_instruction,
4491
4492         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4493
4494         .msr_filter_changed = svm_msr_filter_changed,
4495         .complete_emulated_msr = svm_complete_emulated_msr,
4496 };
4497
4498 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4499         .cpu_has_kvm_support = has_svm,
4500         .disabled_by_bios = is_disabled,
4501         .hardware_setup = svm_hardware_setup,
4502         .check_processor_compatibility = svm_check_processor_compat,
4503
4504         .runtime_ops = &svm_x86_ops,
4505 };
4506
4507 static int __init svm_init(void)
4508 {
4509         __unused_size_checks();
4510
4511         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4512                         __alignof__(struct vcpu_svm), THIS_MODULE);
4513 }
4514
4515 static void __exit svm_exit(void)
4516 {
4517         kvm_exit();
4518 }
4519
4520 module_init(svm_init)
4521 module_exit(svm_exit)